CN1049763C - 形成半导体器件金属互连的方法 - Google Patents

形成半导体器件金属互连的方法 Download PDF

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CN1049763C
CN1049763C CN95109442A CN95109442A CN1049763C CN 1049763 C CN1049763 C CN 1049763C CN 95109442 A CN95109442 A CN 95109442A CN 95109442 A CN95109442 A CN 95109442A CN 1049763 C CN1049763 C CN 1049763C
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insulating barrier
layer
metal layer
metal
barrier
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CN1115117A (zh
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朴相勋
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MagnaChip Semiconductor Ltd
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/943—Movable
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种形成半导体器件金属互连的方法，其在第一绝缘层中形成通孔，连接第一金属层和第一绝缘层，第二金属层位于非第一金属层的层上，包括：第一步，形成大小与第一金属层上的第一绝缘层的通孔尺寸相同的第二绝缘层；第二步，形成腐蚀阻挡层，以便覆盖第二绝缘层用于形成第一金属层的图形；第三步，使用腐蚀阻挡层做腐蚀掩膜来腐蚀第一绝缘层和第一金属层；第四步，形成第三绝缘层，平面化所得结构，露出第二绝缘层；第五步，去除该第二绝缘层；第六步，形成第二金属层。

Description

形成半导体器件金属互连的方法
本发明涉及在制造半导体器件过程中，形成连接不同层上的金属层的金属互连的方法。
下面结合图1介绍现有技术形成金属互连的方法。
图1为金属互连形成后半导体器件的剖面图。
首先，在衬底1上形成场氧化层2，然后在整个衬底表面形成BPSG(硼磷硅玻璃)膜3。具有预定图形的第一金属层4形成在BPSG膜3上，第一绝缘层5和第二绝缘层6依次淀积在BPSG膜3及第一金属层4上。第一绝缘层5和第二绝缘层6的预定部分被选择性地腐蚀形成通孔。第二金属层7淀积在第二绝缘层6上填充所述通孔，然后进行腐蚀，从而形成金属互连。
但是现行方法也存在着问题，当腐蚀绝缘层时，具有相对较高台阶的场氧化层上形成的第一金属层表面会受到等离子腐蚀的损害，从而形成厚厚一层自然氧化膜。
本发明的目的在于提供一种在形成通孔时，能将等离子腐蚀对具有相对较高台阶的金属层的损害减小到最小的形成金属互连的方法。
本发明的这些和其他目的和特点可通过以下形成半导体器件的金属互连的方法得到。其中形成第一金属层和第一绝缘层，并在第一绝缘层中形成通孔，通过该通孔连接第一金属层和第二金属层，第二金属层位于与第一金属层不同的层上，包括：第一步，形成大小与第一金属层上的第一绝缘层的通孔尺寸相同的第二绝缘层；第二步，形成腐蚀阻挡层，以便覆盖第二绝缘层用于形成第一金属层的图形；第三步，使用腐蚀阻挡层做腐蚀掩膜来腐蚀第一绝缘层和第一金属层然后去除腐蚀阻挡层；第四步，在第一步到第三步所得结构上形成第三绝缘层，平面化所得结构，以腐蚀所说第三绝缘层，使露出第二绝缘层；第五步，除去露出的第二绝缘层；和通过去除第二绝缘层后露出的第一绝缘层的部分；第六步，在得到的结构上形成第二金属层。
下面结合实施例参考附图对本发明进行说明。
图1为金属互连形成后半导体器件的剖面图。
图2A-2E为分别按照本发明的一个实施例用于形成金属互连的剖面图。
图2A-2E为本发明优选实施例的剖面图，说明形成金属互连的工艺过程。
首先，如图2A所示，在衬底10上形成场氧化层20，然后在整个衬底表面上依次淀积BPSG(硼磷硅玻璃)膜3、第一金属层40、第一绝缘层50和第二绝缘层60，然后在第二绝缘层60上形成第一光刻胶膜图形80。
此后，如图2B所示，使用第一光刻胶图形80作腐蚀阻挡层各向异性腐蚀第二绝缘层60形成通柱60′。然后去掉第一光刻胶图形80，形成第二光刻胶图形90以覆盖通柱60′。
如图2C所示，使用第二光刻胶图形90作腐蚀阻挡层依次各向异性腐蚀第一绝缘层50和第一金属层40，然后去除第二光刻胶图形90。在所得结构上形成平面化氧化膜100。
如图2D所示，腐蚀平面化氧化膜100露出通柱60′。
最后，如图2E所示，通过湿法腐蚀去除通柱60′，然后去除通柱60′下的第一绝缘层50，因此形成通孔。在所得结构上淀积第二金属层70，之后进行腐蚀，从而完成金属互连的制作工艺。
综上所述，本发明在形成通孔时，将等离子腐蚀对具有相对较高台阶的金属层的损害减小到最小，改善了内连层间的连接状况，从而提高了器件的成品率及可靠性。
虽然结合特殊的实施例对本发明进行了介绍，但对本领域的技术人员来说根据以上介绍进行各种替换和变化都是显而易见的。因此各种替换和变化均包括在本发明附属的权利要求所限定的精神和范围内。

Claims (5)

1.一种形成半导体器件金属互连的方法，其中形成第一金属层(40)和第一绝缘层(50)，并在第一绝缘层中形成通孔，通过该通孔连接第一金属层和第二金属层，第二金属层位于与第一金属层不同的层上，包括：
第一步，形成大小与第一金属层上的第一绝缘层的通孔尺寸相同的第二绝缘层(60′)；
第二步，形成腐蚀阻挡层(90)，以便覆盖第二绝缘层用于形成第一金属层的图形；
第三步，使用腐蚀阻挡层做腐蚀掩膜来腐蚀第一绝缘层(50)和第一金属层，然后去除腐蚀阻挡层；
第四步，在第一步到第三步所得结构上形成第三绝缘层，平面化所得结构，以腐蚀所说第三绝缘层，使露出第二绝缘层；
第五步，去除露出的第二绝缘层，和通过去除第二绝缘层后露出的第一绝缘层的部分；
第六步，在得到的结构上形成第二金属层。
2.根据权利要求1的方法，其中，所述第一步包括：
在第一绝缘层上淀积第二绝缘层的工艺；
形成与第一金属层上的第二绝缘层的通孔尺寸相同的光刻胶膜的工艺；以及
使用光刻胶膜作腐蚀阻挡层腐蚀第二绝缘层的工艺。
3.根据权利要求1或2的方法，其中，所述腐蚀阻挡层包括光刻胶膜。
4.根据权利要求3的方法，其中，所述第二绝缘层和第一绝缘层包括具有湿法腐蚀选择性的绝缘膜。
5.根据权利要求4的方法，其中，在去除所述第二绝缘层的第五步中，利用第二绝缘层和第一绝缘层的腐蚀选择性通过湿法腐蚀去除所述第二绝缘层。
CN95109442A 1994-07-07 1995-07-07 形成半导体器件金属互连的方法 Expired - Fee Related CN1049763C (zh)

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