CN1115117A - 形成半导体器件金属互连的方法 - Google Patents

形成半导体器件金属互连的方法 Download PDF

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CN1115117A
CN1115117A CN95109442A CN95109442A CN1115117A CN 1115117 A CN1115117 A CN 1115117A CN 95109442 A CN95109442 A CN 95109442A CN 95109442 A CN95109442 A CN 95109442A CN 1115117 A CN1115117 A CN 1115117A
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insulating barrier
metal layer
etching
metal
hole
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CN1049763C (zh
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朴相勋
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MagnaChip Semiconductor Ltd
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/943—Movable
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种形成半导体器件金属互连的方法，形成第一金属层和第一绝缘层，在第一绝缘层形成通孔，连接第一金属层与第二金属层，第二金属层是固定层，包括，第二绝缘层有一与第一金属层上的第一绝缘层相同的通孔；以第一金属层模型为蚀刻隔板覆盖第二绝缘层；把第一绝缘层和第一金属层用于蚀刻隔板作为蚀刻掩模；由一至三步，在结构上形成平面型第三绝缘层，暴露第二绝缘层；除去暴露的第二绝缘层；形成第二金属层。

Description

形成半导体器件金 属互连的方法
本发明涉及一种半导体器件的制造方法，特别地涉及在半导体器件不同层间金属层相互连接以形成金属互连的方法。
参照附图1对现行的金属互连法予以说明。
图1是形成金属互连后的半导体器件的剖视图。
首先，在基片1上形成场氧化层2，然后在整个基片表面上形成一层BPSG(硼磷硅玻璃)膜3，在BPSG膜3上第一金属层4形成预置模BPSG膜3及第一金属层4上依次淀积第一绝缘层5、第二绝缘层6。第一绝缘层5和第二绝缘层6的预置部分被蚀刻形成通孔(via hole)。第二绝缘层6上淀积第二金属层7，填充上述通孔，然后刻蚀形成金属互连。
但是，现行的方法存在一个问题，即，当绝缘层被蚀刻时，由于等离子体蚀刻的作用，使场氧化层上形成的第一金属层产生更进一步的损害，以致形成厚厚一层自然氧化膜。
有鉴于此，本发明的目的是提供一种形成金属互连的方法，使等离子体蚀刻对金属层的损害作用减少到最小，并且在通孔的形成方面有更进一步的不同。
本发明提供的一种形成半导体器件金属互连的方法，其形成第一金属层和第一绝缘层，并在第一绝缘层形成通孔，连接第一金属层与第二金属层，第二金属层是固定层，其不同于第一金属层。其步骤包括：形成的第一步，第二绝缘层有一通孔，其大小与第一金属层上的第一绝缘层的通孔相同；形成的第二步，以第一金属层模型为蚀刻隔板覆盖第二绝缘层；蚀刻的第三步，以第一绝缘层和第一金属层为蚀刻隔板作蚀刻掩模；形成的第四步，通过第一至第三步，在总体结构上形成平面型第三绝缘层，使第二绝缘层暴露；第五步，除去暴露的第二绝缘层；第六步，形成第二金属层。
为对本发明的目的、特征、优点进行详细说明，在下文中，结合实施例，参考附图予以描述。
附图简要说明：
图1是由金属互连制成的半导体器件的剖视图。
图2A-2E是分别根据本发明最佳实施例形成金属互连过程的剖视图。
图2A-2E是本发明最佳实施例的剖视图，说明形成金属互连的工艺过程。
首先，如图2A所示，基片10上形成场氧化层20，在整个基片表面有一层BPSG膜30，依次淀积第一金属层40、第一绝缘层50及第二绝缘层60，然后在第二绝缘层60上形成第一感光膜模型80。
其次，如图2B所示，用第一感光膜模型80作蚀刻隔板，各向异性蚀刻第二绝缘层60，使其形成通柱(via bar)60′。然后，除去第一感光膜模型80，形成第二感光膜模型90并覆盖通柱60′。
如图2C所示，用第二感光膜模型90作蚀刻隔板，各向异性依次蚀刻第一绝缘层50和第一金属层40，然后，除去第二感光膜模型90在总体结构上形成平面型氧化膜100。
如图2D所示，平面型氧化膜100的上部被蚀刻，使通柱60′外露。
最后，如图2E所示，用湿蚀刻法除去通柱60′然后除去通柱60′下面的第一绝缘层50，由此形成通孔，总体结构之上淀积第二金属层70，然后蚀刻，最终完成金属互连的制作过程。
综上所述，本发明使等离子蚀刻对金属层损害作用减少到最小，在形成通孔方面，进一步改进了连接层间的连接状况，使本器件的成品率及可靠性都得到提高。
虽然上述已结合实施例对本发明进行了说明，本技术领域的人员对以上所述内容可以进行各种更改，但是，各种替换及更改均包括在本发明权利要求所限定的构思及范围之内。

Claims (5)

1、一种形成半导体器件金属互连的方法，其形成第一金属层和第一绝缘层，在第一绝缘层形成通孔，连接第一金属层与第二金属层，第二金属层是固定层，其不同于第一金属层，其步骤包括：
第一步，第二绝缘层有一通孔，其大小与第一金属层上的第一绝缘层的通孔相同；
第二步，以第一金属层模型为蚀刻隔板，覆盖第二绝缘层；
第三步，把第一绝缘层和第一金属层用于蚀刻隔板作蚀刻掩膜；
第四步，通过第一至第三步，在总体结构上形成平面型第三绝缘层，使第二绝缘层暴露；
第五步，除去暴露的第二绝缘层；
第六步，形成第二金属层。
2、根据权利要求1所述方法，其中，所述第一步包括：
在第一绝缘层上淀积第二绝缘层；
感光膜上有一通孔，其大小与第一金属层上的第二绝缘层的通孔相同；
用感光膜作蚀刻隔板蚀刻第二绝缘层。
3、根据权利要求1或2所述方法，其中，所述蚀刻隔板由感光膜组成。
4、根据权利要求3所述方法，其中，所述第二绝缘层和第三绝缘层由绝缘膜组成，该膜由有选择性的高湿蚀刻法制成。
5、根据权利要求4所述方法，其中，第五步所述除去的第二绝缘层，所述第二绝缘层由湿蚀刻法除去，第二绝缘层和第三绝缘层均采用选择性蚀刻。
CN95109442A 1994-07-07 1995-07-07 形成半导体器件金属互连的方法 Expired - Fee Related CN1049763C (zh)

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KR94-16360 1994-07-07
KR9416360 1994-07-07

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Cited By (3)

* Cited by examiner, † Cited by third party
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DE19626039C2 (de) * 1996-04-12 2003-04-24 Lg Semicon Co Ltd Verfahren zum Herstellen einer Metalleitung
CN101300668B (zh) * 2005-10-31 2011-06-15 斯班逊有限公司 用于制造半导体组件的方法
CN101872114B (zh) * 2009-04-24 2012-03-28 中芯国际集成电路制造(上海)有限公司 用于制造金属互连线的掩模板版图

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US5700739A (en) * 1995-08-03 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd Method of multi-step reactive ion etch for patterning adjoining semiconductor metallization layers
US5616519A (en) * 1995-11-02 1997-04-01 Chartered Semiconductor Manufacturing Pte Ltd. Non-etch back SOG process for hot aluminum metallizations
US5652182A (en) * 1995-12-29 1997-07-29 Cypress Semiconductor Corporation Disposable posts for self-aligned non-enclosed contacts
US5888896A (en) * 1996-06-27 1999-03-30 Micron Technology, Inc. Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component
US5830804A (en) * 1996-06-28 1998-11-03 Cypress Semiconductor Corp. Encapsulated dielectric and method of fabrication
US5981374A (en) * 1997-04-29 1999-11-09 International Business Machines Corporation Sub-half-micron multi-level interconnection structure and process thereof
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US6133139A (en) 1997-10-08 2000-10-17 International Business Machines Corporation Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof
TW359008B (en) * 1997-12-20 1999-05-21 United Microelectronics Corp Double metal embedding
US6197696B1 (en) * 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
TW377502B (en) * 1998-05-26 1999-12-21 United Microelectronics Corp Method of dual damascene
US6319813B1 (en) 1998-07-06 2001-11-20 Micron Technology, Inc. Semiconductor processing methods of forming integrated circuitry and integrated circuitry constructions
KR100304979B1 (ko) * 1998-10-29 2001-10-19 김영환 반도체소자의배선형성방법
TW406369B (en) * 1998-12-18 2000-09-21 United Microelectronics Corp Method for manufacturing damascene
TW429534B (en) * 1999-10-18 2001-04-11 Taiwan Semiconductor Mfg Manufacturing method for borderless via of semiconductor device
US20050184392A1 (en) * 2004-02-23 2005-08-25 Kun-Hong Chen Method for fabricating interconnect and interconnect fabricated thereby

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US4410622A (en) * 1978-12-29 1983-10-18 International Business Machines Corporation Forming interconnections for multilevel interconnection metallurgy systems
US4954423A (en) * 1985-08-06 1990-09-04 Texas Instruments Incorporated Planar metal interconnection for a VLSI device
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JP2773578B2 (ja) * 1992-10-02 1998-07-09 日本電気株式会社 半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19626039C2 (de) * 1996-04-12 2003-04-24 Lg Semicon Co Ltd Verfahren zum Herstellen einer Metalleitung
CN101300668B (zh) * 2005-10-31 2011-06-15 斯班逊有限公司 用于制造半导体组件的方法
CN101872114B (zh) * 2009-04-24 2012-03-28 中芯国际集成电路制造(上海)有限公司 用于制造金属互连线的掩模板版图

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CN1049763C (zh) 2000-02-23
KR960005870A (ko) 1996-02-23
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