CN104952852B - 半导体器件的制造方法 - Google Patents
半导体器件的制造方法 Download PDFInfo
- Publication number
- CN104952852B CN104952852B CN201510217313.7A CN201510217313A CN104952852B CN 104952852 B CN104952852 B CN 104952852B CN 201510217313 A CN201510217313 A CN 201510217313A CN 104952852 B CN104952852 B CN 104952852B
- Authority
- CN
- China
- Prior art keywords
- lettering
- insulating film
- back wiring
- semiconductor substrate
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 52
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 37
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 238000003384 imaging method Methods 0.000 description 47
- 230000001681 protective effect Effects 0.000 description 16
- 239000011521 glass Substances 0.000 description 15
- 238000005538 encapsulation Methods 0.000 description 8
- 238000009434 installation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 239000010949 copper Substances 0.000 description 5
- 238000007648 laser printing Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000006059 cover glass Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02313—Subtractive methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
本发明提供一种在W‑CSP那样的封装尺寸与半导体芯片大致相同的半导体器件中,能确保更宽的印字区的半导体器件的结构的制造方法。该半导体器件的制造方法包含:对反面被磨削过的半导体基板进行蚀刻,形成到达在所述半导体基板的正面形成的正面电极的贯通孔的步骤;形成覆盖所述贯通孔的内壁和所述半导体基板的反面的第1绝缘膜的步骤;在所述半导体基板的反面上的所述绝缘膜上形成与所述正面电极连接的反面布线网的步骤;在所述反面布线网上形成具有开口部的第2绝缘膜的步骤;形成与从所述第2绝缘膜的开口部露出的所述反面布线连接的焊锡的步骤;以及在比所述焊锡的间隔宽并且未配置所述反面布线的印字区进行激光印字的步骤。
Description
本申请是申请人为拉碧斯半导体株式会社、发明名称为“半导体器件”、申请日为2009年1月20日、申请号为“200910005615.2”、优先权日2008年04月22日这一母案申请的分案申请。
技术领域
本发明涉及半导体器件,特别是涉及具有晶片级芯片尺寸封装(W-CSP)结构的半导体器件。
背景技术
近年的以带照相功能的移动电话或数字照相机为代表的信息设备的小型化、高密度、高功能化显著发展。作为实现在这些设备上搭载的CCD或CMOS等摄像元件的小型化的技术,公知有实现与芯片尺寸相同的封装的晶片级芯片尺寸封装(以下称作W-CSP)。
W-CSP是在晶片状态下完成全部的组装工序的新概念的封装。W-CSP与FBGA(FinePitch Ball Grid Array)同样,在封装的反面具有把端子排列为格子状的外形形状,封装尺寸与芯片尺寸大致相同。
在图1表示使用W-CSP技术制作的图像传感器30的截面结构。在由硅等构成的图像传感器芯片4的正面形成受光部3。受光部3由配置为矩阵状的光电二极管和电荷耦合元件(CCD)构成。在受光部3的正面层叠微透镜阵列3a。在图像传感器芯片4的正面形成与受光部3电连接的焊盘9。在焊盘9各个中电连接有贯通图像传感器芯片4并到达下面的贯通电极10。在贯通电极10和硅芯片之间设置使两者之间绝缘的绝缘膜11。在图像传感器芯片的反面形成反射防止膜23,在其开口部中形成与贯通电极10连接的反面布线13。焊锡凸起12在图像传感器芯片4的反面侧与反面布线13电连接。通过使用焊锡凸起12进行回流焊,将图像传感器30安装在安装基板上。在图像传感器芯片4上,隔着间隙形成玻璃罩6。图像传感器芯片上的空隙由包围受光部3的外周的方式形成的隔离块5形成。隔离块5和玻璃罩6的接合由粘接剂20进行。
通过这样用W-CSP构成图像传感器,不仅能实现装置的小型化、轻量化,不必通过在无尘室内使用倒装片焊接那样的高成本的个别安装方式,就能通过一般的回流焊,即可向安装基板进行安装。
专利文献1:日本特开2007-184680号公报
专利文献2:日本特开2006-73852号公报
一般,在半导体器件的制造工序中,在封装的正面或反面使用激光器描画来进行用于表示产品名称或制造时间、制造批次和特性等的文字、数字和记号等激光印字。由激光印字形成的印字标记,在把半导体器件在安装基板安装时作为用于防止异种元件的混入的识别标记、用装配机装配时的位置识别标记使用,此外,发生问题时用于制造流程的追踪等。可是,在以尽可能缩小封装尺寸为目的的W-CSP中,激光印字引起的弊端令人担心。
即在W-CSP中,从印字面到半导体芯片正面的距离极短,所以有时由于印字标记的形成,使反面布线露出,或者由于激光的热量使反面布线熔化,有可能引起绝缘不良。此外,在具有图像传感器那样的受光部的器件中,在受光区域无法形成印字标记。在W-CSP中,由于该封装的特点,能通过激光印字形成印字标记的区域非常有限,不容易设置印字区。
发明内容
本发明是鉴于所述问题而提出的,其目的在于,提供在W-CSP那样的封装尺寸与半导体芯片大致相同的半导体器件中,能确保更宽的印字区的半导体器件的结构的制造方法。
半导体器件的制造方法包含:对反面被磨削过的半导体基板进行蚀刻,形成到达在所述半导体基板的正面形成的正面电极的贯通孔的步骤;形成覆盖所述贯通孔的内壁和所述半导体基板的反面的第1绝缘膜的步骤;在所述半导体基板的反面上的所述绝缘膜上形成与所述正面电极连接的反面布线网的步骤;在所述反面布线网上形成具有开口部的第2绝缘膜的步骤;形成与从所述第2绝缘膜的开口部露出的所述反面布线连接的焊锡的步骤;以及在比所述焊锡的间隔宽并且未配置所述反面布线的印字区进行激光印字的步骤。
优选,在所述半导体器件的制造方法中,所述第1绝缘膜通过CVD法堆积。
优选,在所述半导体器件的制造方法中,所述第2绝缘膜是光硬化性环氧树脂,通过除去要成为所述开口部的部分进行曝光并且除去未曝光部分来形成。
优选,在所述半导体器件的制造方法中,所述反面布线由阻碍金属层、电镀种层以及电镀层构成。
优选,在所述半导体器件的制造方法中,在所述进行激光印字的步骤之后具备单片化为芯片状的步骤。
附图说明
图1是以往的具有W-CSP结构的图像传感器的剖面结构图。
图2是本发明实施例的图像传感器的剖面结构图。
图3是本发明实施例的图像传感器的剖面结构图。
图4是本发明实施例的图像传感器的反面侧的俯视图。
图5是比较印字区的配置和印字区的面积的图。
图6是表示本发明实施例的图像传感器的制造工序的剖面图。
图7是表示本发明实施例的图像传感器的制造工序的剖面图。
图8是本发明另一实施例的图像传感器的剖面图。
图9(a)是表示本发明另一实施例的图像传感器的印字区的俯视图,图9(b)是沿着图9(a)的9b-9b线的剖面图。
图中符号的说明:
1—图像传感器;100—半导体基板;102—玻璃基板;105a—贯通电极;105b—反面布线;108—焊锡凸起;110—正面电极;111—绝缘膜;150—保护膜;200—印字标记;300—印字区。
具体实施方式
下面,参照附图说明本发明的实施例。另外,在以下所示的图中,对实质上相同或等价的构成要素或部分标注相同的参照符号。
(实施例1)
图2是本发明实施例1的具有W-CSP结构的图像传感器1的剖面结构图。由单晶硅构成的半导体基板100构成图像传感器1的主体,在其正面形成CMOS电路或者CCD等受光元件140。在半导体基板100上形成像素数目个的多个受光元件,通过设置在外部的透镜等的光学系统,从摄像对象发出的光在受光元件140的受光面成像。受光元件140把与受光的光的强度对应的光电变换信号作为检测输出信号输出。然后,根据受光元件的位置和检测输出信号生成图像数据。
在半导体基板100的正面形成例如由铝等金属构成的正面电极110,通过正面电极110进行检测输出信号的收发或偏置电压的输入。在半导体基板100的正面形成在正面电极110的形成部分具有开口的由聚酰亚胺等构成的钝化膜112,用于保护半导体基板100的正面。
在半导体基板100形成从其反面侧到达正面电极110的贯通孔120。贯通孔120的内壁表面由铜等导电膜覆盖,据此,构成贯通电极105a。贯通电极105a在贯通孔120的底面,与正面电极110电连接。在半导体基板100的反面侧,与贯通电极105a电连接的反面布线105b被伸展。贯通电极105a的侧壁和半导体基板100的反面由绝缘膜111覆盖,据此,使贯通电极105a和反面布线105b及半导体基板100绝缘。半导体基板100的反面由阻焊剂等的绝缘膜106覆盖,确保反面侧的绝缘性。在反面布线105b的终端部,通过在绝缘膜106形成的开口部形成焊锡凸起108。焊锡凸起108经由反面布线105b和贯通电极105a与正面电极110电连接,因此,从半导体基板100的反面侧取出检测输出信号,或者供给偏置电压。焊锡凸起108构成与安装图像传感器1的安装基板的接合部。
在半导体基板100上形成具有光透过性的粘接层101。另外,取代形成光透过性的粘接层,也可以在该区域设置空隙。在粘接层101上形成具有光透过性的玻璃基板102。在玻璃基板102上,为了在图像传感器1的制造工序中对玻璃基板102的正面不带来损伤,粘贴保护膜150。另外,保护膜150是专门为了保护玻璃基板102,在把图像传感器1对安装基板安装之前剥离。
在图像传感器1的反面侧即形成焊锡凸起108的面形成由表示产品名称或制造时间和特性等的文字、数字和记号构成的印字标记200。在覆盖图像传感器1的反面的绝缘膜106上,通过激光印字方式形成印字标记200。通过从激光印字装置照射的激光的功率,在印字标记形成面刻沟,从而形成印字标记200。因此,如果在反面布线105b上进行激光印字,例如在由于制造偏差,绝缘膜106的膜厚变薄时,或者激光印字装置的激光输出被提高时,印字标记的沟到达反面布线105b,其结果使反面布线露出,无法确保绝缘性。因此,在反面布线上无法形成印字标记。
此外,在激光印字中,还有必要考虑基于激光的热量的影响,所以不仅从印字标记形成面到反面布线105b在深度方向的距离,还有必要确保与印字标记形成面平行的方向的距离。即印字标记200的外缘配置在从最近的反面布线105b或焊锡凸起108的形成位置在与印字标记形成面平行的方向至少分开距离L的位置。如图3所示,在反面布线成为多层布线时,在上层的布线105c上不形成印字标记。
图4表示从反面侧观察图像传感器1的俯视图。图像传感器1在制造工艺的最终工序中被分割,单片化为图4所示的芯片状。图像传感器1的反面由绝缘膜106覆盖,在其开口部形成配置为矩阵状的多个焊锡凸起108。另外,在图4中,表示设置在绝缘膜106的下层的贯通电极105a和反面布线105b。贯通电极105a沿着单片化的图像传感器1的周围部配置。在各贯通电极105a与反面布线105b连接,各反面布线105b分别延伸到焊锡凸起108的形成位置。各焊锡凸起108连接在绝缘膜106的终端部。连接从各焊锡凸起108到贯通电极105a之间的反面布线105b分别与其它反面布线彼此不接近地形成确保适当的间隔的布线图案。
在图像传感器1的反面设置多个凸起,在离正面极浅的位置存在反面布线网,所以为了一边确保必要的凸起数量,一边在图像传感器1的反面侧确保印字区,对凸起的排列方式和反面布线的布置进行研究。
在本实施例中,在图像传感器1的反面确保由图4的虚线包围的印字区300。在印字区300内形成表示表示产品名称、制造时间、制造批次等的文字、数字和记号等构成的印字标记200。假定在本实施例中形成的印字标记的大小与焊锡凸起108的间隔为相同程度或其以上。
印字区300如上所述,为了不配置在反面布线的形成区域的上方,避免激光引起的热对相邻的焊锡凸起或反面布线产生不良影响,印字区300的外缘配置在从最近的焊锡凸起或反面布线的形成位置在与印字形成面平行的方向至少分开距离L,所以图中斜线表示的区域从印字区排除。例如,考虑绝缘膜106的膜厚的偏差、激光印字装置的激光功率的偏差等,即使在它们变为最差的情形时,激光印字引起的热等的影响也不波及反面布线或焊锡凸起,由此决定距离L。
在不容易确保印字区的状况下,为了尽可能谋求印字区的扩大,本发明的半导体器件如图4所示,在图像传感器1的周围部配置印字区300。换言之,按照印字区的外缘与单片化的图像传感器芯片的外缘一致的方式配置印字区。通过在芯片周围部配置印字区300,与不伴随着扩大封装尺寸或者焊锡凸起或反面布线的削减将印字区在图像传感器1的中央部配置的情况相比,能够扩大印字区。
图5(a)表示在图像传感器1的反面侧中央部配置印字区300a的情形。即这时,印字区300a成为其周围由焊锡凸起108包围的状态。如上所述,需要将印字区300a的外缘从焊锡凸起108的形成位置在与印字形成面平行的方向至少分开距离L,所以图中斜线表示的区域从印字区排除。即在芯片中央部配置印字区时,构成印字区的外缘的四边全部需要从焊锡凸起108的形成位置后退距离L。作为结果,无法充分确保足够的印字空间,有时无法在印字区300a以预定的文字的尺寸形成预定字数的印字标记。
图5(b)表示在图像传感器1的周围部配置印字区300b的情形。在该图所示的例子中,印字区300b配置在图像传感器1的左侧端部。这时,在印字区300b的左方不存在焊锡凸起或反面布线,关于印字区300b的左侧端部,不需要如图5(a)所示的情形那样后退距离L。其结果,印字区300b的左端部能扩展到芯片左端部,印字区300b的面积能比图5(a)所示的情形的印字区300a的面积大。
在图5(d)表示通过重叠显示印字区300a和印字区300b,比较两者的面积的图。该图的斜线部分是扩大后的部分的面积。通过这样的芯片周围部配置印字区,不伴随着封装尺寸的扩大或焊锡凸起或反面布线的削减,就能扩大印字区。另外,扩大部分的区域除了能充当印字区,还能充当焊锡凸起或反面布线的形成区域。
图5(c)表示在芯片角部配置印字区300c的情形。在该图所示的例子中,印字区300c配置在图像传感器1的左下角部。这时,在印字区300c的左方和下方不存在焊锡凸起或反面布线,关于印字区300c的左端部和下端部,不需要如图5(a)所示的情形那样,后退距离L。其结果,印字区300c的左端部和下端部能分别扩展到芯片左侧端部和下端部,印字区300c的面积能比图5(a)所示的情形的印字区300a的面积大。此外,这时,比图5(b)所示的情形的印字区300b的面积更大。
在图5(d)通过重叠显示印字区300a和印字区300c,比较两者的面积。该图的斜线部分是扩大的部分的面积。通过在芯片周围部,特别是角部配置印字区300c,不伴随着封装尺寸的扩大或焊锡凸起或反面布线的削减,就能扩大印字区。扩大部分的区域除了能充当印字区,还能充当焊锡凸起或反面布线的形成区域。
下面,参照图6(a)~(e)和图7(f)~(i)所示的制造工序图,说明具有所述结构的图像传感器1的制造方法。
首先,准备CMOS电路或CCD等受光元件的形成工序、正面电极形成工序、其它作为形成图像传感器所必需的构成部分的由单晶硅等构成的半导体基板100(图6(a))。
此外,准备在正面粘贴保护膜150的玻璃基板102。保护膜150是为了避免玻璃基板102在制造工序中不损伤,为了保护而设置,覆盖玻璃基板102的上面的整面进行粘贴。接着,在半导体基板100的受光元件形成面涂敷透明粘接层101,粘贴半导体基板100和玻璃基板102(图6(b))。
接着,磨削半导体基板100的反面,从而使半导体基板100的厚度变为预定值(图6(c))。
接着,在半导体基板100的反面侧与正面电极(未图示)的形成位置对应的部分形成具有开口部的光掩模之后,蚀刻从光掩模的开口部分露出的半导体基板100,形成用于形成贯通电极的贯通孔104。贯通孔104蚀刻到在半导体基板100的正面形成的正面电极(未图示)(图6(d))。
接着,通过CVD法,按照覆盖贯通孔104的内壁和半导体基板100的反面的方式堆积由SiO2等构成的绝缘膜111。然后,蚀刻在贯通孔104的底面堆积的绝缘膜106,在贯通孔104的内部使正面电极(未图示)露出。接着,通过CVD法在贯通孔104的侧壁和底面、半导体基板100的反面依次堆积由TiN构成的阻碍金属层、铜(Cu)构成的电镀种层之后,在电镀种层中安装电极,通过电解电镀法,在贯通孔104的内壁形成由铜(Cu)构成的贯通电极105a,并且在半导体基板100的反面的绝缘膜111上形成反面布线105b。然后,对于反面布线105b通过蚀刻进行图案化,形成所希望的布线图案。贯通电极105a在贯通孔104的底面与正面电极(未图示)电连接(图6(e))。
接着,按照覆盖形成反面布线105b的半导体基板100的反面全体的方式,以约30μm左右的厚度涂敷由光硬化性环氧树脂构成的阻焊剂,干燥后,通过预定的光掩模使曝光部分光硬化。然后,有选择地除去阻焊剂的未曝光部分,形成在焊锡凸起形成位置具有开口部107的绝缘膜106(图7(f))。
接着,通过电解电镀法形成与从绝缘膜106的开口部107中露出的反面布线105b电连接的焊锡凸起108(图7(g))。
接着,在单片化为芯片状之前,在绝缘膜106上,使用激光印字装置,形成印字标记。印字标记如图4所示,形成在芯片周围部所确保的印字区300内。基于激光印字的印字深度由激光功率管理。印字区300考虑印字装置的激光功率的偏差、绝缘膜106的偏差,按照即使在它们变为最差的情形时,激光印字引起的热等的影响也不波及反面布线或焊锡凸起的方式,把印字区300的外缘配置在从反面布线105b或焊锡凸起108在平行于印字形成面的方向分开预定距离L的位置(图7(h))。
接着,剥离粘贴在玻璃基板102上的保护膜150,在晶片胶带300粘贴玻璃基板102一侧,进行分割,由此把图像传感器1单片化为芯片状(图7(i))。经过以上的各工序,制成本发明的图像传感器1。
(实施例2)
图8是具有本发明实施例2的W-CSP结构的图像传感器2的剖面结构图。图像传感器2与实施例1的图像传感器1不同点在于,印字标记200不是在半导体基板100的反面侧,而是在玻璃基板102上所粘贴的保护膜150上形成。即在图像传感器2的保护膜150的正下方不存在应该避免印字标记的形成的反面布线,此外,保护膜150在把图像传感器安装在安装基板上之前剥离,所以在使用时印字标记不会妨碍受光,能把该整面作为印字区。另外,通常,一般在分割之前剥离保护膜150,但是有时也可以保持粘贴保护膜,在晶片状态或单片化的芯片状态下出厂。在用户在剥离保护膜150之前,能把形成在保护膜150上的印字标记200作为向安装基板安装时的位置识别标记或方向识别标记使用。
根据保护膜150的特性或膜厚等,在保护膜150上进行激光印字,有可能对正下方的玻璃基板102带来损伤,有时由于它的干扰,无法从受光元件取得适当的检测输出信号。在这时,例如如图9(a)和(b)所示,优选回避由受光元件140受光的受光区400形成印字标记。图9(a)是从上面一侧观察图像传感器2的俯视图,图9(b)是图9(a)的9b-9b线剖面图。即受光区400例如配置在图像传感器2的中央部,包围受光区400的外周区域成为印字区300。这样配置印字区300回避了受光区400,从而向保护膜上印字时可以不损害作为图像传感器的功能。
受光区的周围部作为印字区300时,也可以在玻璃基板102直接形成印字标记。这时,不损害作为图像传感器的功能,而且安装后也会留下印字标记。
此外,如实施例1所示,在图像传感器的反面侧形成印字标记时,也可以如本实施例中所示那样,在保护膜或玻璃基板上形成印字标记。
此外,在所述各实施例中,以本发明应用在图像传感器中的情形为例进行说明,但是并不局限于此,作为半导体器件的功能也可以是其它的半导体器件。
Claims (5)
1.一种半导体器件的制造方法,其特征在于,包含:
对反面被磨削过的半导体基板进行蚀刻,形成到达在所述半导体基板的正面形成的正面电极的贯通孔的步骤;
形成覆盖所述贯通孔的内壁和所述半导体基板的反面的第1绝缘膜的步骤;
在所述半导体基板的反面上的所述绝缘膜上形成与所述正面电极连接的反面布线网的步骤;
在所述反面布线网上形成具有开口部的第2绝缘膜的步骤;
形成与从所述第2绝缘膜的开口部露出的所述反面布线连接的焊锡的步骤;以及
在所述第2绝缘膜的外表面上的比所述焊锡的间隔宽并且未配置所述反面布线的印字区进行激光印字的步骤。
2.根据权利要求1所述的半导体器件的制造方法,其特征在于:
所述第1绝缘膜通过CVD法堆积。
3.根据权利要求1所述的半导体器件的制造方法,其特征在于:
所述第2绝缘膜是光硬化性环氧树脂,通过除去要成为所述开口部的部分进行曝光并且除去未曝光部分来形成。
4.根据权利要求1所述的半导体器件的制造方法,其特征在于:
所述反面布线由阻碍金属层、电镀种层以及电镀层构成。
5.根据权利要求1所述的半导体器件的制造方法,其特征在于:
在所述进行激光印字的步骤之后具备单片化为芯片状的步骤。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008111087A JP5078725B2 (ja) | 2008-04-22 | 2008-04-22 | 半導体装置 |
JP2008-111087 | 2008-04-22 | ||
CN200910005615.2A CN101567350B (zh) | 2008-04-22 | 2009-01-20 | 半导体器件 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910005615.2A Division CN101567350B (zh) | 2008-04-22 | 2009-01-20 | 半导体器件 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104952852A CN104952852A (zh) | 2015-09-30 |
CN104952852B true CN104952852B (zh) | 2018-06-12 |
Family
ID=41283442
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510217313.7A Active CN104952852B (zh) | 2008-04-22 | 2009-01-20 | 半导体器件的制造方法 |
CN200910005615.2A Active CN101567350B (zh) | 2008-04-22 | 2009-01-20 | 半导体器件 |
CN201510217327.9A Pending CN104882437A (zh) | 2008-04-22 | 2009-01-20 | 半导体器件 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200910005615.2A Active CN101567350B (zh) | 2008-04-22 | 2009-01-20 | 半导体器件 |
CN201510217327.9A Pending CN104882437A (zh) | 2008-04-22 | 2009-01-20 | 半导体器件 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20090289319A1 (zh) |
JP (1) | JP5078725B2 (zh) |
KR (1) | KR101547091B1 (zh) |
CN (3) | CN104952852B (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102782862B (zh) * | 2010-02-26 | 2015-08-26 | 精材科技股份有限公司 | 芯片封装体及其制造方法 |
TWI495113B (zh) * | 2010-03-22 | 2015-08-01 | Xintec Inc | 具有改良防焊堰體結構之封裝用光學蓋板、影像感測件封裝體及其製作方法 |
JP5703730B2 (ja) * | 2010-12-13 | 2015-04-22 | 富士通株式会社 | 赤外線撮像装置 |
US8872293B2 (en) * | 2011-02-15 | 2014-10-28 | Sony Corporation | Solid-state imaging device and method of manufacturing the same and electronic apparatus |
TWI464857B (zh) * | 2011-05-20 | 2014-12-11 | Xintec Inc | 晶片封裝體、其形成方法、及封裝晶圓 |
US9170222B2 (en) | 2012-05-11 | 2015-10-27 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Detecting thermal interface material (‘TIM’) between a heat sink and an integrated circuit |
US9316603B2 (en) | 2012-05-11 | 2016-04-19 | Lenovo Enterprise Solutions (Singapore) Pte. Ltd. | Detecting thermal interface material (‘TIM’) between a heat sink and an integrated circuit |
US9666730B2 (en) | 2014-08-18 | 2017-05-30 | Optiz, Inc. | Wire bond sensor package |
JP2016171149A (ja) | 2015-03-11 | 2016-09-23 | 株式会社東芝 | 半導体装置およびその製造方法 |
KR102503892B1 (ko) | 2015-12-31 | 2023-02-28 | 삼성전자주식회사 | 패키지-온-패키지 타입의 반도체 패키지 및 그 제조방법 |
KR102564805B1 (ko) * | 2016-04-25 | 2023-08-10 | 에스케이하이닉스 주식회사 | 외부 및 내부 어드레스 마커들을 가진 이미지 센서 |
CN107634019A (zh) * | 2017-09-27 | 2018-01-26 | 江苏凯尔生物识别科技有限公司 | 一种薄膜冲压装置以及芯片喷码工艺 |
US10574025B2 (en) * | 2018-01-26 | 2020-02-25 | Lightwave Logic Inc. | Hermetic capsule and method for a monolithic photonic integrated circuit |
CN108693189A (zh) * | 2018-04-02 | 2018-10-23 | 中国工程物理研究院激光聚变研究中心 | 大口径熔石英光学元件基准标识的构建方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW558806B (en) * | 1999-11-29 | 2003-10-21 | Hitachi Ltd | Manufacturing method for semiconductor device |
TW200536448A (en) * | 2004-04-22 | 2005-11-01 | Phoenix Prec Technology Corp | Circuit board with identifiable information and method for fabricating the same |
TW200733336A (en) * | 2006-02-17 | 2007-09-01 | Advanced Semiconductor Eng | Ball grid array package structure with identification marks and substrate thereof |
TW200739851A (en) * | 2006-04-12 | 2007-10-16 | Advanced Semiconductor Eng | Chip package structure and process thereof |
CN101055857A (zh) * | 2006-04-14 | 2007-10-17 | 夏普株式会社 | 半导体器件及其制造方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61284932A (ja) * | 1985-06-11 | 1986-12-15 | Nec Yamagata Ltd | 半導体製造用樹脂封入金型 |
JPH07321146A (ja) * | 1994-05-25 | 1995-12-08 | Fuji Xerox Co Ltd | ワイヤーボンディング用認識マークの配置方法 |
US5734155A (en) * | 1995-06-07 | 1998-03-31 | Lsi Logic Corporation | Photo-sensitive semiconductor integrated circuit substrate and systems containing the same |
US5937270A (en) * | 1996-01-24 | 1999-08-10 | Micron Electronics, Inc. | Method of efficiently laser marking singulated semiconductor devices |
AU5090400A (en) * | 1999-05-27 | 2001-03-05 | Jetmask Limited | Method of forming a masking pattern on a surface |
JP2002217377A (ja) * | 2001-01-18 | 2002-08-02 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP4790157B2 (ja) * | 2001-06-07 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP3878868B2 (ja) * | 2002-03-01 | 2007-02-07 | シャープ株式会社 | GaN系レーザ素子 |
JP2004056061A (ja) * | 2002-05-27 | 2004-02-19 | Kyocera Corp | 撮像素子収納用パッケージ |
JP4257844B2 (ja) | 2003-11-04 | 2009-04-22 | パナソニック株式会社 | 半導体装置およびその製造方法 |
TWI247409B (en) * | 2004-05-13 | 2006-01-11 | Via Tech Inc | Flip chip package and process thereof |
JP2006012952A (ja) * | 2004-06-23 | 2006-01-12 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2006073852A (ja) | 2004-09-03 | 2006-03-16 | Dainippon Printing Co Ltd | センサーパッケージおよびその製造方法 |
JP4471213B2 (ja) * | 2004-12-28 | 2010-06-02 | Okiセミコンダクタ株式会社 | 半導体装置およびその製造方法 |
JP2006190879A (ja) * | 2005-01-07 | 2006-07-20 | Matsushita Electric Ind Co Ltd | 固体撮像装置 |
JP2007180200A (ja) * | 2005-12-27 | 2007-07-12 | Yamaha Corp | 識別マークの読取方法及び識別マークの読取装置 |
JP2007184680A (ja) * | 2006-01-04 | 2007-07-19 | Fujifilm Corp | 固体撮像装置及びその製造方法 |
JP2007208081A (ja) * | 2006-02-02 | 2007-08-16 | Oki Electric Ind Co Ltd | アラインメントマーク、合わせマーク及び半導体装置の製造方法 |
US7884472B2 (en) * | 2008-03-20 | 2011-02-08 | Powertech Technology Inc. | Semiconductor package having substrate ID code and its fabricating method |
-
2008
- 2008-04-22 JP JP2008111087A patent/JP5078725B2/ja active Active
-
2009
- 2009-01-20 CN CN201510217313.7A patent/CN104952852B/zh active Active
- 2009-01-20 CN CN200910005615.2A patent/CN101567350B/zh active Active
- 2009-01-20 CN CN201510217327.9A patent/CN104882437A/zh active Pending
- 2009-03-13 US US12/403,430 patent/US20090289319A1/en not_active Abandoned
-
2013
- 2013-12-26 US US14/140,842 patent/US20140103528A1/en not_active Abandoned
-
2015
- 2015-06-29 KR KR1020150092374A patent/KR101547091B1/ko active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW558806B (en) * | 1999-11-29 | 2003-10-21 | Hitachi Ltd | Manufacturing method for semiconductor device |
TW200536448A (en) * | 2004-04-22 | 2005-11-01 | Phoenix Prec Technology Corp | Circuit board with identifiable information and method for fabricating the same |
TW200733336A (en) * | 2006-02-17 | 2007-09-01 | Advanced Semiconductor Eng | Ball grid array package structure with identification marks and substrate thereof |
TW200739851A (en) * | 2006-04-12 | 2007-10-16 | Advanced Semiconductor Eng | Chip package structure and process thereof |
CN101055857A (zh) * | 2006-04-14 | 2007-10-17 | 夏普株式会社 | 半导体器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20140103528A1 (en) | 2014-04-17 |
CN104882437A (zh) | 2015-09-02 |
KR20150082164A (ko) | 2015-07-15 |
US20090289319A1 (en) | 2009-11-26 |
KR101547091B1 (ko) | 2015-08-24 |
JP2009266862A (ja) | 2009-11-12 |
CN101567350B (zh) | 2016-06-15 |
CN104952852A (zh) | 2015-09-30 |
CN101567350A (zh) | 2009-10-28 |
JP5078725B2 (ja) | 2012-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104952852B (zh) | 半导体器件的制造方法 | |
US9230947B2 (en) | Method of forming 3D integrated microelectronic assembly with stress reducing interconnects | |
US9373653B2 (en) | Stepped package for image sensor | |
US8895344B2 (en) | Method of making a low stress cavity package for back side illuminated image sensor | |
US8546900B2 (en) | 3D integration microelectronic assembly for integrated circuit devices | |
US7973397B2 (en) | Package substrate having embedded semiconductor chip and fabrication method thereof | |
JP4799543B2 (ja) | 半導体パッケージ及びカメラモジュール | |
JP4542768B2 (ja) | 固体撮像装置及びその製造方法 | |
KR101420934B1 (ko) | Cmos 이미지 센서를 위한 와이어 본드 인터포저 패키지 및 그 제조 방법 | |
US20080099907A1 (en) | Wafer-level fabrication of lidded chips with electrodeposited dielectric coating | |
CN102132411A (zh) | 图像传感器 | |
US20080284012A1 (en) | Semiconductor module manufacturing method, semiconductor module, and mobile device | |
JP2002198463A (ja) | チップサイズパッケージおよびその製造方法 | |
US8129829B2 (en) | Package substrate having embedded photosensitive semiconductor chip and fabrication method thereof | |
JP2010087229A (ja) | 半導体モジュール、半導体モジュールの製造方法および携帯機器 | |
US7335870B1 (en) | Method for image sensor protection | |
JP7389029B2 (ja) | 固体撮像装置、電子機器、および固体撮像装置の製造方法 | |
JP4806468B2 (ja) | 半導体モジュール | |
KR20090053461A (ko) | 마이크로 비아 홀 연결에 의한 실리콘 이미지 센서의웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 | |
CN101425470A (zh) | 形成影像传感器保护层的方法 | |
CN104051489A (zh) | 小轮廓图像传感器 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |