CN104766792A - 具有改善粘附性能和填充性能的钨层沉积方法 - Google Patents

具有改善粘附性能和填充性能的钨层沉积方法 Download PDF

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CN104766792A
CN104766792A CN201410003202.1A CN201410003202A CN104766792A CN 104766792 A CN104766792 A CN 104766792A CN 201410003202 A CN201410003202 A CN 201410003202A CN 104766792 A CN104766792 A CN 104766792A
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sih
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徐强
赵超
罗军
王桂磊
杨涛
李俊峰
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Institute of Microelectronics of CAS
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Priority to CN201410003202.1A priority Critical patent/CN104766792A/zh
Priority to EP14868723.9A priority patent/EP3093874B1/en
Priority to PCT/CN2014/072304 priority patent/WO2015100847A1/zh
Priority to US14/744,835 priority patent/US9589809B2/en
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Abstract

本发明公开了一种沉积钨(W)层的方法。该方法可以包括：对衬底进行预处理，以在衬底的表面上沉积SiH4源W膜；以及在经预处理的表面上沉积B2H6源W层。通过该方法，一方面可以实现优异的填充性能；另一方面，可以改善粘附性能。

Description

具有改善粘附性能和填充性能的钨层沉积方法
技术领域
本申请涉及半导体制造领域，更具体地，涉及一种沉积具有改善粘附性能和填充性能的钨(W)层的方法。
背景技术
随着金属氧化物半导体(CMOS)器件的特征尺寸不断缩小，栅极氧化物的厚度已经逐渐接近原子间距，受到隧穿效应的影响，栅极漏电流增大、可靠性降低等逐渐成为了不容忽视的问题。由此传统的SiO2栅介质材料已经不能满足CMOS器件进一步缩小的需要，在45nm技术节点以下，利用高介电常数(高K)栅介质取代SiO2已经成为了必然。另一方面，由于传统多晶硅栅极与高K材料不兼容，由此引发的阈值电压(Vt)升高、退火时严重的界面反应等问题，人们开始采用金属栅极来取代多晶硅栅极，从而从根本上消除了多晶硅栅极固有的栅耗尽和硼穿透等效应。
高K金属栅技术的实现有两种方法，一种为前栅工艺(gate first)，一种为后栅工艺(gate last)。前栅工艺同传统的SiO2/多晶硅栅工艺相差较小，其栅介质和金属电极形成于源、漏之前。后栅工艺则是先形成牺牲栅、牺牲栅介质层、源漏极、层间介质层之后，再去除牺牲栅重新形成栅极。
前栅工艺由于其栅层材料会受到源漏高温退火工艺的影响，限制了其对栅层材料的选择，目前已经逐渐被淘汰。另一方面，后栅工艺其栅极材料不需要承受很高的退火温度，对栅极材料的选择则更加广泛，同时能够更加体现材料的本征特征，因而目前很多大公司都采用后栅工艺来进行45nm以下CMOS器件的开发、生产。
通常可以选用铝(A1)或者钨(W)来作为后栅工艺中的栅电极材料。Intel最早报道了采用Al作为栅电极材料而制备的45nm芯片工艺。由于金属电极填充之后为平坦化工艺，而相对于传统的金属W平坦化工艺，铝平坦化工艺在生产控制上具有较大难度。因此金属W作为栅极材料则成为众多公司的选择。
对于金属W栅极材料来说，由于后栅工艺是将牺牲栅去除之后再进行栅极材料的填充，其对于栅极材料的填充性能要求非常高，并且到了22nm以下，可供栅极填充的空间更加小，传统的化学气相沉积(CVD)W沉积方法不能满足填充的需求，因而原子层沉积(ALD)W沉积方法则逐渐被采用。考虑到薄膜电阻以及填充性能等要求，一般选用由B2H6源制备的ALD W来作为金属栅极材料。
但是，由B2H6源制备的ALD W薄膜其粘附性能不佳，容易在后续的金属平坦化工艺过程中发生开裂，从其阻挡层TiN金属之上裂开，从而极大的影响了产品的良率。
发明内容
鉴于上述问题，本公开的目的至少部分地在于提供一种具有改善粘附性能和填充性能的钨(W)层的方法。
根据本公开的一个方面，提供了一种沉积钨(W)层的方法。该方法可以包括：对衬底进行预处理，以在衬底的表面上沉积SiH4源W膜；以及在经预处理的表面上沉积B2H6源W层。
可以在衬底的表面上形成数个原子层的SiH4源W膜。
SiH4源W膜的沉积与B2H6源W层的沉积可以通过单一的原子层沉积(ALD)工艺进行。ALD工艺例如可以包括：反应源气体浸没操作、反应源气体引入操作、主沉积操作。在这种情况下，形成SiH4源W膜可以包括：在反应源气体浸没操作中，向反应腔中引入SiH4；以及在反应源气体引入操作中，向反应腔中引入SiH4和WF6。在反应源气体引入操作中，可以向反应腔中交替引入SiH4和WF6数个(例如，2-10个)周期。沉积B2H6源W层可以包括：在主沉积操作中，向反应腔中交替引入B2H6和WF6若干周期。周期数可以取决于要沉积的W层的厚度。
衬底可以包括经后栅工艺处理后形成的栅槽，所述W膜和W层可以填充到该栅槽中以用作栅电极。
根据本公开的实施例，在沉积B2H6源W层之前，先利用SiH4进行预处理，以形成例如数个原子层的SiH4源W膜。于是，一方面可以保留B2H6源W层的优异填充性能；另一方面，通过结合SiH4源W膜，可以改善粘附性能。而且，B2H6源W层与SiH4源W膜的沉积可以在单一ALD工艺中进行。因此，可以增加了产品的良率，并且可以拓展工艺填充的窗口。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1是示出了根据本公开实施例的沉积W层的方法的流程图；
图2是示出了根据本公开实施例的原子层沉积(ALD)工艺的流程图；
图3A和3B是分别示出了根据本公开的示例方法制造的W层的横截面和顶视图的照片；以及
图4A和4B是分别示出了根据常规工艺制造的B2H6源W层的横截面和顶视图的照片。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
图1是示出了根据本公开实施例的沉积W层的方法的流程图。如图1所示，该方法100可以包括在操作102中对需要沉积钨(W)层的表面进行预处理，以在该表面上沉积SiH4源W膜。
这种表面例如可以包括衬底的表面，衬底上可以形成有器件。衬底可以包括各种合适的衬底，如体半导体衬底、绝缘体上半导体(SOI)衬底等。在以下，以体硅衬底为例进行描述，但是本公开不限于此。
根据一示例，衬底可以包括通过后栅工艺形成的器件(或其一部分)。这种器件例如可以如下制作。具体地，可以在衬底上形成包括牺牲栅介质层(例如，SiO2)和牺牲栅导体(例如，多晶硅)的牺牲栅堆叠。可以牺牲栅堆叠为掩模，进行晕圈(halo)注入和延伸区(extension)注入。然后，可以在牺牲栅堆叠的侧壁上形成如氮化物的栅侧墙(spacer)，并可以栅侧墙和牺牲栅堆叠为掩模，进行源/漏(S/D)注入。可以通过热处理，来激活注入的离子。然后，可以在衬底上沉积层间电介质层如氧化物，并可以对层间电介质层进行平坦化处理如化学机械抛光(CMP)。平坦化处理可以停止于栅侧墙，从而露出牺牲栅堆叠。可以选择性去除牺牲栅堆叠，从而在栅侧墙内侧留下栅槽。最后，可以向栅槽中填充真正的栅堆叠，例如包括高K栅介质如HfO2和金属栅导体如W。方法100可以应用于向栅槽中填充W层。
这里需要指出的是，后栅工艺不限于以上述方式进行，本领域技术人员知道多种方式来执行后栅工艺。另外，尽管在此以向栅槽中填充W层为例来进行描述，但是本公开的技术可以适用于需要沉积W层(特别是向有限空间如槽或孔中有效填充W层)的任何其他应用。
预处理可以包括向待处理表面(具体地，携带该表面的衬底)所在的反应腔中引入SiH4气体。如下进一步详细所述，该预处理可以结合到原子层沉积(ALD)工艺中，在这种情况下，反应腔可以是进行ALD之处。这种预处理可以导致在表面上形成数个(例如，少于10个)原子层的W膜。SiH4源W膜有助于改善随后沉积的W层主体的粘附性(例如，与下方的TiN阻挡层的粘附性)。
在预处理102之后，该方法100可以包括在操作104中在表面上(具体地，在SiH4源W膜上)进一步沉积B2H6源W层。B2H6源W层例如可以通过向反应腔中交替引入B2H6和WE6气体来沉积，这种沉积可以是ALD。由于B2H6源W层的生长速率相对较慢(例如，约为周期)，因此填充性能相对较好。
如上所述，本公开的技术可以结合到ALD工艺中。图2示出了ALD工艺的一般流程。该流程200包括在操作202中将需要处理的晶片放入反应腔中。可以在操作204中将惰性气体如Ar等引入反应腔中，以在反应腔内保持一定的真空度。为保证工艺顺利进行，可以在操作206中检查晶片是否牢靠地固定(例如，通过真空吸附)在反应基座上。在上述准备工作继续之后，可以开始正式沉积。首先，在反应源气体浸没(soak)操作208中，将反应源气体引入反应腔中。为去除吸附在晶片表面的多余反应源气体，可以在操作210中，利用惰性气体进行吹扫。然后，可以在反应源气体引入操作212中，向反应腔中引入反应源气体。接着，可以进行主沉积操作214。在主沉积操作214中，可以向反应腔中交替引入反应气体(例如，在沉积B2H6源W层的情况下，可以交替引入B2H6和WF6)。反应气体在反应腔内发生反应，从而产生预期成分的薄膜。在引入反应气体的过程中，可以利用惰性气体进行吹扫，以去除多余反应气体。在沉积了一定厚度的薄膜之后，可以在操作216，进一步利用惰性气体进行吹扫，以带走反应腔中多余的反应气体。最后，可以在操作218中从反应腔中去除沉积有薄膜的晶片。
根据常规技术，在利用反应气体B2H6和WF6来沉积B2H6源W层的情况下，在反应源气体浸没操作208中一般引入B2H6气体且在反应源气体引入操作212中一般引入B2H6和WF6气体。相反，根据本公开的实施例，可以在操作208中引入SiH4气体且在操作212中引入SiH4和WF6气体。这种反应源气体浸没操作和反应源气体引入操作可以导致表面预处理，并形成SiH4源W膜。
在反应源气体引入操作212中，可以交替引入SiH4和WF6气体。例如，当引入SiH4时，SiH4可以吸附在晶片表面上。之后，当引入WF6时，WF6可以与吸附在晶片表面上的SiH4反应，从而在晶片表面上W膜。在每次引入SiH4和WF6时，均可以利用惰性气体进行吹扫，以去除多余反应气体，使得只有单层或少数层的原子吸附到晶片表面上，从而能够以原子层为单位控制在晶片表面上发生反应。上述操作可以形成一个周期(cycle)。可以交替引入SiH4和WF6气体数个(例如，2-10个)周期，以形成数个原子层厚度的SiH4源W膜。
在主沉积操作214中，同样可以交替引入B2H6和WF6气体，且在每次引入之后，也可以利用惰性气体进行吹扫。这样进行若干周期(例如，250个周期)，以沉积所需厚度的B2H6源W层。主沉积操作中的周期数主要取决于要沉积的W层的厚度。
在此需要指出的是，在以上的描述中，没有说明ALD工艺中各步骤的具体工艺参数。本领域技术人员可以按照具体设计和沉积设备，按需设定这些工艺参数。另外，本领域技术人员可以设想多种ALD工艺流程，例如可以在图2所示的流程200中省略某些步骤，或者添加某些额外步骤。
图3A和3B分别示出了根据本公开的示例方法制造的W层的横截面和顶视图的照片。作为对比文件，图4A和4B中分别示出了根据常规工艺制造的B2H6源W层的横截面和顶视图的照片。比较图3A和4A可以看出，根据本公开实施例的W层保持了向栅槽中的良好填充；且比较图3B和4B可以看出，根据本公开实施例的W层粘附性能更好(开裂较少)。
根据本公开的实施例，所形成的W层具有较高的粘附性能和较高的填充性能，将其应用与22nm金属栅电极能够提高产品良率并且增加填充工艺窗口。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (10)

1.一种沉积钨(W)层的方法，包括：
对衬底进行预处理，以在衬底的表面上沉积SiH4源W膜；以及
在经预处理的表面上沉积B2H6源W层。
2.根据权利要求1所述的方法，其中，在衬底的表面上形成数个原子层的SiH4源W膜。
3.根据权利要求1所述的方法，其中，SiH4源W膜的沉积与B2H6源W层的沉积通过单一的原子层沉积(ALD)工艺进行。
4.根据权利要求3所述的方法，所述单一的ALD工艺包括：反应源气体浸没操作、反应源气体引入操作、主沉积操作。
5.根据权利要求4所述的方法，其中，形成SiH4源W膜包括：
在反应源气体浸没操作中，向反应腔中引入SiH4；以及
在反应源气体引入操作中，向反应腔中引入SiH4和WF6。
6.根据权利要求5所述的方法，其中，在反应源气体引入操作中，向反应腔中交替引入SiH4和WF6数个周期。
7.根据权利要求6所述的方法，其中，周期数为2-10。
8.根据权利要求4所述的方法，其中，沉积B2H6源W层包括：
在主沉积操作中，向反应腔中交替引入B2H6和WF6若干周期。
9.根据权利要求8所述的方法，其中周期数取决于要沉积的W层的厚度。
10.根据权利要求1所述的方法，其中，所述衬底包括经后栅工艺处理后形成的栅槽，所述W膜和W层填充到该栅槽中以用作栅电极。
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