WO2015100847A1 - 具有改善粘附性能和填充性能的钨层沉积方法 - Google Patents

具有改善粘附性能和填充性能的钨层沉积方法 Download PDF

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WO2015100847A1
WO2015100847A1 PCT/CN2014/072304 CN2014072304W WO2015100847A1 WO 2015100847 A1 WO2015100847 A1 WO 2015100847A1 CN 2014072304 W CN2014072304 W CN 2014072304W WO 2015100847 A1 WO2015100847 A1 WO 2015100847A1
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source
layer
gate
reaction
deposition
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PCT/CN2014/072304
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English (en)
French (fr)
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徐强
赵超
罗军
王桂磊
杨涛
李俊峰
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中国科学院微电子研究所
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Priority to EP14868723.9A priority Critical patent/EP3093874B1/en
Priority to US14/744,835 priority patent/US9589809B2/en
Publication of WO2015100847A1 publication Critical patent/WO2015100847A1/zh

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14—Deposition of only one other metal element
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • Tungsten layer deposition method with improved adhesion and filling properties.
  • the present application claims a method for depositing a tungsten layer having an improved adhesion and filling properties, which is filed on Jan. 3, 2014, with the application number 201410003202.1.
  • Priority of Chinese Patent Application the entire contents of which is incorporated herein by reference.
  • the present application relates to the field of semiconductor fabrication and, more particularly, to a method of depositing a tungsten (W) layer having improved adhesion properties and filling properties.
  • W tungsten
  • CMOS metal oxide semiconductor
  • the thickness of the gate oxide has gradually approached the atomic spacing, which is affected by the tunneling effect, and the increase in gate leakage current and reliability is becoming inevitable. Neglected problems. Therefore, the conventional SiO 2 gate dielectric material can no longer meet the needs of further shrinking of CMOS devices. Under the 45 nm technology node, it has become inevitable to replace SiO 2 with a high dielectric constant (high K) gate dielectric.
  • high K dielectric constant
  • Vt wide-value voltage
  • the serious interface reaction during annealing have begun to replace the polysilicon gate with a metal gate.
  • the front gate process has a small difference from the conventional Si0 2 / polysilicon gate process, and the gate dielectric and metal electrodes are formed before the source and drain.
  • the back gate process is to form a sacrificial gate, a sacrificial gate dielectric layer, a source drain, and an interlayer dielectric layer, and then remove the sacrificial gate to re-form the gate.
  • the front gate process has been gradually eliminated because its gate layer material is affected by the source-drain high-temperature annealing process, which limits its choice of gate layer materials.
  • the gate material of the back gate process does not need to withstand the high annealing temperature, the selection of the gate material is more extensive, and the intrinsic characteristics of the material can be more reflected. Therefore, many large companies currently use the back gate.
  • the process is to develop and produce CMOS devices below 45nm.
  • Aluminum (A1) or tungsten (W) can usually be used as the gate electrode material in the back gate process.
  • Intel The 45nm chip process prepared by using A1 as the gate electrode material was first reported. Since the metal electrode is filled after the planarization process, the aluminum planarization process is more difficult in production control than the conventional metal W planarization process. Therefore, metal W as a gate material has become the choice of many companies.
  • the gate-gate process is to remove the gate material after the gate-gate process is removed, the filling property of the gate material is very high, and below 22 nm, the gate can be filled.
  • the space is even smaller, and the traditional chemical vapor deposition (CVD) W deposition method can not meet the filling requirements, so the atomic layer deposition (ALD) W deposition method is gradually being used.
  • ALD W prepared from B 2 H 6 source is generally used as the ALD W film prepared from the B 2 H 6 source, which has poor adhesion and is easy to be flat in the subsequent metal. Cracking occurs during the chemical process, cracking from the barrier TiN metal, which greatly affects the yield of the product.
  • a method of depositing a tungsten (W) layer is provided.
  • the method may comprise: pretreatment of a substrate to the deposition source Si3 ⁇ 4 W film on a surface of the substrate; and depositing the source B 2 H 6 W layer on the surface pretreated.
  • a plurality of atomic Si 2 ⁇ 4 source W films may be formed on the surface of the substrate.
  • Depositing the W film and the source B Si3 ⁇ 4 W layer deposition source 2 H 6 may be performed by a single process of atomic layer deposition (ALD).
  • the ALD process may include, for example, a reaction source gas immersion operation, a reaction source gas introduction operation, and a main deposition operation.
  • the W film may be formed Si3 ⁇ 4 source comprising: a source gas in immersion operation, Si3 ⁇ 4 introduced into the reaction chamber; and a pull-in operation in the reaction gas source, introducing WF 6 and Si3 ⁇ 4 into the reaction chamber.
  • the reaction source gas introduction operation several (for example, 2 to 10) cycles of SiH 4 and WF 6 may be alternately introduced into the reaction chamber.
  • Depositing the B 2 3 ⁇ 4 source W layer can include: introducing a plurality of cycles of B 2 H 6 and WF 6 alternately into the reaction chamber during the main deposition operation. The number of cycles may depend on the thickness of the W layer to be deposited.
  • the substrate may include a gate trench formed by a post gate process, and the W film and the W layer may be filled into the gate trench to serve as a gate electrode.
  • pretreatment is performed using Si 3 ⁇ 4 to form a Si 3 ⁇ 4 source W film such as a plurality of atomic layers.
  • Si 3 ⁇ 4 source W film such as a plurality of atomic layers.
  • the excellent filling property of the W 2 H 6 source W layer can be retained; on the other hand, the adhesion property can be improved by combining the Si 3 ⁇ 4 source W film.
  • the deposition of the B 2 H 6 source W layer and the SiH 4 source W film can be performed in a single ALD process. Therefore, the yield of the product can be increased, and the window of the process filling can be expanded.
  • FIG. 1 is a flow chart showing a method of depositing a W layer in accordance with an embodiment of the present disclosure
  • FIGS. 3A and 3B are photographs showing cross-section and top view, respectively, of a W layer fabricated according to an exemplary method of the present disclosure. ; as well as
  • FIGS. 4A and 4B are photographs showing cross-sectional and top views, respectively, of a B 2 H 6 source W layer fabricated according to a conventional process. detailed description
  • FIG. 1 is a flow chart illustrating a method of depositing a W layer in accordance with an embodiment of the present disclosure.
  • the method 100 may include operation 102 of the needed surface of the tungsten (W) layer is deposited pretreated, to the upper surface of the W film is deposited SiH 4 source.
  • Such a surface may, for example, comprise a surface of a substrate on which a device may be formed.
  • the substrate may include various suitable substrates such as bulk semiconductor substrates, semiconductor-on-insulator (SOI) substrates, and the like.
  • SOI semiconductor-on-insulator
  • a bulk silicon substrate will be described as an example, but the present disclosure is not limited thereto.
  • the substrate may include a device (or a portion thereof) formed by a back gate process.
  • a sacrificial gate stack including a sacrificial gate dielectric layer (eg, SiO 2 ) and a sacrificial gate conductor (eg, polysilicon) may be formed on the substrate. Halo implants and extension implants can be performed at the expense of the gate stack as a mask.
  • a gate spacer such as a nitride may be formed on the sidewall of the sacrificial gate stack, and a source/drain (S/D) implant may be performed using the gate spacer and the sacrificial gate stack as a mask.
  • S/D source/drain
  • the implanted ions can be activated by heat treatment.
  • an interlayer dielectric layer such as an oxide may be deposited on the substrate, and the interlayer dielectric layer may be subjected to a planarization treatment such as chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the planarization process can stop at the gate spacers to expose the sacrificial gate stack.
  • the sacrificial gate stack can be selectively removed to leave a gate trench inside the gate spacer.
  • a true gate stack can be filled into the gate trenches, including, for example, high-k gate dielectrics such as Hf0 2 and metal gate conductors such as W.
  • the method 100 can be applied to fill a gate trench with a W layer.
  • the back gate process is not limited to being performed in the above manner, and those skilled in the art are aware of various ways to perform the gate-last process.
  • the technique of the present disclosure can be applied to any other that requires deposition of a W layer (particularly, effectively filling a W layer into a limited space such as a groove or a hole). application.
  • the pretreatment may include introducing SiH 4 gas into the reaction chamber in which the surface to be treated, in particular, the substrate carrying the surface, is located.
  • the pretreatment can be incorporated into an atomic layer deposition (ALD) process, in which case the reaction chamber can be where ALD is performed.
  • ALD atomic layer deposition
  • This pretreatment can result in the formation of a plurality of (e.g., less than 10) atomic layers of W film on the surface.
  • the SiH 4 source W film helps to improve the adhesion of the subsequently deposited W layer body (e.g., adhesion to the underlying TiN barrier layer).
  • the method 100 may include operation 104 (specifically, the source Si3 ⁇ 4 W film) is deposited a further source of B 2 H 6 W layer on the surface.
  • the B 2 H 6 source W layer can be deposited, for example, by alternately introducing B 2 H 6 and WF 6 gases into the reaction chamber, which deposition can be ALD. Since the growth rate of the W 2 H 6 source W layer is relatively slow (for example, about 3.1 A/cycle), the filling performance is relatively good.
  • FIG. 2 shows the general flow of an ALD process.
  • the process 200 includes placing a wafer to be processed into a reaction chamber in operation 202.
  • An inert gas such as Ar or the like may be introduced into the reaction chamber in operation 204 to maintain a certain degree of vacuum within the reaction chamber.
  • it can be checked in operation 206 whether the wafer is securely fixed. (for example, by vacuum adsorption) on the reaction susceptor.
  • formal deposition can begin.
  • a reaction source gas soak operation 208 a reaction source gas is introduced into the reaction chamber.
  • a purge may be performed using an inert gas in operation 210.
  • the reaction source gas can be introduced into the reaction chamber in the reaction source gas introduction operation 212.
  • a main deposition operation 214 can be performed.
  • a reactive gas may be introduced alternately into the reaction chamber (for example, in the case of depositing a B 2 H 6 source W layer, B 2 H 6 and WF 6 may be alternately introduced).
  • the reaction gas reacts in the reaction chamber to produce a film of the desired composition.
  • an inert gas may be used for purging to remove excess reaction gas. After depositing a film of a certain thickness, it may be further purged with an inert gas at operation 216 to remove excess reactive gas from the reaction chamber.
  • the wafer-deposited wafer can be removed from the reaction chamber in operation 218.
  • B 2 H 6 gas is generally introduced in the reaction source gas immersion operation 208 and the reaction source gas introduction operation is performed.
  • B 2 H 6 and WF 6 gases are generally introduced in 212.
  • it may be introduced in operation 208 in operation 212 and Si3 ⁇ 4 gas Si3 ⁇ 4 and introducing WF 6 gas.
  • This reaction source gas immersion operation and reaction source gas introduction operation can cause surface pretreatment and formation of a Si3 ⁇ 4 source W film.
  • the reaction gas is introduced into the source 212 can be alternately introduced Si3 ⁇ 4 and WF 6 gas.
  • Si3 ⁇ 4 can be adsorbed on the surface of the wafer.
  • WF 6 can react with Si3 ⁇ 4 adsorbed on the surface of the wafer to form a W film on the surface of the wafer.
  • Si3 ⁇ 4 and WF 6 can be purged with an inert gas to remove excess reactive gas, so that only a single layer or a few layers of atoms are adsorbed onto the surface of the wafer, so that the wafer can be controlled in atomic layer units.
  • a reaction occurs on the surface.
  • the above operation can form a cycle.
  • Si3 ⁇ 4 alternately introducing WF 6 gas and a plurality (e.g., 2-10) cycles to form a plurality of atomic layer thickness W film SiH 4 source.
  • the B 2 H 6 and WF 6 gases can also be introduced alternately, and after each introduction, the purge can also be carried out using an inert gas. Carried out by a number of cycles (e.g., 250 cycles), B to deposit the desired thickness of W layer 2 H 6 source. The number of cycles in the main deposition operation depends primarily on the thickness of the W layer to be deposited.
  • FIGS. 4A and 4B show photographs of cross-section and top view, respectively, of a W layer fabricated in accordance with an example method of the present disclosure.
  • photographs of a cross section and a top view of a B 2 H 6 source W layer manufactured according to a conventional process are respectively shown in FIGS. 4A and 4B.
  • 3A and 4A it can be seen that the W layer according to an embodiment of the present disclosure maintains a good filling into the gate trench; and as can be seen by comparing FIGS. 3B and 4B, the W layer adhesion performance according to an embodiment of the present disclosure is better. (less cracking).
  • the formed W layer has higher adhesion properties and higher filling properties, and its application to a 22 nm metal gate electrode can improve product yield and increase a filling process window.

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Abstract

一种沉积钨（W）层的方法，包括：对衬底进行预处理，以在衬底的表面上沉积SiH4源W膜；以及在经预处理的表面上沉积B2H6源W层。通过该方法，一方面可以实现优异的填充性能，另一方面，可以改善粘附性能。

Description

具有改善粘附性能和填充性能的钨层沉积方法 本申请要求了 2014年 1月 3 日提交的、 申请号为 201410003202.1、 发明 名称为 "具有改善粘附性能和填充性能的钨层沉积方法"的中国专利申请的优 先权， 其全部内容通过引用结合在本申请中。 技术领域
本申请涉及半导体制造领域， 更具体地， 涉及一种沉积具有改善粘附性能 和填充性能的钨（W )层的方法。 背景技术
随着金属氧化物半导体（CMOS )器件的特征尺寸不断缩小， 栅极氧化物 的厚度已经逐渐接近原子间距， 受到隧穿效应的影响， 栅极漏电流增大、 可靠 性降低等逐渐成为了不容忽视的问题。 由此传统的 Si02栅介质材料已经不能 满足 CMOS器件进一步缩小的需要， 在 45nm技术节点以下， 利用高介电常 数（高 K )栅介质取代 Si02已经成为了必然。 另一方面， 由于传统多晶硅栅 极与高 K材料不兼容， 由此引发的阔值电压 （Vt )升高、 退火时严重的界面 反应等问题，人们开始釆用金属栅极来取代多晶硅栅极，从而从根本上消除了 多晶硅栅极固有的栅耗尽和硼穿透等效应。
高 K金属栅技术的实现有两种方法， 一种为前栅工艺 （gate first ), —种 为后栅工艺 （gate last )。 前栅工艺同传统的 Si02/多晶硅栅工艺相差较小， 其 栅介质和金属电极形成于源、 漏之前。 后栅工艺则是先形成牺牲栅、 牺牲栅介 质层、 源漏极、 层间介质层之后， 再去除牺牲栅重新形成栅极。
前栅工艺由于其栅层材料会受到源漏高温退火工艺的影响，限制了其对栅 层材料的选择， 目前已经逐渐被淘汰。 另一方面， 后栅工艺其栅极材料不需要 承受很高的退火温度，对栅极材料的选择则更加广泛， 同时能够更加体现材料 的本征特征， 因而目前很多大公司都釆用后栅工艺来进行 45nm 以下 CMOS 器件的开发、 生产。
通常可以选用铝（ A1 )或者钨（ W )来作为后栅工艺中的栅电极材料。 Intel 最早报道了釆用 A1作为栅电极材料而制备的 45nm芯片工艺。 由于金属电极 填充之后为平坦化工艺， 而相对于传统的金属 W平坦化工艺， 铝平坦化工艺 在生产控制上具有较大难度。 因此金属 W作为栅极材料则成为众多公司的选 择。
对于金属 W栅极材料来说， 由于后栅工艺是将牺牲栅去除之后再进行栅 极材料的填充，其对于栅极材料的填充性能要求非常高，并且到了 22nm以下， 可供栅极填充的空间更加小， 传统的化学气相沉积 （CVD ) W沉积方法不能 满足填充的需求， 因而原子层沉积 （ALD ) W沉积方法则逐渐被釆用。 考虑 到薄膜电阻以及填充性能等要求， 一般选用由 B2H6源制备的 ALD W来作为 但是， 由 B2H6源制备的 ALD W薄膜其粘附性能不佳， 容易在后续的金 属平坦化工艺过程中发生开裂，从其阻挡层 TiN金属之上裂开，从而极大的影 响了产品的良率。
发明内容
鉴于上述问题，本公开的目的至少部分地在于提供一种具有改善粘附性能 和填充性能的钨（W )层的方法。
根据本公开的一个方面， 提供了一种沉积钨（W )层的方法。 该方法可以 包括： 对衬底进行预处理， 以在衬底的表面上沉积 Si¾源 W膜； 以及在经预 处理的表面上沉积 B2H6源 W层。
可以在衬底的表面上形成数个原子层的 Si¾源 W膜。
Si¾源 W膜的沉积与 B2H6源 W层的沉积可以通过单一的原子层沉积 ( ALD )工艺进行。 ALD 工艺例如可以包括： 反应源气体浸没操作、 反应源 气体引入操作、 主沉积操作。 在这种情况下， 形成 Si¾源 W膜可以包括： 在 反应源气体浸没操作中， 向反应腔中引入 Si¾; 以及在反应源气体引入操作 中， 向反应腔中引入 Si¾和 WF6。 在反应源气体引入操作中， 可以向反应腔 中交替引入 SiH4和 WF6数个（例如， 2-10个）周期。 沉积 B2¾源 W层可以 包括： 在主沉积操作中， 向反应腔中交替引入 B2H6和 WF6若干周期。 周期数 可以取决于要沉积的 W层的厚度。 衬底可以包括经后栅工艺处理后形成的栅槽，所述 W膜和 W层可以填充 到该栅槽中以用作栅电极。
根据本公开的实施例， 在沉积 B2H6源 W层之前， 先利用 Si¾进行预处 理， 以形成例如数个原子层的 Si¾源 W膜。 于是， 一方面可以保留 B2H6源 W层的优异填充性能； 另一方面，通过结合 Si¾源 W膜，可以改善粘附性能。 而且， B2H6源 W层与 SiH4源 W膜的沉积可以在单一 ALD工艺中进行。因此， 可以增加了产品的良率， 并且可以拓展工艺填充的窗口。 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和优点将更为清楚， 在附图中：
图 1是示出了根据本公开实施例的沉积 W层的方法的流程图；
图 2是示出了根据本公开实施例的原子层沉积（ALD ) 工艺的流程图； 图 3A和 3B是分别示出了根据本公开的示例方法制造的 W层的横截面和 顶视图的照片； 以及
图 4A和 4B是分别示出了根据常规工艺制造的 B2H6源 W层的横截面和 顶视图的照片。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是 示例性的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知 结构和技术的描述， 以避免不必要地混淆本公开的概念。
图 1是示出了根据本公开实施例的沉积 W层的方法的流程图。 如图 1所 示， 该方法 100可以包括在操作 102中对需要沉积钨（ W )层的表面进行预处 理， 以在该表面上沉积 SiH4源 W膜。
这种表面例如可以包括衬底的表面，衬底上可以形成有器件。衬底可以包 括各种合适的衬底， 如体半导体衬底、 绝缘体上半导体（SOI )衬底等。 在以 下， 以体硅衬底为例进行描述， 但是本公开不限于此。
根据一示例， 衬底可以包括通过后栅工艺形成的器件 （或其一部分）。 这 种器件例如可以如下制作。 具体地， 可以在衬底上形成包括牺牲栅介质层（例 如， Si02 )和牺牲栅导体（例如， 多晶硅）的牺牲栅堆叠。 可以牺牲栅堆叠为 掩模， 进行晕圈 （halo ) 注入和延伸区 （extension ) 注入。 然后， 可以在牺牲 栅堆叠的侧壁上形成如氮化物的栅侧墙（ spacer ),并可以栅侧墙和牺牲栅堆叠 为掩模， 进行源 /漏（ S/D )注入。 可以通过热处理， 来激活注入的离子。 然后， 可以在衬底上沉积层间电介质层如氧化物，并可以对层间电介质层进行平坦化 处理如化学机械抛光（ CMP )。 平坦化处理可以停止于栅侧墙， 从而露出牺牲 栅堆叠。 可以选择性去除牺牲栅堆叠， 从而在栅侧墙内侧留下栅槽。 最后， 可 以向栅槽中填充真正的栅堆叠， 例如包括高 K栅介质如 Hf02和金属栅导体如 W。 方法 100可以应用于向栅槽中填充 W层。
这里需要指出的是，后栅工艺不限于以上述方式进行， 本领域技术人员知 道多种方式来执行后栅工艺。 另外， 尽管在此以向栅槽中填充 W层为例来进 行描述， 但是本公开的技术可以适用于需要沉积 W层（特别是向有限空间如 槽或孔中有效填充 W层） 的任何其他应用。
预处理可以包括向待处理表面（具体地， 携带该表面的衬底）所在的反应 腔中引入 SiH4气体。 如下进一步详细所述， 该预处理可以结合到原子层沉积 ( ALD )工艺中， 在这种情况下， 反应腔可以是进行 ALD之处。 这种预处理 可以导致在表面上形成数个（例如， 少于 10个）原子层的 W膜。 SiH4源 W 膜有助于改善随后沉积的 W层主体的粘附性（例如， 与下方的 TiN阻挡层的 粘附性）。
在预处理 102之后，该方法 100可以包括在操作 104中在表面上（具体地， 在 Si¾源 W膜上）进一步沉积 B2H6源 W层。 B2H6源 W层例如可以通过向 反应腔中交替引入 B2H6和 WF6气体来沉积，这种沉积可以是 ALD。由于 B2H6 源 W层的生长速率相对较慢（例如， 约为 3.1A/周期）， 因此填充性能相对较 好。
如上所述，本公开的技术可以结合到 ALD工艺中。 图 2示出了 ALD工艺 的一般流程。 该流程 200包括在操作 202中将需要处理的晶片放入反应腔中。 可以在操作 204中将惰性气体如 Ar等引入反应腔中， 以在反应腔内保持一定 的真空度。 为保证工艺顺利进行， 可以在操作 206中检查晶片是否牢靠地固定 (例如， 通过真空吸附）在反应基座上。 在上述准备工作继续之后， 可以开始 正式沉积。 首先， 在反应源气体浸没（soak )操作 208中， 将反应源气体引入 反应腔中。 为去除吸附在晶片表面的多余反应源气体， 可以在操作 210中， 利 用惰性气体进行吹扫。 然后， 可以在反应源气体引入操作 212中， 向反应腔中 引入反应源气体。 接着， 可以进行主沉积操作 214。 在主沉积操作 214中， 可 以向反应腔中交替引入反应气体（例如， 在沉积 B2H6源 W层的情况下， 可以 交替引入 B2H6和 WF6 )。反应气体在反应腔内发生反应，从而产生预期成分的 薄膜。 在引入反应气体的过程中， 可以利用惰性气体进行吹扫， 以去除多余反 应气体。 在沉积了一定厚度的薄膜之后， 可以在操作 216, 进一步利用惰性气 体进行吹扫， 以带走反应腔中多余的反应气体。 最后， 可以在操作 218中从反 应腔中去除沉积有薄膜的晶片。
根据常规技术， 在利用反应气体 B2H6和 WF6来沉积 B2H6源 W层的情况 下， 在反应源气体浸没操作 208中一般引入 B2H6气体且在反应源气体引入操 作 212中一般引入 B2H6和 WF6气体。 相反， 根据本公开的实施例， 可以在操 作 208中引入 Si¾气体且在操作 212中引入 Si¾和 WF6气体。这种反应源气 体浸没操作和反应源气体引入操作可以导致表面预处理，并形成 Si¾源 W膜。
在反应源气体引入操作 212中， 可以交替引入 Si¾和 WF6气体。 例如， 当引入 SiH4时， Si¾可以吸附在晶片表面上。 之后， 当引入 WF6时， WF6可 以与吸附在晶片表面上的 Si¾反应，从而在晶片表面上 W膜。在每次引入 Si¾ 和 WF6时， 均可以利用惰性气体进行吹扫， 以去除多余反应气体， 使得只有 单层或少数层的原子吸附到晶片表面上，从而能够以原子层为单位控制在晶片 表面上发生反应。 上述操作可以形成一个周期 （ cycle )。 可以交替引入 Si¾ 和 WF6气体数个（例如， 2-10个）周期， 以形成数个原子层厚度的 SiH4源 W 膜。
在主沉积操作 214中， 同样可以交替引入 B2H6和 WF6气体， 且在每次引 入之后， 也可以利用惰性气体进行吹扫。 这样进行若干周期（例如， 250个周 期 ) , 以沉积所需厚度的 B2H6源 W层。 主沉积操作中的周期数主要取决于要 沉积的 W层的厚度。
在此需要指出的是， 在以上的描述中， 没有说明 ALD工艺中各步骤的具 体工艺参数。本领域技术人员可以按照具体设计和沉积设备，按需设定这些工 艺参数。 另外， 本领域技术人员可以设想多种 ALD工艺流程， 例如可以在图 2所示的流程 200中省略某些步骤， 或者添加某些额外步骤。
图 3A和 3B分别示出了根据本公开的示例方法制造的 W层的横截面和顶 视图的照片。 作为对比文件， 图 4A和 4B中分别示出了根据常规工艺制造的 B2H6源 W层的横截面和顶视图的照片。 比较图 3A和 4A可以看出，根据本公 开实施例的 W层保持了向栅槽中的良好填充； 且比较图 3B和 4B可以看出， 根据本公开实施例的 W层粘附性能更好（开裂较少 )。
根据本公开的实施例， 所形成的 W层具有较高的粘附性能和较高的填充 性能，将其应用与 22nm金属栅电极能够提高产品良率并且增加填充工艺窗口。
以上对本公开的实施例进行了描述。但是， 这些实施例仅仅是为了说明的 目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价 物限定。 不脱离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这 些替代和修改都应落在本公开的范围之内。

Claims

权 利 要 求 书
1. 一种沉积钨（W )层的方法， 包括：
对衬底进行预处理， 以在衬底的表面上沉积 Si¾源 W膜； 以及
在经预处理的表面上沉积 B2H6源 W层。
2. 根据权利要求 1所述的方法， 其中， 在衬底的表面上形成数个原子层 的 Si¾源 W膜。
3. 根据权利要求 1所述的方法， 其中， Si¾源 W膜的沉积与 B2H6源 W 层的沉积通过单一的原子层沉积（ALD )工艺进行。
4. 根据权利要求 3所述的方法， 所述单一的 ALD工艺包括： 反应源气体 浸没操作、 反应源气体引入操作、 主沉积操作。
5. 根据权利要求 4所述的方法， 其中， 形成 Si¾源 W膜包括：
在反应源气体浸没操作中， 向反应腔中引入 Si¾; 以及
在反应源气体引入操作中， 向反应腔中引入 Si¾和 WF6。
6. 根据权利要求 5所述的方法， 其中， 在反应源气体引入操作中， 向反 应腔中交替引入 SiH4和 WF6数个周期。
7. 根据权利要求 6所述的方法， 其中， 周期数为 2-10。
8. 根据权利要求 4所述的方法， 其中， 沉积 B2H6源 W层包括： 在主沉积操作中， 向反应腔中交替引入 B2H6和 WF6若干周期。
9. 根据权利要求 8所述的方法，其中周期数取决于要沉积的 W层的厚度。
10. 根据权利要求 1所述的方法， 其中， 所述衬底包括经后栅工艺处理后 形成的栅槽， 所述 W膜和 W层填充到该栅槽中以用作栅电极。
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