CN104752232A - 一种改善热载流子注入损伤的离子注入方法 - Google Patents

一种改善热载流子注入损伤的离子注入方法 Download PDF

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CN104752232A
CN104752232A CN201510144259.8A CN201510144259A CN104752232A CN 104752232 A CN104752232 A CN 104752232A CN 201510144259 A CN201510144259 A CN 201510144259A CN 104752232 A CN104752232 A CN 104752232A
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side wall
hot carrier
ion
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injection method
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桑宁波
李润领
关天鹏
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Shanghai Huali Microelectronics Corp
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Abstract

本发明提供一种改善热载流子注入损伤的离子注入方法,通过在侧墙刻蚀前对漏极区域增加一步紫外线处理工艺,使得漏极区域上方的侧墙层与源极区域上方的侧墙层具有不同的刻蚀速率,进而使源极侧墙的截面宽度小于漏极侧墙的截面宽度,导致漏端的掺杂离子离沟道距离被拉远,而源端的掺杂离子与沟道和衬底的距离被拉近,降低了漏端的纵向电场强度,减小了器件热载流子注入的损伤。

Description

一种改善热载流子注入损伤的离子注入方法
技术领域
本发明涉及一种半导体制造领域,尤其涉及一种改善热载流子注入损伤的离子注入方法。
背景技术
热载流子效应是MOS(金属氧化物半导体)器件的一个重要的失效机理,随着MOS器件尺寸的日益缩小,器件的热载流子注入效应越来越严重。以PMOS(P型金属氧化物半导体)器件为例,沟道中的空穴,在漏源之间高横向电场的作用下被加速,形成高能载流子,高能载流子与硅晶格碰撞,产生电离的电子空穴对,电子由衬底收集,形成衬底电流,大部分碰撞产生的空穴,流向漏极,但还有部分空穴,在纵向电场的作用下,注入到栅极中形成栅极电流,这种现象称为热载流子注入(Hot Carrier Injection)。
热载流子会造成硅衬底与二氧化硅栅氧界面处能键的断裂,在硅衬底与二氧化硅栅氧界面处产生界面态,导致器件性能,如阈值电压、跨导以及线性区/饱和区电流的退化,最终造成MOS器件失效。MOS器件失效通常首先发生在漏端,这是由于载流子通过整个沟道的电场加速,在到达漏端后,载流子的能量达到最大值,因此漏端的热载流子注入现象比较严重。因此,如何减小半导体器件热载流子注入损伤成为本领域工作人员的研究热点。
如图1~3所示,通常工艺中,MOS器件的减小热载流子注入损伤的离子注入方法包括:
首先,提供衬底11,所述衬底11包括源极区域和漏极区域,所述源极区域中形成有源极延伸区14,所述漏极区域中形成有漏极延伸区15,所述衬底11上形成有栅极结构12,随后在衬底11和栅极结构12上沉积形成侧墙沉积层13,如图1所示;
接下来,采用各向异性的干法刻蚀工艺对侧墙沉积层13进行刻蚀,以在源极区域上方形成源极侧墙13a,在漏极区域上方形成漏极侧墙13b,所述源极侧墙13a和漏极侧墙13b为对称结构,如图2所示;
然后,进行源漏重掺杂以及退火工艺,在衬底中形成源极重掺杂区141和漏极重掺杂区151,如图3所示;
可以得知,源极重掺杂区141和漏极重掺杂区151的位置受源极侧墙13a和漏极侧墙13b的影响,即,源极重掺杂区141和漏极重掺杂区151中掺杂离子距离器件沟道的距离由侧墙的宽度所决定。因此,本领域技术人员亟需提供一种通过改变侧墙的宽度进而改善热载流子注入损伤的离子注入方法。
发明内容
本发明的目的是提供了一种通过改变侧墙的宽度进而改善热载流子注入损伤的离子注入方法。
为解决上述问题,本发明提供一种改善热载流子注入损伤的离子注入方法,包括:
步骤S01、提供衬底,所述衬底包括至少一晶体管区域,所述晶体管区域包括栅极结构、源极区域和漏极区域;
步骤S02、在所述衬底上依次淀积侧墙层、保护层以及光刻胶层,所述侧墙层覆盖所述栅极结构、源极区域以及漏极区域;
步骤S03、对所述漏极区域进行光刻,去除所述漏极区域的光刻胶层以及保护层,同时去除所述源极区域的光刻胶层;
步骤S04、对所述衬底进行紫外线处理工艺;
步骤S05、去除所述源极区域的保护层,并对所述侧墙层进行刻蚀,以在所述源极区域上方形成源极侧墙,并在所述漏极区域上方形成漏极侧墙,其中,所述源极侧墙的截面宽度小于所述漏极侧墙的截面宽度;
步骤S06、对所述晶体管区域进行离子注入,形成晶体管结构。
优选的,步骤S05中,所述漏极侧墙的截面宽度和源极侧墙的截面宽度的宽度比在2.5~1.5之间。
优选的,步骤S02中,采用等离子气相沉积工艺形成所述侧墙层,所述侧墙层的材料为氮化硅。
优选的,步骤S02中,采用等离子气相沉积工艺或原子层淀积工艺形成所述保护层,所述保护层的材料为非晶碳或二氧化硅。
优选的,步骤S03中,采用湿法刻蚀工艺或灰化工艺去除所述光刻胶层。
优选的,步骤S04中,对所述漏极区域进行紫外灯的照射,所述紫外灯的波长在100~400nm之间,照射的时间在100s~1000s之间。
优选的,步骤S05中,对所述侧墙层采用各项异形的干法刻蚀工艺进行刻蚀。
优选的,步骤S05中,所述漏极区域经过紫外线处理工艺后,刻蚀所述漏极区域上方的侧墙层与刻蚀所述源极区域上方的侧墙层的刻蚀比在0.5~0.75之间。
优选的,步骤S06中,所述采用中性离子对所述晶体管区域进行离子注入,所述中性离子为锗离子或氙离子。
优选的,所述衬底放置在基板上,所述基板的温度在300℃~480℃之间。
从上述技术方案可以看出,本发明提供的改善热载流子注入损伤的离子注入方法中,通过在侧墙刻蚀前对漏极区域增加一步紫外线处理工艺,使得漏极区域上方的侧墙层与源极区域上方的侧墙层具有不同的刻蚀速率,进而使源极侧墙的截面宽度小于所述漏极侧墙的截面宽度,导致漏端的掺杂离子离沟道距离被拉远,而源端的掺杂离子与沟道和衬底的距离被拉近,降低了漏端的纵向电场强度,减小了器件热载流子注入的损伤。
附图说明
图1至图3为现有技术中离子注入方法中的器件剖面示意图;
图4为本发明改善热载流子注入损伤的离子注入方法优选实施方式的流程示意图;
图5至图10为本发明改善热载流子注入损伤的离子注入方法优选实施例中所形成器件剖面结构示意图。
具体实施方式
为使本发明的内容更加清楚易懂,以下结合说明书附图,对本发明的内容作进一步说明。当然本发明并不局限于该具体实施例,本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。其次,本发明利用示意图进行了详细的表述,在详述本发明实例时,为了便于说明,示意图不依照一般比例局部放大,不应以此作为对本发明的限定。
上述及其它技术特征和有益效果,将结合实施例及附图4至图10对本发明的改善热载流子注入损伤的离子注入方法进行详细说明。图4为本发明改善热载流子注入损伤的离子注入方法的一较佳具体实施例的流程示意图;图5~10为采用图4所示形成方法所制造出的器件剖面结构示意图。
请参阅图4,在本实施例中,本发明提供一种改善热载流子注入损伤的离子注入方法具体包括以下步骤:
步骤S01、提供衬底10,衬底10包括至少一晶体管区域,晶体管区域包括栅极结构20、源极区域40和漏极区域30(请参阅图5)。
具体的,本实施例中,在硅衬底10上形成至少一晶体管区域,晶体管区域包括有源区和浅沟槽隔离,有源区上具有栅极结构20、源极区域40和漏极区域30;此外,还包括阱注入,栅极氧化层的形成等,在此不一一列举。本实施例中的晶体管区域优选为PMOS,在一些实施例中,还可包括第二晶体管区域,第二栅极等区域,如第一晶体管区域为PMOS,则第二晶体管区域为NMOS。
步骤S02、在衬底10上依次淀积侧墙层50、保护层60以及光刻胶层70,侧墙层50覆盖栅极结构20、源极区域40以及漏极区域30(请参阅图6)。
其中,优选采用等离子气相沉积工艺形成侧墙层50,侧墙层50的材料为氮化硅,氮化硅的厚度为200A,沉积完成后的台阶覆盖率高于85%,使氮化硅层将栅极结构20、源极区域40和漏极区域30全部均匀覆盖。
本实施例中,优选采用等离子气相沉积工艺或原子层淀积工艺形成保护层60,保护层60的材料为非晶碳或二氧化硅。以非晶碳为例,在衬底10上用PECVD的方法沉积一层厚度为1000-2000A的非晶碳薄膜60,并在此基础上旋涂光刻胶70,将栅极结构20、源极区域40和漏极区域30全部覆盖。
步骤S03、对漏极区域30进行光刻,去除漏极区域30的光刻胶层70以及保护层60,同时去除源极区域40的光刻胶层70(请参阅图7)。
本步骤中,对漏极区域30进行光刻,去除漏极区域30的光刻胶层70以及保护层60,优选采用湿法刻蚀工艺或灰化工艺去除光刻胶层70,再通过HF酸湿法刻蚀掉保护层60;同时去除源极区域40的光刻胶层70,但是保留源极区域40的保护层60。
步骤S04、对衬底10进行紫外线处理工艺(请参阅图8)。
具体的,本步骤中,采用AMAT或者LAM的紫外线照射设备对衬底10进行照射,其中,用于装载硅片的基板的温度在300度到480度之间,本实施例中温度优选为300度,紫外灯的波长在100~400nm之间,照射的时间在100s~1000s之间,本实施例中处理的时间优选为300S,漏极区域30紫外线处理前有较高的SiH/N-H比,刻蚀速率较高,但是漏极区域30经过紫外线处理后有较低的SiH/N-H比,刻蚀速率较低,而源极区域40则由于有保护层60的保护,不受紫外线工艺的影响,此外本步骤还包括硅片的传输,预加热,冷却等常规步骤。
步骤S05、去除源极区域40的保护层60,并对侧墙层50进行刻蚀,以在源极区域40上方形成源极侧墙41,并在漏极区域30上方形成漏极侧墙31,其中,源极侧墙41的截面宽度小于漏极侧墙31的截面宽度(请参阅图9)。
具体的,对侧墙层50采用各项异形的干法刻蚀工艺进行刻蚀,形成的侧墙仅覆盖栅极结构20的两侧,而栅极结构20顶部、源极区域40以及漏极区域30表面的侧墙层50则被去除。
由于漏极区域30经过紫外线处理工艺后,刻蚀侧墙层的速率不一致,因此刻蚀漏极区域30上方的侧墙31与刻蚀源极区域40上方的侧墙41的刻蚀比在0.5~0.75之间,最终形成的漏极侧墙31的截面宽度和源极侧墙41的截面宽度的宽度比优选在2.5~1.5之间;本实施例中的漏极侧墙31的宽度为175A,而源极侧墙41的宽度为100A。
步骤S06、对晶体管区域进行离子注入,形成晶体管结构(请参阅图10)。
本实施例可采用中性离子对晶体管区域进行离子注入,中性离子为锗离子或氙离子,也再次旋涂光刻胶,将该晶体管区域全部覆盖,对其他晶体管区域进行离子注入,最终完成晶体管结构的制作。
由图10可以看出,由于离子注入,形成了源极重掺杂区412以及漏极重掺杂区312,源极重掺杂区412的掺杂离子与器件沟道的距离被拉近,漏极重掺杂区312的掺杂离子与器件沟道的距离被拉远。使得漏极重掺杂区312与栅极结构20之间的交叠区域面积减小,当栅极加上电压后,在漏极产生的纵向电场强度减弱,因此,由横向电场加速的载流子碰撞产生的的电子空穴对,空穴会在较弱的纵向电场作用下想栅极中注入,从而减小了由于热载流子注入而形成的栅极电流,减小了半导体器件热载流子注入的损伤。
综上所述,本发明提供的改善热载流子注入损伤的离子注入方法中,通过在侧墙刻蚀前对漏极区域增加一步紫外线处理工艺,使得漏极区域上方的侧墙层与源极区域上方的侧墙层具有不同的刻蚀速率,进而使源极侧墙的截面宽度小于所述漏极侧墙的截面宽度,导致漏端的掺杂离子离沟道距离被拉远,而源端的掺杂离子与沟道和衬底的距离被拉近,降低了漏端的纵向电场强度,减小了器件热载流子注入的损伤。
以上的仅为本发明的优选实施例,实施例并非用以限制本发明的专利保护范围,因此凡是运用本发明的说明书及附图内容所作的等同结构变化,同理均应包含在本发明的保护范围内。

Claims (10)

1.一种改善热载流子注入损伤的离子注入方法,其特征在于,包括:
步骤S01、提供衬底,所述衬底包括至少一晶体管区域,所述晶体管区域包括栅极结构、源极区域和漏极区域;
步骤S02、在所述衬底上依次淀积侧墙层、保护层以及光刻胶层,所述侧墙层覆盖所述栅极结构、源极区域以及漏极区域;
步骤S03、对所述漏极区域进行光刻,去除所述漏极区域的光刻胶层以及保护层,同时去除所述源极区域的光刻胶层;
步骤S04、对所述衬底进行紫外线处理工艺;
步骤S05、去除所述源极区域的保护层,并对所述侧墙层进行刻蚀,以在所述源极区域上方形成源极侧墙,并在所述漏极区域上方形成漏极侧墙,其中,所述源极侧墙的截面宽度小于所述漏极侧墙的截面宽度;
步骤S06、对所述晶体管区域进行离子注入,形成晶体管结构。
2.如权利要求1所述的改善热载流子注入损伤的离子注入方法,其特征在于,步骤S05中,所述漏极侧墙的截面宽度和源极侧墙的截面宽度的宽度比在2.5~1.5之间。
3.如权利要求1所述的改善热载流子注入损伤的离子注入方法,其特征在于,步骤S02中,采用等离子气相沉积工艺形成所述侧墙层,所述侧墙层的材料为氮化硅。
4.如权利要求1所述的改善热载流子注入损伤的离子注入方法,其特征在于,步骤S02中,采用等离子气相沉积工艺或原子层淀积工艺形成所述保护层,所述保护层的材料为非晶碳或二氧化硅。
5.如权利要求1所述的改善热载流子注入损伤的离子注入方法,其特征在于,步骤S03中,采用湿法刻蚀工艺或灰化工艺去除所述光刻胶层。
6.如权利要求1所述的改善热载流子注入损伤的离子注入方法,其特征在于,步骤S04中,对所述漏极区域进行紫外灯的照射,所述紫外灯的波长在100~400nm之间,照射的时间在100s~1000s之间。
7.如权利要求1所述的改善热载流子注入损伤的离子注入方法,其特征在于,步骤S05中,对所述侧墙层采用各项异形的干法刻蚀工艺进行刻蚀。
8.如权利要求1所述的改善热载流子注入损伤的离子注入方法,其特征在于,步骤S05中,所述漏极区域经过紫外线处理工艺后,刻蚀所述漏极区域上方的侧墙层与刻蚀所述源极区域上方的侧墙层的刻蚀比在0.5~0.75之间。
9.如权利要求1所述的改善热载流子注入损伤的离子注入方法,其特征在于,步骤S06中,所述采用中性离子对所述晶体管区域进行离子注入,所述中性离子为锗离子或氙离子。
10.如权利要求1~9任一所述的改善热载流子注入损伤的离子注入方法,其特征在于,所述衬底放置在基板上,所述基板的温度在300℃~480℃之间。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113658869A (zh) * 2021-08-16 2021-11-16 成都京东方光电科技有限公司 薄膜晶体管及其制作方法、显示器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235675A (ja) * 1994-02-24 1995-09-05 Nec Corp 半導体装置の製造方法
US6168999B1 (en) * 1999-09-07 2001-01-02 Advanced Micro Devices, Inc. Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain
US6410382B1 (en) * 1999-04-19 2002-06-25 Hyundai Electronics Industries Co., Ltd. Fabrication method of semiconductor device
CN104157557A (zh) * 2014-08-15 2014-11-19 上海华力微电子有限公司 改善热载流子注入损伤的离子注入方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235675A (ja) * 1994-02-24 1995-09-05 Nec Corp 半導体装置の製造方法
US6410382B1 (en) * 1999-04-19 2002-06-25 Hyundai Electronics Industries Co., Ltd. Fabrication method of semiconductor device
US6168999B1 (en) * 1999-09-07 2001-01-02 Advanced Micro Devices, Inc. Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain
CN104157557A (zh) * 2014-08-15 2014-11-19 上海华力微电子有限公司 改善热载流子注入损伤的离子注入方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113658869A (zh) * 2021-08-16 2021-11-16 成都京东方光电科技有限公司 薄膜晶体管及其制作方法、显示器件
CN113658869B (zh) * 2021-08-16 2023-07-25 成都京东方光电科技有限公司 薄膜晶体管及其制作方法、显示器件

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