CN104900652A - 一种低温多晶硅晶体管阵列基板及其制备方法、显示装置 - Google Patents

一种低温多晶硅晶体管阵列基板及其制备方法、显示装置 Download PDF

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CN104900652A
CN104900652A CN201510169378.9A CN201510169378A CN104900652A CN 104900652 A CN104900652 A CN 104900652A CN 201510169378 A CN201510169378 A CN 201510169378A CN 104900652 A CN104900652 A CN 104900652A
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陆小勇
刘政
李小龙
李栋
张慧娟
孙亮
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BOE Technology Group Co Ltd
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Abstract

本发明提供一种低温多晶硅晶体管阵列基板及其制备方法、显示装置，属于显示技术领域，其可解决现有的低温多晶硅晶体管阵列基板的多晶硅半导体有源区的沟道区与源漏扩展区或源漏掺杂区之间存在掺杂离子浓度梯度比较大，容易产生热载流子，产生漏电流的问题。本发明的低温多晶硅晶体管阵列基板及其制备方法、显示装置由于在栅极两侧设有电介质间隔区，并在多晶硅半导体有源区上的对应区域形成了缓冲区，上述缓冲区能有效防止由于热载流子效应引起的漏电流；同时，栅极绝缘层和栅极通过一次构图工艺形成能够改善栅极绝缘层的界面缺陷；电介质间隔区还能保护栅极绝缘层和栅极的侧壁免受后续的功能层制备工艺损害。

Description

一种低温多晶硅晶体管阵列基板及其制备方法、显示装置
技术领域
本发明属于显示技术领域，具体涉及一种低温多晶硅晶体管阵列基板及其制备方法、显示装置。
背景技术
如图1、2所示，现有技术中的低温多晶硅晶体管阵列基板，包括衬底1和在所述衬底1上设置的多晶硅半导体有源区2，以及与所述多晶硅半导体有源区2绝缘设置的栅极4，其中，栅极4与多晶硅半导体有源区2之间设有栅极绝缘层3，在通过构图工艺分别形成栅极绝缘层3图形和栅极4的图形时会对栅极绝缘层3进行两次刻蚀，使得栅极绝缘层3的致密度降低，与多晶硅半导体有源区2接触的界面产生界面缺陷。
如图1所示，含有N型金属-氧化物-半导体晶体管(Nmos)的低温多晶硅晶体管阵列基板还包括位于多晶硅半导体有源区2两侧的依次设置源漏扩展区5和源漏掺杂区6，其中，先以栅极4的掩膜板进行遮挡以中低量注入磷或砷等离子形成的源漏扩展区5(包括形成的低能量浅结)，然后再用掩膜板遮挡，以大剂量的源漏注入形成源漏掺杂区6。
上述的源漏扩展区5在高离子浓度的源漏掺杂区6和低离子浓度的多晶硅半导体有源区2的沟道区间形成渐变的横向离子浓度梯度。源漏扩展区5的横向离子浓度梯度减小了结和沟道区间的电场，把结中的最大电场位置与沟道中的最大电流路径分离，以防止产生热载流子。
但是，即使设置有源漏扩展区5，该源漏扩展区5与多晶硅半导体有源区2的漏电流依然比较大，尤其是接触多晶硅半导体有源区2的部分。
如图2所示，含有P型金属-氧化物-半导体晶体管(Pmos)的低温多晶硅晶体管阵列基板还包括位于多晶硅半导体有源区2两侧的设置源漏掺杂区6，其中，源漏掺杂区6为大剂量的源漏注入形成的。此时，源漏掺杂区6与多晶硅半导体有源区2之间没有降低的横向浓度梯度，因此浓度梯度比较大，更容易产生热载流子。
发明内容
本发明的目的是解决现有技术的低温多晶硅晶体管阵列基板的多晶硅半导体有源区的沟道区与源漏扩展区或源漏掺杂区之间存在掺杂离子浓度梯度比较大，容易产生热载流子，产生漏电流的问题，提供一种能够防止产生热载流子的低温多晶硅晶体管阵列基板及其制备方法、显示装置。
解决本发明技术问题所采用的技术方案是一种低温多晶硅晶体管阵列基板，包括：
衬底和在所述衬底上设置的多晶硅半导体有源区，以及与所述多晶硅半导体有源区绝缘设置的栅极，所述栅极两侧设有电介质间隔区，所述电介质间隔区将所述栅极的侧面包围并覆盖所述多晶硅半导体有源区的端部；
所述多晶硅半导体有源区与所述电介质间隔区相对应的位置包括缓冲区。
优选的，所述栅极和多晶硅半导体有源区之间设有栅极绝缘层；所述栅极绝缘层具有与所述栅极相同的图形。
优选的，所述电介质间隔区从靠近所述栅极的一侧到远离所述栅极的一侧的最大长度为0.1-1um。
优选的，所述电介质间隔区至少包括一层电介质材料。
优选的，所述电介质材料选自二氧化硅或氮化硅。
本发明的另一个目的还包括提供一种上述低温多晶硅晶体管阵列基板的制备方法，包括：
在衬底上形成多晶硅半导体有源层；
在所述多晶硅半导体有源层上形成栅极绝缘层；
在所述栅极绝缘层上形成栅极层；
通过构图工艺形成栅极绝缘层和栅极的图形；
在形成栅极图形的衬底上形成电介质层，通过构图工艺形成电介质间隔区，所述电介质间隔区将所述栅极的侧面包围并覆盖所述多晶硅半导体有源区的端部。
优选的，所述电介质间隔区从靠近所述栅极的一侧到远离所述栅极的一侧的最大长度为0.1-1um。
优选的，所述电介质间隔区至少包括一层电介质材料。
优选的，所述电介质材料选自二氧化硅或氮化硅。
优选的，在形成电介质间隔区之后，还包括通过掺杂形成位于所述多晶硅半导体有源区两侧的缓冲区的步骤。
本发明的另一个目的还包括提供一种显示装置，包括上述的低温多晶硅晶体管阵列基板。
本发明的低温多晶硅晶体管阵列基板及其制备方法、显示装置由于在栅极两侧设有电介质间隔区，并在多晶硅半导体有源区上的对应区域形成了缓冲区，上述缓冲区能有效防止由于热载流子效应引起的漏电流；同时，栅极绝缘层和栅极通过一次构图工艺形成能够改善栅极绝缘层的界面缺陷；电介质间隔区还能保护栅极绝缘层和栅极的侧壁免受后续的功能层制备工艺损害。
附图说明
图1为现有技术中低温多晶硅晶体管阵列基板(Nmos)部分结构示意图。
图2为现有技术中低温多晶硅晶体管阵列基板(Pmos)部分结构示意图。
图3为本发明实施例1中低温多晶硅晶体管阵列基板(Nmos)部分结构示意图。
图4为本发明实施例1中低温多晶硅晶体管阵列基板(Pmos)部分结构示意图。
图5为本发明实施例2中形成多晶硅半导体有源区后低温多晶硅晶体管阵列基板的结构示意图。
图6为本发明实施例2中沉积栅极绝缘层后低温多晶硅晶体管阵列基板的结构示意图。
图7为本发明实施例2中形成栅极绝缘层和栅极的图形后低温多晶硅晶体管阵列基板的结构示意图。
图8为本发明实施例2中形成电介质间隔区后低温多晶硅晶体管阵列基板的结构示意图。
图9为本发明实施例2中第一次离子注入后低温多晶硅晶体管阵列基板的结构示意图。
图10为本发明实施例2中第二次离子注入后低温多晶硅晶体管阵列基板的结构示意图。
其中：
1.衬底；2.多晶硅半导体有源区；3.栅极绝缘层；4.栅极；5.源漏扩展区；6.源漏掺杂区；7.电介质间隔区；8.缓冲区。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1
如图3-4所示，本实施例提供一种低温多晶硅晶体管阵列基板，包括：
衬底1和在所述衬底1上设置的多晶硅半导体有源区，以及与所述多晶硅半导体有源区2绝缘设置的栅极4，所述栅极4两侧设有电介质间隔区7，所述电介质间隔区7将所述栅极4的侧面包围并覆盖所述多晶硅半导体有源区2的端部；所述多晶硅半导体有源区2与所述电介质间隔区7相对应的位置包括缓冲区8。
本实施例的低温多晶硅晶体管阵列基板，由于在栅极4两侧设有电介质间隔区7，在后续离子注入掺杂工序中能在多晶硅半导体有源区2的对应形成缓冲区8，该缓冲区8中杂质离子的浓度小于外侧源漏扩展区5的杂质离子的浓度大于内侧多晶硅半导体有源区2的杂质离子的浓度，上述的缓冲区8能够进一步的降低结和沟道区间的电场，把结中的最大电场位置与沟道中的最大电流路径分离，以防止产生热载流子。
优选的，所述栅极4和多晶硅半导体有源区2之间设有栅极绝缘层3；所述栅极绝缘层3具有与所述栅极4相同的图形。这样可以将栅极绝缘层3具有与所述栅极4采用一次构图工艺形成，减少刻蚀对栅极绝缘层3的损伤，减少栅极绝缘层3与多晶硅半导体有源区2之间界面缺陷。
所述电介质间隔区7从靠近所述栅极4的一侧到远离所述栅极4的一侧的最大长度为0.1-1um。若长度过小无法起到上述的作用，若长度过大无法导通源漏极。
所述电介质间隔区7至少包括一层电介质材料。也就是说电介质材料可以通过沉积多层获得。具体的层数和各层的厚度在此不作限定。
所述电介质材料选自二氧化硅或氮化硅。可以单独将二氧化硅或氮化硅沉积形成电介质间隔区7，也可以将两者先后沉积或同时沉积。应当理解的是，现有技术中的其它电介质材料也是可以适用的。
低温多晶硅晶体管阵列基板还包括位于所述多晶硅半导体有源区2两侧的源漏扩展区5。该源漏扩展区5是通过P型或N-型轻掺杂漏注入形成，进一步防止产生热载流子。
应当理解的是，低温多晶硅晶体管阵列基板还可以包括其它必要的功能层，例如，平坦化层，像素电极，各种外围金属线等，在此不再一一赘述。
实施例2
如图5-10所示，本实施例提供一种上述低温多晶硅晶体管阵列基板的制备方法，包括：
步骤1：在衬底上形成多晶硅半导体有源层；
如图5所示，在衬底1上沉积一层非晶硅层，然后，脱氢处理，采用激光退火工艺，金属诱导结晶工艺，固相结晶工艺等对非结晶层进行结晶处理，形成多晶硅半导体有源层；通过构图工艺形成多晶硅半导体有源区2的图形。
步骤2：在所述多晶硅半导体有源层上形成栅极绝缘层；
如图6所示，采用PEVCD方法沉积栅极绝缘层3，具体方法为现有技术范畴在此不再一一赘述。
步骤3：在所述栅极绝缘层上形成栅极；
如图7所示，在栅极绝缘层3上通过溅射工艺形成栅极金属层，通过构图工艺一次形成栅极4和栅极绝缘层3的图形；这样可以防止绝缘层在单独构图工艺中过多的受到刻蚀的影响导致与多晶硅半导体有源区2的接触界面产生接触缺陷。
步骤3：在栅极上形成电介质层
如图8所示，通过等离子体化学气相沉积法(PEVCD)在栅极4上沉积一层或几层电介质材料，控制沉积的条件是沉积的最终厚度度小于1um。
上述的电介质材料选自二氧化硅或氮化硅。应当理解的是，现有技术的其它电介质材料也是适用的。
接着采用构图工艺形成电介质间隔区7，所述电介质间隔区7从靠近所述栅极4的一侧到远离所述栅极4的一侧的最大长度为0.1-1um；所述电介质间隔区7将所述栅极4的侧面包围并覆盖所述多晶硅半导体有源区2的端部。该电介质间隔区7还能保护栅极绝缘层3和栅极4的侧壁免受后续的功能层制备工艺损害。
步骤4：通过掺杂形成缓冲区
如图9所示，在形成电介质间隔区7的图形之后，通过掺杂形成位于所述多晶硅半导体有源区2两侧的缓冲区8。
具体地，采用栅极掩膜对多晶硅半导体有源区2进行遮挡，对上述衬底1进行掺杂，对于N型金属-氧化物-半导体晶体管(Nmos)先以中低量注入砷离子形成的(包括形成的低能量浅结)源漏扩展区5，这时由于电介质间隔区7的遮挡使得在多晶硅半导体有源区2的对应位置形成缓冲区8，缓冲区8中砷离子浓度沿向多晶硅半导体有源区2中心的方向逐渐降低，形成砷离子的浓度梯度，这样更加有利于防止产生热载流子；
如图10所示，然后，大剂量的源漏注入形成源漏掺杂区6。
对于P型金属-氧化物-半导体晶体管(Pmos)可以直接大剂量的源漏注入形成源漏掺杂区6，这时由于电介质间隔区7的遮挡使得在多晶硅半导体有源区2的对应位置形成缓冲区8，缓冲区8中砷离子浓度沿向多晶硅半导体有源区2中心的方向逐渐降低，形成离子的浓度梯度，这样更加有利于防止产生热载流子。
应当理解的是，上述的掺杂方法及掺杂的离子均为现有技术范畴，在此不再一一赘述。
可选的，可以继续制备低温多晶硅晶体管阵列基板的其它必要功能层，上述必要功能的制备方法为现有技术在此不再一一赘述。
实施例3
本实施例提供一种显示装置由于采用上述的低温多晶硅晶体管阵列基板
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (11)

1.一种低温多晶硅晶体管阵列基板，包括：衬底和在所述衬底上设置的多晶硅半导体有源区，以及与所述多晶硅半导体有源区绝缘设置的栅极，其特征在于，所述栅极两侧设有电介质间隔区，所述电介质间隔区将所述栅极的侧面包围并覆盖所述多晶硅半导体有源区的端部；
所述多晶硅半导体有源区与所述电介质间隔区相对应的位置包括缓冲区。
2.如权利要求1所述的低温多晶硅晶体管阵列基板，其特征在于，所述栅极和多晶硅半导体有源区之间设有栅极绝缘层；所述栅极绝缘层具有与所述栅极相同的图形。
3.如权利要求1所述的低温多晶硅晶体管阵列基板，其特征在于，所述电介质间隔区从靠近所述栅极的一侧到远离所述栅极的一侧的最大长度为0.1-1um。
4.如权利要求1所述的低温多晶硅晶体管阵列基板，其特征在于，所述电介质间隔区至少包括一层电介质材料。
5.如权利要求4所述的低温多晶硅晶体管阵列基板，其特征在于，所述电介质材料选自二氧化硅或氮化硅。
6.一种如权利要求1-5任一项所述的低温多晶硅晶体管阵列基板的制备方法，其特征在于，包括：
在衬底上形成多晶硅半导体有源层；
在所述多晶硅半导体有源层上形成栅极绝缘层；
在所述栅极绝缘层上形成栅极层；
通过构图工艺形成栅极绝缘层和栅极的图形；
在形成栅极图形的衬底上形成电介质层，通过构图工艺形成电介质间隔区，所述电介质间隔区将所述栅极的侧面包围并覆盖所述多晶硅半导体有源区的端部。
7.如权利要求6所述的低温多晶硅晶体管阵列基板的制备方法，其特征在于，所述电介质间隔区从靠近所述栅极的一侧到远离所述栅极的一侧的最大长度为0.1-1um。
8.如权利要求6所述的低温多晶硅晶体管阵列基板的制备方法，其特征在于，所述电介质间隔区至少包括一层电介质材料。
9.如权利要求8所述的低温多晶硅晶体管阵列基板的制备方法，其特征在于，所述电介质材料选自二氧化硅或氮化硅。
10.如权利要求6所述的低温多晶硅晶体管阵列基板的制备方法，其特征在于，在形成电介质间隔区之后，还包括通过掺杂形成位于所述多晶硅半导体有源区两侧的缓冲区的步骤。
11.一种显示装置，其特征在于，包括如权利要求1-5任一项所述的低温多晶硅晶体管阵列基板。
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