CN104733527A - 耐压40伏特以上的ldmos器件的结构 - Google Patents

耐压40伏特以上的ldmos器件的结构 Download PDF

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CN104733527A
CN104733527A CN201310717896.0A CN201310717896A CN104733527A CN 104733527 A CN104733527 A CN 104733527A CN 201310717896 A CN201310717896 A CN 201310717896A CN 104733527 A CN104733527 A CN 104733527A
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drift region
region
ldmos
ldmos device
voltage
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刘冬华
钱文生
段文婷
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

本发明公开了一种耐压40伏特以上的LDMOS器件的结构，该LDMOS器件的漏端漂移区下方具有一个掺杂类型与漂移区掺杂类型相反的掺杂区域。本发明由于在漏端一侧增加了一个掺杂类型与漂移区掺杂类型相反的区域，使得LDMOS器件具有了漏端辅助Resurf效应，不仅提高了器件的击穿电压，而且解决了传统Resurf技术在提高器件击穿电压的同时，会造成漂移区中的杂质被中和和漂移区中的电流通道变窄的问题。

Description

耐压40伏特以上的LDMOS器件的结构
技术领域
本发明涉及集成电路制造领域，特别是涉及耐压40伏特以上的LDMOS器件。
背景技术
信息技术和全球通讯市场的飞速发展对高压集成电路的性能提出了更高的要求。作为一种性价比很高的器件，LDMOS由于更容易与CMOS工艺兼容而在高压集成电路中获得了广泛应用。
LDMOS管具有负温效应，其漏电流在受热时自动均流，不会像双极型管的正温度效应那样在收集极电流局部形成热点，所以管子不易损坏，负载失配和过激励的承受能力也大大加强。同样由于LDMOS管的自动均流作用，其输入－输出特性曲线在1dB压缩点（大信号运用的饱和区段）下弯较缓，所以动态范围变宽，有利于模拟和数字电视射频信号放大。LDMOS在小信号放大时近似线性，几乎没有交调失真，很大程度简化了校正电路。此外，MOS器件的直流栅极电流几乎为零，偏置电路简单，无需复杂的带正温度补偿的有源低阻抗偏置电路。
对LDMOS而言，外延层的厚度、掺杂浓度、漂移区的长度是其最重要的特性参数。高压LDMOS器件的耐压和导通电阻取决于外延层的浓度、厚度及漂移区长度的折中选择。因为耐压和导通阻抗对于外延层的浓度和厚度的要求是矛盾的。高的击穿电压要求厚的轻掺杂外延层和长的漂移区，而低的导通电阻则要求薄的重掺杂外延层和短的漂移区，因此必须选择最佳外延参数和漂移区长度，以便在满足一定的源漏击穿电压的前提下，得到最小的导通电阻。
Resurf（降低表面电场）技术是经常被采用的一种提高器件耐压（或者降低器件导通电阻）的方法，特别是对于较高耐压的LDMOS器件，比如应用于40伏特以上的LDMOS器件（见图1）。Resurf技术的原理是，比如对N型LDMOS来说，在N型漂移区的底部形成P型区域，实现对漂移区的纵向相互耗尽。而不采用Resurf技术的传统NLDMOS，漂移区的耗尽是靠N型漂移区与P型沟道形成的横向耗尽来实现的。Resurf引起的纵向耗尽将使得漂移区的耗尽长度更长，从而实现更高的耐压。
但传统Resurf技术也存在缺点，比如P型掺杂区位于N型漂移区之下，因此，工艺制作过程中，会中和掉部分漂移区的杂质；同时P型掺杂区也会导致N型漂移区的纵向宽度变小，导致电流路径变窄，电路密度变大，从而可能引起NLDMOS中的寄生NPN三极管的大电流注入效应变严重，影响器件的开态击穿电压。
发明内容
本发明要解决的技术问题是提供一种耐压40伏特以上的LDMOS器件的结构，它可以提高LDMOS器件的击穿电压。
为解决上述技术问题，本发明的耐压40伏特以上的LDMOS器件的结构，带有漏端辅助Resurf，其漏端漂移区下方具有一个掺杂类型与漂移区掺杂类型相反的掺杂区域。
所述LDMOS为NLDMOS，所述掺杂区域为P型掺杂区。所述P型掺杂区可以为一高压P阱。
本发明的40伏特以上LDMOS器件，由于在漏端一侧增加了一个掺杂类型与漂移区掺杂类型相反的区域，使得LDMOS器件具有了漏端辅助Resurf效应，不仅提高了器件的击穿电压，而且解决了传统Resurf技术在提高器件击穿电压的同时，会造成漂移区中的杂质被中和和漂移区中的电流通道变窄的问题。
附图说明
图1是传统的40伏特以上NLDMOS器件的结构。
图2是本发明的带有漏端辅助Resurf的40伏特以上NLDMOS器件的结构。
图3是图2结构的NLDMOS器件与图1结构的NLDMOS器件的漏端耗尽比较图。图2结构的NLDMOS器件具有更多的漏端耗尽。
图4图2结构的NLDMOS器件与图1结构的NLDMOS器件的击穿电压比较图。图2结构的NLDMOS器件具有更高的击穿电压。
图中附图标记说明如下：
1：P型衬底
2：N型深阱（DNW)
3a：沟道一侧高压P阱(HVPW)
3b：漏端一侧高压P阱(HVPW)
4：浅隔离槽（STI）
5：P阱（PW)
6：N阱（NW)
7：栅极
8：P型重掺杂区
9a：N型重掺杂区（源端）
9b：N型重掺杂区（漏端）
10：隔离侧墙
具体实施方式
为对本发明的技术内容、特点与功效有更具体的了解，现结合附图，详述如下：
本发明的耐压40伏特以上的LDMOS器件，其漏端带有辅助Resurf。对于N型LDMOS来说，是在NLDMOS的漏端底部，加入一P型掺杂区域。这一P型掺杂区可以只是在漏端底部，也可以同时向漂移区覆盖一小部分区域（如果覆盖到漂移区的区域，则这个区域不能太大，需要严格控制其小于1微米）。
以上海华虹宏力半导体制造有限公司的BCD180G的40伏特模拟NLDMOS器件为例，漏端的P型掺杂区可以通过高压P阱来实现，即在这个器件的漏端注入位置形成高压P阱。由于高压P阱注入的剂量较低（一般注入硼离子，注入剂量1.1E12～1.2E13cm-2），同时退火推进到较深的位置，因此最终可以在漏端底部形成一个P型掺杂区域，如图2所示。该P型掺杂区域和N型漂移区形成纵向的相互耗尽，这样，在提高器件击穿电压的同时，就不会造成漂移区中的N型杂质被中和，也不会使NLDMOS器件在漂移区中的电流通道变窄。

Claims (3)

1.耐压40伏特以上的LDMOS器件的结构，其特征在于，该LDMOS器件的漏端漂移区下方具有一个掺杂类型与漂移区掺杂类型相反的掺杂区域。
2.根据权利要求1所述的LDMOS器件的结构，其特征在于，所述LDMOS为NLDMOS，所述掺杂区域为P型掺杂区。
3.根据权利要求2所述的LDMOS器件的结构，其特征在于，所述P型掺杂区为高压P阱。
CN201310717896.0A 2013-12-23 2013-12-23 耐压40伏特以上的ldmos器件的结构 Pending CN104733527A (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5378912A (en) * 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
CN101217161A (zh) * 2007-12-28 2008-07-09 中国电子科技集团公司第五十五研究所 无负阻ldmos器件结构及其生产方法
CN101465378A (zh) * 2007-12-20 2009-06-24 夏普株式会社 半导体器件及其制造方法
CN102790089A (zh) * 2012-07-24 2012-11-21 华中科技大学 一种漏极下具有埋层的射频ldmos器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5378912A (en) * 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
CN101465378A (zh) * 2007-12-20 2009-06-24 夏普株式会社 半导体器件及其制造方法
CN101217161A (zh) * 2007-12-28 2008-07-09 中国电子科技集团公司第五十五研究所 无负阻ldmos器件结构及其生产方法
CN102790089A (zh) * 2012-07-24 2012-11-21 华中科技大学 一种漏极下具有埋层的射频ldmos器件

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Application publication date: 20150624