CN104716110B - 芯片封装结构及其制造方法 - Google Patents

芯片封装结构及其制造方法 Download PDF

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CN104716110B
CN104716110B CN201410111967.7A CN201410111967A CN104716110B CN 104716110 B CN104716110 B CN 104716110B CN 201410111967 A CN201410111967 A CN 201410111967A CN 104716110 B CN104716110 B CN 104716110B
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chip
packaging structure
thermal column
perforation
opening
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CN104716110A (zh
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廖宗仁
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Chipmos Technologies Inc
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Abstract

一种芯片封装结构及其制造方法，该芯片封装结构包括导线架、芯片、至少一散热柱以及封装胶体。导线架包括芯片座以及多个引脚。芯片座具有至少一贯孔。引脚环绕芯片座设置。芯片设置于芯片座上并电性连接至引脚。芯片包括主动表面以及相对主动表面的背面。芯片以背面设置于芯片座上。散热柱设置于背面并穿过贯孔。封装胶体包覆芯片、至少部份引脚以及芯片座。封装胶体包括至少一开口，以暴露散热柱。一种制造此芯片封装结构的方法也被提出。

Description

芯片封装结构及其制造方法
技术领域
本发明是有关于一种半导体封装结构及其制造方法，且特别是有关于一种芯片封装结构及其制造方法。
背景技术
在半导体产业中，集成电路（Integrated Circuits,IC）的生产，主要分为三个阶段：晶圆（wafer）的制造、集成电路的制作以及集成电路的封装（Package）等。其中，裸芯片是经由晶圆（Wafer）制作、电路设计、光罩制作以及切割晶圆等步骤而完成，而每一颗由晶圆切割所形成的裸芯片，在经由裸芯片上的接点与外部信号电性连接后，可再以封胶材料将裸芯片包覆着，其封装的目的在于防止裸芯片受到湿气、热量、噪声的影响，并提供裸芯片与外部电路之间电性连接的媒介，如此即完成集成电路的封装步骤。
随着集成电路的密集度的增加，芯片的封装结构越来越复杂而多样化。另一方面，为了提高封装结构的散热效果，通常会在封装结构上设置散热片。传统散热方式是藉由粘胶（adhesive）或是焊料（solder）将散热片贴附在封装结构表面，然而此种散热方式散热片往往无法牢固地贴合在封装结构上，以至于散热片可能从封装结构上剥离或脱落，而影响产品的生产良率以及使用上的可靠度，更需额外耗费散热片的成本。
发明内容
本发明提供一种芯片封装结构，其可提升散热效率，节省生产成本。
本发明提供一种芯片封装结构的制作方法，其制作出的芯片封装结构可提升散热效率，节省生产成本。
本发明的一种芯片封装结构，其包括导线架、芯片、至少一散热柱以及封装胶体。导线架包括芯片座以及多个引脚。芯片座具有至少一贯孔。引脚环绕芯片座设置。芯片设置于芯片座上并电性连接至引脚。芯片包括主动表面以及相对主动表面的背面。芯片以背面设置于芯片座上。散热柱设置于背面并穿过贯孔。封装胶体包覆芯片、至少部份引脚以及芯片座。封装胶体包括至少一开口，以暴露散热柱。
一种芯片封装结构的制造方法包括下列步骤。提供晶圆。晶圆包括具有导电图案的主动表面以及相对主动表面的背面，其中晶圆包括多个彼此连接且阵列排列的芯片。设置具有多个开孔的图案化干膜层于晶圆的背面。进行电镀工艺，以图案化干膜层为掩膜而分别于开孔内形成多个散热柱。移除图案化干膜层。切割晶圆以使芯片彼此分离。各芯片具有散热柱的至少其中之一。提供导线架。导线架包括芯片座以及多个引脚。芯片座具有至少一贯孔。引脚环绕芯片座设置。设置芯片的其中之一于芯片座上并电性连接芯片至引脚，并以芯片的散热柱穿过贯孔。提供封装胶体，以包覆芯片、至少部份引脚以及芯片座。封装胶体包括至少一开口，并暴露散热柱。
在本发明的一实施例中，上述的散热柱的数量为多个。
在本发明的一实施例中，上述的散热柱位于贯孔内，且开口暴露散热柱。
在本发明的一实施例中，上述的开口的数量为多个。开口分别暴露散热柱。
在本发明的一实施例中，上述的贯孔的数量为多个。散热柱分别位于贯孔内。
在本发明的一实施例中，上述的开口至少暴露各散热柱的顶面。
在本发明的一实施例中，上述的芯片封装结构更包括多个导线。导线分别电性连接芯片与引脚。
在本发明的一实施例中，上述的各引脚包括内引脚以及外引脚。导线分别电性连接芯片与内引脚。
在本发明的一实施例中，上述的封装胶体包覆内引脚。
在本发明的一实施例中，上述的芯片座用以承载芯片的上表面与各引脚用以与芯片电性连接的上表面之间具有高度差。
在本发明的一实施例中，上述的开口暴露至少部份芯片座。
基于上述，本发明的芯片封装结构将散热柱通过电镀的方式直接形成于芯片的背面，并将芯片设置于导线架的芯片座上，且散热柱穿过芯片座的贯孔，而封装胶体更包括对应于散热柱的开口，以暴露散热柱。如此，本发明的芯片封装结构即可通过被封装胶体暴露的散热柱将芯片所产生的热能直接散逸至外界。因此，本发明的芯片封装结构确实可提升芯片封装结构的散热效能，更可省去设置散热膏或散热片等额外的散热元件的成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A至图1G是依照本发明的一实施例的一种芯片封装结构的制作方法的流程剖面示意图。
图2是图1G的芯片设置于芯片座上的仰视示意图。
图3是依照本发明的一实施例的一种芯片封装结构的剖面示意图。
图4是依照本发明的另一实施例的一种芯片封装结构的剖面示意图。
【符号说明】
100、100a、100b：芯片封装结构
110：导线架
112：芯片座
112a：贯孔
114：引脚
114a：内引脚
114b：外引脚
120：芯片
122：主动表面
124：背面
126：导电图案
130：散热柱
140：封装胶体
142：开口
150：基材
160：导线
170：图案化干膜层
172：开孔
具体实施方式
有关本发明的前述及其他技术内容、特点与功效，在以下配合参考图式的各实施例的详细说明中，将可清楚的呈现。以下实施例中所提到的方向用语，例如：“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附加附图的方向。因此，使用的方向用语是用来说明，而并非用来限制本发明。并且，在下列各实施例中，相同或相似的元件将采用相同或相似的标号。
图1A至图1G是依照本发明的一实施例的一种芯片封装结构的制作方法的流程剖面示意图。本实施例的芯片封装结构的制作方法可包括下列步骤：首先，请先参照图1A，提供晶圆，其如图1A所示包括主动表面122、相对于主动表面122的背面124以及导电图案126。晶圆包括多个彼此连接且阵列排列的芯片120。在此须说明的是，为了图面简洁，图1A仅绘示晶圆的多个阵列排列的芯片120中的其中之一，也就是说，芯片120可为晶圆级芯片。此外，在本实施例中，导电图案126可例如通过电镀而形成于晶圆的主动表面122上，其可作为各芯片120的球底金属层（Under-Bump Metallization,UBM）或重配置线路层（Redistribution Layer，RDL）。在本实施例中，晶圆可例如以其主动表面122设置于基材150上，其中，基材150可例如为胶带或是干膜层（dry film），并如图1A所示覆盖导电图案126。
接着，请参照图1B，设置具有多个开孔172的图案化干膜层170于芯片120的背面124上，接着再以图案化干膜层170为电镀掩膜进行电镀工艺，以分别形成如图1C所示的多个散热柱130于上述的多个开孔172内，也就是形成散热柱130于开孔172所暴露的部份背面124上，其中，各芯片120具有上述的散热柱130的至少其中之一，且散热柱130不与背面124上的其他线路层电性连接。之后，再移除图案化干膜层，以暴露出背面124以及形成于其上的散热柱130。在另一可行的实施例中，芯片120上的散热柱130及导电图案126是先以相同上述的工艺预先电镀形成于晶圆上，之后，再切割晶圆以使芯片120彼此分离。在本实施例中，可例如沿着如图1D所示的切线切割晶圆，以得到单体芯片120，以进行后续的封装工艺。
接着，请参照图1E，将上述的多个芯片120的其中之一设置于导线架110的芯片座112上，其中，导线架110包括芯片座112以及多个引脚114。引脚114环绕芯片座112设置，而芯片座112具有至少一贯孔112a。芯片120以其背面124设置于芯片座112上，并电性连接至引脚114。详细来说，贯孔112a的位置对应于散热柱130，使芯片120以其背面124设置于芯片座112上时，散热柱130得以穿过贯孔112a。并且，芯片120的背面124的尺寸应大于贯孔112a的尺寸，使芯片120的背面124得以承靠于芯片座112上。在本实施例中，芯片120可例如通过粘着层固定于芯片座112上，并通过多个导线160电性连接至引脚114，也就是说，芯片120是利用打线接合（wire bonding）的方式与引脚114形成电性连接。
具体而言，各引脚114可包括内引脚114a以及外引脚114b，而导线160则分别连接于芯片120的导电图案126与内引脚114a之间，以电性连接芯片120与内引脚114a。此外，在本实施例中，芯片座112用以承载芯片120的上表面与各内引脚114a用以与芯片120电性连接的上表面之间可具有高度差。在本实施例中，导线架110的芯片座112为沉置设计，也就是芯片座112的上表面低于各内引脚114a的上表面。当然，任何所属技术领域中具有通常知识者应了解，本实施例的附图仅用以举例说明，本发明并不以此为限。
请接续参照图1F，形成封装胶体140，使其包覆芯片120、至少部份引脚114、散热柱130、导线160以及芯片座112。在本实施例中，封装胶体140可例如包覆内引脚114a而暴露外引脚114b。接着，再如图1G所示，利用例如激光钻孔（laser drill）工艺，于封装胶体140形成至少一开口142，以暴露至少部份散热柱130。在本实施例中，封装胶体140至少暴露各散热柱130的顶面。如此，本实施例的芯片封装结构100即大致制作完成。
依上述制作方法所制作出的芯片封装结构100如图1G所示包括导线架110、芯片120、至少一散热柱130以及封装胶体140。导线架110包括芯片座112以及多个环绕芯片座112的引脚114。芯片座112具有至少一贯孔112a，对应散热柱130设置。芯片120设置于芯片座112上并电性连接至引脚114。在本实施例中，芯片120包括相对的主动表面122以及背面124，且散热柱130设置于背面124并穿过芯片座112的贯孔112a，使芯片120得以其背面124设置于芯片座112上。封装胶体140包覆芯片120、至少部份引脚114以及芯片座112并包括至少一开口142，以暴露散热柱130。
如此配置，本实施例的芯片封装结构100即可通过设置于芯片120的背面124的散热柱130而直接将芯片120所产生的热能散逸至外界，因而可提升散热效能，也可省去设置散热膏或散热片等额外的散热元件的成本。当然，在本发明的其他实施例中，芯片封装结构100也可依产品的需求而选择性地设置散热片于封装胶体140相对于开口142的上表面上，以进一步提升芯片封装结构100的散热效率。或者，也可将芯片座112的下表面部分外露于封装胶体140。在本实施例中，开口142可如图4所示的暴露至少部分芯片座112。如此，则可无需另外设置散热片，而可直接将暴露于外的芯片座112当成散热片使用。此外，由于散热柱130设置于芯片120的背面124，且不与芯片120的其他线路电性连接，因此，即使散热柱130因长期暴露于封装胶体140外而产生氧化的情形，也不会影响芯片120本身的电性效能。
图2是图1G的芯片设置于芯片座上的仰视示意图。在此须说明的是，图2省略了图1G中的封装胶体140，以更清楚呈现芯片120与芯片座112间的设置关系。请同时参照图1G以及图2，在本实施例中，散热柱130的数量为多个，芯片座112的贯孔112a的数量则可如图2所示例如为一个，而散热柱130皆位于贯孔112a内。封装胶体140的开口142的数量可对应于散热柱130的数量而为多个，且开口142分别对应散热柱130设置，以分别暴露对应的散热柱130。
图3是依照本发明的一实施例的一种芯片封装结构的剖面示意图。在此必须说明的是，本实施例的芯片封装结构100a与图1G所示的芯片封装结构100大致相似，因此，本实施例沿用前述实施例的元件标号与部分内容，其中采用相同的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例，本实施例不再重复赘述。以下将针对本实施例的芯片封装结构100a与图1G所示的芯片封装结构100的不同之处加以说明。在本实施例中，芯片封装结构100a的散热柱130的数量为多个，且芯片座112的贯孔112a以及封装胶体140的开口142的数量也为多个，其中，贯孔112a以及开口142分别对应散热柱130设置。也就是说，各散热柱130如图3所示分别位于对应的各个贯孔112a内，而封装胶体140的各开口142则分别暴露对应的散热柱130，使芯片封装结构100a得以通过暴露的散热柱130将芯片120所产生的热能散逸至外界。
图4是依照本发明的另一实施例的一种芯片封装结构的剖面示意图。在此必须说明的是，本实施例的芯片封装结构100b与图1G所示的芯片封装结构100大致相似，因此，本实施例沿用前述实施例的元件标号与部分内容，其中采用相同的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例，本实施例不再重复赘述。以下将针对本实施例的芯片封装结构100b与图1G所示的芯片封装结构100的不同之处加以说明。
在本实施例中，芯片封装结构100b的散热柱130的数量为多个，芯片座112的贯孔112a的数量则可如图2以及图4所示为一个。散热柱130位于贯孔112a内。此外，本实施例的封装胶体140的开口142的数量可为一个，以如图4所示暴露出各个散热柱130的顶面，使芯片封装结构100b可通过暴露的散热柱130将芯片120所产生的热能散逸至外界。当然，任何所属技术领域中具有通常知识者应了解，上述的实施例仅为举例说明，本发明并不限制散热柱130、贯孔112a以及开口142的数量。于其他未绘示的实施例中，使用者也可依产品需求而自行排列组合上述实施例的特征，只要散热柱130可穿过贯孔112a而使芯片120承靠于芯片座112上，且封装胶体140可利用其开口142而暴露散热柱130即可。
综上所述，本发明的芯片封装结构将散热柱通过电镀的方式直接形成于芯片的背面，且散热柱穿过芯片座的贯孔，使芯片得以背面设置于导线架的芯片座上，且封装胶体更包括对应于散热柱的开口，以暴露散热柱。如此，本发明的芯片封装结构即可通过设置于芯片背面的散热柱将芯片所产生的热能直接散逸至外界，因而可提升芯片封装结构的散热效能，也可省去设置散热膏或散热片等额外的散热元件的成本。当然，本发明的芯片封装结构也可依产品的需求而选择性地设置散热片于封装胶体上，以进一步提升芯片封装结构的散热效率。此外，由于散热柱设置于芯片背面，且不与芯片的其他线路电性连接，因而可避免散热柱因长期暴露而氧化，进而影响芯片电性效能的问题。
虽然本发明已以实施例揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视后附的权利要求所界定者为准。

Claims (10)

1.一种芯片封装结构，其特征在于，包括：
导线架，包括芯片座以及多个引脚，该芯片座具有至少一贯孔，所述多个引脚环绕该芯片座设置；
芯片，设置于该芯片座上并电性连接至所述多个引脚，该芯片包括主动表面以及相对该主动表面的背面，该芯片以该背面设置于该芯片座上；
至少一散热柱，直接设置于该背面并穿过该贯孔；以及封装胶体，包覆该芯片、至少部份所述多个引脚以及该芯片座，该封装胶体包括至少一开口，以暴露该散热柱，其中该散热柱是以电镀工艺形成。
2.如权利要求1所述的芯片封装结构，其特征在于，该散热柱的数量为多个。
3.如权利要求2所述的芯片封装结构，其特征在于，多个该散热柱位于该贯孔内，且该开口暴露多个该散热柱。
4.如权利要求2所述的芯片封装结构，其特征在于，该开口的数量为多个，各个该开口分别暴露对应的各个该散热柱。
5.如权利要求2所述的芯片封装结构，其特征在于，该贯孔的数量为多个，各个该散热柱分别位于对应的各个该贯孔内。
6.如权利要求1所述的芯片封装结构，其特征在于，该开口至少暴露各该散热柱的顶面，其中该顶面不与该背面的接触。
7.如权利要求1所述的芯片封装结构，其特征在于，更包括多个导线，各个所述多个导线分别电性连接该芯片与对应的各个所述多个引脚。
8.如权利要求1所述的芯片封装结构，其特征在于，更包括散热片，设置于该封装胶体相对于该开口的上表面。
9.如权利要求1所述的芯片封装结构，其特征在于，该开口暴露至少部份该芯片座。
10.一种芯片封装结构的制造方法，其特征在于，包括：
提供晶圆，该晶圆包括具有导电图案的主动表面以及相对该主动表面的背面，其中该晶圆包括多个彼此连接且阵列排列的芯片；
设置具有多个开孔的图案化干膜层于该晶圆的该背面；
进行电镀工艺，以图案化干膜层为掩膜而分别于所述多个开孔内形成多个散热柱，且各个所述多个散热柱分别位于对应的各个所述多个开孔内；
移除该图案化干膜层；
切割该晶圆以使多个该芯片彼此分离，各该芯片具有所述多个散热柱的至少其中之一；
提供导线架，该导线架包括芯片座以及多个引脚，该芯片座具有至少一贯孔，所述引脚环绕该芯片座设置；
设置多个该芯片的其中之一于该芯片座上并电性连接该芯片至所述多个引脚，并以该芯片的散热柱穿过该贯孔；
提供封装胶体，以包覆该芯片、至少部份所述多个引脚以及该芯片座，该封装胶体包括至少一开口，并暴露该散热柱。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160071787A1 (en) * 2014-09-08 2016-03-10 Sheila F. Chopin Semiconductor device attached to an exposed pad
CN105590906B (zh) * 2016-01-11 2019-02-01 江苏科技大学 一种用于扇出式圆片级封装的散热构件及制造方法
US10586751B2 (en) * 2017-08-03 2020-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US11398417B2 (en) 2018-10-30 2022-07-26 Stmicroelectronics, Inc. Semiconductor package having die pad with cooling fins
CN109904125B (zh) * 2019-03-06 2021-02-19 西安航思半导体有限公司 耐高温qfn封装结构的制备方法
CN109904124B (zh) * 2019-03-06 2021-04-23 西安航思半导体有限公司 具有防短路功能的qfn封装结构
KR20210108583A (ko) 2020-02-26 2021-09-03 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US11239127B2 (en) 2020-06-19 2022-02-01 Infineon Technologies Ag Topside-cooled semiconductor package with molded standoff
TWI770880B (zh) * 2020-12-04 2022-07-11 立錡科技股份有限公司 晶片封裝方法以及晶片封裝單元
CN114721188B (zh) * 2022-03-29 2024-05-17 颀中科技（苏州）有限公司 覆晶封装结构的形成方法、覆晶封装结构及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273256A (ja) * 1994-04-01 1995-10-20 Nippon Steel Corp 半導体装置および該装置用ヒートスプレッダー
CN1503358A (zh) * 2002-11-25 2004-06-09 恩益禧电子股份有限公司 树脂密封型半导体器件及用于生产这种半导体器件的生产工艺
CN101877334A (zh) * 2009-04-28 2010-11-03 钰桥半导体股份有限公司 具散热增益的半导体装置
CN102176434A (zh) * 2010-12-24 2011-09-07 苏州达方电子有限公司 气密陶瓷层结构与制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05160289A (ja) * 1991-12-10 1993-06-25 Fujitsu Ltd 半導体チップの実装構造
US5506755A (en) * 1992-03-11 1996-04-09 Kabushiki Kaisha Toshiba Multi-layer substrate
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5604376A (en) * 1994-06-30 1997-02-18 Digital Equipment Corporation Paddleless molded plastic semiconductor chip package
JPH0955459A (ja) * 1995-06-06 1997-02-25 Seiko Epson Corp 半導体装置
US8330270B1 (en) * 1998-06-10 2012-12-11 Utac Hong Kong Limited Integrated circuit package having a plurality of spaced apart pad portions
US6696643B2 (en) * 2000-08-01 2004-02-24 Mitsubishi Denki Kabushiki Kaisha Electronic apparatus
JP3879452B2 (ja) * 2001-07-23 2007-02-14 松下電器産業株式会社 樹脂封止型半導体装置およびその製造方法
US6777788B1 (en) * 2002-09-10 2004-08-17 National Semiconductor Corporation Method and structure for applying thick solder layer onto die attach pad
DE10332009B4 (de) * 2003-07-14 2008-01-31 Infineon Technologies Ag Halbleiterbauelement mit elektromagnetischer Abschirmvorrichtung
KR100586699B1 (ko) * 2004-04-29 2006-06-08 삼성전자주식회사 반도체 칩 패키지와 그 제조 방법
JP2004228603A (ja) * 2004-05-06 2004-08-12 Seiko Epson Corp 半導体装置および半導体装置の製造方法
US7087986B1 (en) * 2004-06-18 2006-08-08 National Semiconductor Corporation Solder pad configuration for use in a micro-array integrated circuit package
TWI237364B (en) * 2004-12-14 2005-08-01 Advanced Semiconductor Eng Flip chip package with anti-floating mechanism
TWI265617B (en) * 2005-01-11 2006-11-01 Siliconware Precision Industries Co Ltd Lead-frame-based semiconductor package with lead frame and lead frame thereof
US20060170081A1 (en) * 2005-02-03 2006-08-03 Gerber Mark A Method and apparatus for packaging an electronic chip
KR101004842B1 (ko) * 2008-07-25 2010-12-28 삼성전기주식회사 전자 칩 모듈
JP5149854B2 (ja) * 2009-03-31 2013-02-20 ルネサスエレクトロニクス株式会社 半導体装置
US8547709B2 (en) * 2010-02-12 2013-10-01 Cyntec Co. Ltd. Electronic system with a composite substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07273256A (ja) * 1994-04-01 1995-10-20 Nippon Steel Corp 半導体装置および該装置用ヒートスプレッダー
CN1503358A (zh) * 2002-11-25 2004-06-09 恩益禧电子股份有限公司 树脂密封型半导体器件及用于生产这种半导体器件的生产工艺
CN101877334A (zh) * 2009-04-28 2010-11-03 钰桥半导体股份有限公司 具散热增益的半导体装置
CN102176434A (zh) * 2010-12-24 2011-09-07 苏州达方电子有限公司 气密陶瓷层结构与制造方法

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