CN104685569B - 关于存取存储器单元的分布式子块的设备及方法 - Google Patents

关于存取存储器单元的分布式子块的设备及方法 Download PDF

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Publication number
CN104685569B
CN104685569B CN201380049356.8A CN201380049356A CN104685569B CN 104685569 B CN104685569 B CN 104685569B CN 201380049356 A CN201380049356 A CN 201380049356A CN 104685569 B CN104685569 B CN 104685569B
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sub
block
blocks
memory cells
memory
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CN104685569A (zh
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丹沢彻
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Micron Technology Inc
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Micron Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
CN201380049356.8A 2012-08-21 2013-08-20 关于存取存储器单元的分布式子块的设备及方法 Active CN104685569B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/590,926 2012-08-21
US13/590,926 US8891305B2 (en) 2012-08-21 2012-08-21 Apparatuses and methods involving accessing distributed sub-blocks of memory cells
PCT/US2013/055767 WO2014031624A1 (en) 2012-08-21 2013-08-20 Apparatuses and methods involving accessing distributed sub-blocks of memory cells

Publications (2)

Publication Number Publication Date
CN104685569A CN104685569A (zh) 2015-06-03
CN104685569B true CN104685569B (zh) 2016-07-06

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US (5) US8891305B2 (cg-RX-API-DMAC7.html)
EP (2) EP2888740B1 (cg-RX-API-DMAC7.html)
JP (1) JP6321650B2 (cg-RX-API-DMAC7.html)
KR (1) KR102214272B1 (cg-RX-API-DMAC7.html)
CN (1) CN104685569B (cg-RX-API-DMAC7.html)
TW (1) TWI512756B (cg-RX-API-DMAC7.html)
WO (1) WO2014031624A1 (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9779791B2 (en) 2012-08-21 2017-10-03 Micron Technology, Inc. Apparatuses and methods involving accessing distributed sub-blocks of memory cells

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107689377A (zh) * 2016-08-06 2018-02-13 厦门海存艾匹科技有限公司 含有分离地址/数据转换器的三维一次电编程存储器
US9312005B2 (en) * 2013-09-10 2016-04-12 Micron Technology, Inc. Accessing memory cells in parallel in a cross-point array
CN112074816B (zh) 2018-03-16 2025-02-21 美光科技公司 Nand数据放置模式的集群奇偶校验
EP3766070B1 (en) 2018-03-16 2025-12-10 Micron Technology, Inc. Nand data placement schema
US11271002B2 (en) 2019-04-12 2022-03-08 Micron Technology, Inc. Methods used in forming a memory array comprising strings of memory cells
US12483804B2 (en) * 2023-12-08 2025-11-25 Varjo Technologies Oy Subsampling and wobulation in colour filter arrays having smallest repeating units with different sub-units
US20250193542A1 (en) * 2023-12-08 2025-06-12 Varjo Technologies Oy Selective reading in colour filter arrays having smallest repeating units with different sub-units

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367655A (en) * 1991-12-23 1994-11-22 Motorola, Inc. Memory and associated method including an operating mode for simultaneously selecting multiple rows of cells
CN1930635A (zh) * 2003-12-30 2007-03-14 桑迪士克股份有限公司 对多个区块进行适应性确定群组以成为多个多区块单元
US20070079056A1 (en) * 2005-09-30 2007-04-05 Tsutomu Nakamura Semiconductor memory and memory controller therefor
US20090303767A1 (en) * 2008-04-02 2009-12-10 Avidan Akerib System, method and apparatus for memory with embedded associative section for computations

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5204842A (en) * 1987-08-05 1993-04-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory with memory unit comprising a plurality of memory blocks
US6098145A (en) * 1998-02-18 2000-08-01 Winbond Electronics Corporation Pulsed Y-decoders for improving bitline precharging in memories
JP3707943B2 (ja) * 1998-12-24 2005-10-19 株式会社東芝 半導体記憶装置
JP4458584B2 (ja) * 1999-09-07 2010-04-28 株式会社ルネサステクノロジ 半導体記憶装置
US7177181B1 (en) 2001-03-21 2007-02-13 Sandisk 3D Llc Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
US6724665B2 (en) * 2001-08-31 2004-04-20 Matrix Semiconductor, Inc. Memory device and method for selectable sub-array activation
US6975536B2 (en) * 2002-01-31 2005-12-13 Saifun Semiconductors Ltd. Mass storage array and methods for operation thereof
US6879505B2 (en) 2003-03-31 2005-04-12 Matrix Semiconductor, Inc. Word line arrangement having multi-layer word line segments for three-dimensional memory array
US7286439B2 (en) 2004-12-30 2007-10-23 Sandisk 3D Llc Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders
US7889571B2 (en) * 2008-01-09 2011-02-15 Unity Semiconductor Corporation Buffering systems methods for accessing multiple layers of memory in integrated circuits
US7359279B2 (en) * 2005-03-31 2008-04-15 Sandisk 3D Llc Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
US7649788B2 (en) 2006-01-30 2010-01-19 Unity Semiconductor Corporation Buffering systems for accessing multiple layers of memory in integrated circuits
US7505328B1 (en) * 2006-08-14 2009-03-17 Spansion Llc Method and architecture for fast flash memory programming
US8139432B2 (en) * 2006-12-27 2012-03-20 Samsung Electronics Co., Ltd. Variable resistance memory device and system thereof
CN100552645C (zh) * 2007-05-28 2009-10-21 创见资讯股份有限公司 非易失性存储器装置与数据的存取电路及其方法
WO2009105362A1 (en) * 2008-02-19 2009-08-27 Rambus Inc. Multi-bank flash memory architecture with assignable resources
KR20090095003A (ko) * 2008-03-04 2009-09-09 삼성전자주식회사 적층형 반도체 메모리 장치
JP4806046B2 (ja) * 2009-03-16 2011-11-02 株式会社東芝 半導体記憶装置
US7940554B2 (en) 2009-04-24 2011-05-10 Sandisk 3D Llc Reduced complexity array line drivers for 3D matrix arrays
JP2011165298A (ja) 2010-01-18 2011-08-25 Elpida Memory Inc 半導体記憶装置及びこれを備えた情報処理システム
WO2012050935A2 (en) * 2010-09-28 2012-04-19 Fusion-Io, Inc. Apparatus, system, and method for data transformations within a data storage device
US8273610B2 (en) * 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US8645616B2 (en) * 2011-02-03 2014-02-04 Micron Technology, Inc. Protecting groups of memory cells in a memory device
KR101772951B1 (ko) * 2011-03-10 2017-09-13 삼성전자주식회사 불 휘발성 메모리 장치 및 그것의 읽기 방법
US8760957B2 (en) * 2012-03-27 2014-06-24 SanDisk Technologies, Inc. Non-volatile memory and method having a memory array with a high-speed, short bit-line portion
US8891305B2 (en) 2012-08-21 2014-11-18 Micron Technology, Inc. Apparatuses and methods involving accessing distributed sub-blocks of memory cells

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5367655A (en) * 1991-12-23 1994-11-22 Motorola, Inc. Memory and associated method including an operating mode for simultaneously selecting multiple rows of cells
CN1930635A (zh) * 2003-12-30 2007-03-14 桑迪士克股份有限公司 对多个区块进行适应性确定群组以成为多个多区块单元
US20070079056A1 (en) * 2005-09-30 2007-04-05 Tsutomu Nakamura Semiconductor memory and memory controller therefor
US20090303767A1 (en) * 2008-04-02 2009-12-10 Avidan Akerib System, method and apparatus for memory with embedded associative section for computations

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9779791B2 (en) 2012-08-21 2017-10-03 Micron Technology, Inc. Apparatuses and methods involving accessing distributed sub-blocks of memory cells
US10170169B2 (en) 2012-08-21 2019-01-01 Micron Technology, Inc. Apparatuses and methods involving accessing distributed sub-blocks of memory cells
US10734049B2 (en) 2012-08-21 2020-08-04 Micron Technology, Inc. Apparatuses and methods involving accessing distributed sub-blocks of memory cells
US11282556B2 (en) 2012-08-21 2022-03-22 Micron Technology, Inc. Apparatuses and methods involving accessing distributed sub-blocks of memory cells

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Publication number Publication date
US20180122443A1 (en) 2018-05-03
EP2888740A1 (en) 2015-07-01
US10734049B2 (en) 2020-08-04
US20210020214A1 (en) 2021-01-21
TW201419302A (zh) 2014-05-16
US20140056070A1 (en) 2014-02-27
EP3686890A1 (en) 2020-07-29
US11282556B2 (en) 2022-03-22
US20150063022A1 (en) 2015-03-05
EP2888740A4 (en) 2016-04-13
EP2888740B1 (en) 2020-03-11
US10170169B2 (en) 2019-01-01
US20190279695A1 (en) 2019-09-12
KR20150047568A (ko) 2015-05-04
JP2015529929A (ja) 2015-10-08
US8891305B2 (en) 2014-11-18
KR102214272B1 (ko) 2021-02-10
WO2014031624A1 (en) 2014-02-27
TWI512756B (zh) 2015-12-11
JP6321650B2 (ja) 2018-05-09
US9779791B2 (en) 2017-10-03
CN104685569A (zh) 2015-06-03

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