CN104662762A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN104662762A
CN104662762A CN201380048700.1A CN201380048700A CN104662762A CN 104662762 A CN104662762 A CN 104662762A CN 201380048700 A CN201380048700 A CN 201380048700A CN 104662762 A CN104662762 A CN 104662762A
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power supply
terminal
voltage
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mos transistor
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CN104662762B (zh
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北岛裕一郎
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Ablic Inc
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Seiko Instruments Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H02H11/002—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0034—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using reverse polarity correcting or protecting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Direct Current Feeding And Distribution (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

为了在电源被反向连接于半导体装置的反接时能够有效地切断电流路径，采用如下的结构。NMOS晶体管(14)的栅极与电源端子(11)连接，源极和背栅连接于内部接地节点(17)，漏极与接地端子(12)连接。NMOS晶体管(15)的栅极与接地端子(12)连接，源极和背栅连接于内部接地节点(17)，漏极与电源端子(11)连接。内部电路(13)的电源端子与电源端子(11)连接，内部电路(13)的接地端子与内部接地节点(17)连接。

Description

半导体装置
技术领域
本发明涉及半导体装置。特别是涉及在直流电源被反向连接的情况下不会流过电流的半导体装置。
背景技术
对现有的电子设备进行说明，现有的电子设备针对电池等直流电源被反向连接的所谓的反接，具有保护内部电路的功能。图5是示出专利文献1所记载的电子设备的电路图。对电路的工作进行说明，该电路在与该电子设备通常地连接电源的情况相反地连接电源的情况下，具有保护功能。
<电源被通常地连接于电子设备的通常连接时>
在电源1被通常地连接于电子设备3的通常连接时，由电阻R1和R2对电源端子TV与接地线LG之间的电压进行分压。分压电压被施加到NMOS晶体管MT1的栅极。在进行了通常连接的情况下，由于NMOS晶体管MT1导通，所以因流过NMOS晶体管MT1的沟道的电流，接地端子TG与接地线LG导通，从而建立对电子设备3的供电。
<电源被反向连接于电子设备的反接时>
在电源1被反向连接于电子设备3的反接时，施加到NMOS晶体管MT1的栅极的电压比施加到源极的电压低，所以NMOS晶体管MT1截止、且寄生二极管也被反向偏置，因此接地端子TG与接地线LG不导通。因而，不会流过反向电流，所以针对反接，电子设备3得到保护。
现有技术文献
专利文献
专利文献1：日本特开2002－095159号公报
发明内容
发明所要解决的课题
当在半导体装置中应用了上述现有技术的情况下，由于在反接时NMOS晶体管MT1是截止的，所以内部电路的接地线LG与较低侧的电源电压大致相等。然而，在该情况下，具有如下危险性：由于接地线LG是以高阻抗连接的，所以有可能经由内部电路中存在的寄生元件所形成的电流路径而施加电压，进而导致内部电路进行意想不到的工作。
本发明正是鉴于上述危险性而完成的，其课题在于提供一种半导体装置，该半导体装置具有在直流电源被反向连接于半导体装置的反接时能够有效地切断电流路径的功能。
用于解决课题的手段
本发明为了解决上述课题，提供一种半导体装置，其特征在于，具备：第一个第一导电型MOS晶体管，其栅极与第一电源端子连接，源极和背栅连接于内部第二电源节点，漏极与第二电源端子连接；第二个第一导电型MOS晶体管，其栅极与所述第二电源端子连接，源极和背栅连接于所述内部第二电源节点，漏极与所述第一电源端子连接；以及内部电路，其将所述第一电源端子与所述内部第二电源节点之间的电压作为工作用电源。
发明效果
根据本发明，由于在反接时，内部电路的内部节点和保护环的扩散区不会成为悬空(floating)状态，所以能够有效地切断内部电路中存在的寄生元件所形成的电流路径，从而使内部电路稳定地停止工作。
附图说明
图1是示出半导体装置的电路图。
图2是示出半导体装置的电路图。
图3是示出半导体装置的剖视图。
图4是示出半导体装置的电路图。
图5是示出现有的电子设备的电路图。
具体实施方式
下面，参照附图对本发明的实施方式进行说明。
如图1所示，半导体装置10具备电源端子(第一电源端子)11、接地端子(第二电源端子)12、内部电路13、NMOS晶体管14、NMOS晶体管15、内部电源节点(内部第一电源节点)16和内部接地节点(内部第二电源节点)17。另外，电源20的电源端子21与半导体装置10的电源端子11连接，电源20的接地端子22与半导体装置10的接地端子12连接。
NMOS晶体管14的栅极与电源端子11连接，NMOS晶体管14的源极和用于提供衬底电位的背栅连接于内部接地节点17，NMOS晶体管14的漏极与接地端子12连接。NMOS晶体管15的栅极与接地端子12连接，NMOS晶体管15的源极和用于提供衬底电位的背栅连接于内部接地节点17，NMOS晶体管15的漏极与电源端子11连接。因此，在NMOS晶体管14和NMOS晶体管15中，分别在源极与漏极之间配置有寄生二极管。
内部电路13的电源端子与电源端子11连接，内部电路13的接地端子与内部接地节点17连接。即，内部电路13将电源端子11与内部接地节点17之间的电压作为工作用电源。在此，电源端子11与内部电源节点16连接，接地端子12经由NMOS晶体管14连接于内部接地节点17。对电路的工作分别进行说明，该电路在与电源被通常地连接于该电子设备的情况相反地连接电源的情况下，具有保护功能。
<电源被通常地连接于半导体装置的通常连接时>
接下来，在图1中，在电源20被通常地连接于半导体装置10的通常连接时，由于内部电源节点16与电源端子11连接，所以内部电源节点16的电压成为从电源20提供的电源电压。而且，由于NMOS晶体管14的栅极电压是从电源20提供的电源电压，所以NMOS晶体管14导通。于是，内部接地节点17的电压与接地端子12的电压大致相同，且成为从电源20提供的接地电压。从而，建立对内部电路13的供电。根据这些电源电压和接地电压，内部电路13进行所期望的工作。此外，NMOS晶体管14的驱动能力是根据内部电路13的消耗电流来适当地进行电路设计的。
而且，由于NMOS晶体管15的栅极电压是从电源20提供的接地电压，所以NMOS晶体管15截止。
此时，需要将NMOS晶体管14的栅极绝缘膜设为具有与从电源20提供的电源电压相比足够高的破坏电压的膜厚。
<电源被反向连接于半导体装置的反接时>
在电源20被反向连接于半导体装置10的反接时，如图2所示，电源20的电源端子21与半导体装置10的接地端子12连接，电源20的接地端子22与半导体装置10的电源端子11连接。
此时，NMOS晶体管14的栅极电压是从电源20提供的接地电压，所以NMOS晶体管14截止。而且，在接地端子12与内部接地节点17之间，由于NMOS晶体管14的寄生二极管被反向偏置，所以不会流过电流。从而，接地端子12与内部接地节点17不导通。因而，在反接时，不存在从接地端子12向内部电路13的电流路径，所以内部电路13得到保护。
而且，由于NMOS晶体管15的栅极电压是从电源20提供的电源电压，所以NMOS晶体管15导通。据此，经由低阻抗的NMOS晶体管15，内部接地节点17的电压与电源端子11以及内部电源节点16的电压大致相同，成为从电源20提供的接地电压。即，内部电路13的电源端子和接地端子的电压均成为从电源20提供的接地电压。从而，在反接时，内部电路13的内部节点和保护环的扩散区不会成为悬空状态，所以内部电路13中存在的寄生元件所形成的电流路径被彻底地切断，从而内部电路13能够彻底地停止工作。
此时，将NMOS晶体管15的栅极绝缘膜设为具有与从电源20提供的电源电压相比足够高的破坏电压的膜厚。
NMOS晶体管14和NMOS晶体管15不仅针对电源的反接，使内部电路得到保护，并且还作为针对内部电路13的ESD保护元件发挥功能。下面，对将浪涌电压施加到电源端子的情况下的、针对ESD的保护工作进行说明。
<以接地端子12为基准、将正的浪涌电压施加到电源端子11时>
在将正的浪涌电压施加到电源端子11时，浪涌电流从电源端子11流向接地端子12。此时，NMOS晶体管15的寄生二极管因击穿动作而反向地流过浪涌电流，NMOS晶体管14的寄生二极管正向地流过浪涌电流，由此不会使浪涌电流流向内部电路13。从而，针对浪涌电流，内部电路13得到保护。
此时，与电源端子11连接的NMOS晶体管14的栅极被施加浪涌电压。因此，以保护NMOS晶体管14的栅极为目的，如下地设定NMOS晶体管15。将NMOS晶体管15的寄生二极管的击穿动作的开始电压设为NMOS晶体管14的栅极绝缘膜的破坏耐压以下，且NMOS晶体管14的栅极绝缘膜以在被破坏之前使浪涌电流流过的方式来设定大小或杂质浓度等。而且，NMOS晶体管15的寄生二极管的击穿动作的开始电压必须为图1所示的通常连接时从电源20提供的电压以上。
<以接地端子12为基准、将负的浪涌电压施加到电源端子11时>
在将负的浪涌电压施加到电源端子11时，浪涌电流从接地端子12流向电源端子11。此时，NMOS晶体管14的寄生二极管因击穿动作而反向地流过浪涌电流，NMOS晶体管15的寄生二极管正向地流过浪涌电流，由此不会使浪涌电流流向内部电路13。从而，针对浪涌电流，内部电路13得到保护。
此时，NMOS晶体管15的栅极被施加浪涌电压。因此，以保护NMOS晶体管15的栅极为目的，如下地设定NMOS晶体管14。对于NMOS晶体管14的寄生二极管的击穿动作的开始动作，设为NMOS晶体管15的栅极绝缘膜的破坏耐压以下，且NMOS晶体管15的栅极绝缘膜以在被破坏之前使浪涌电流流过的方式来设定大小或杂质浓度等。而且，NMOS晶体管14的寄生二极管的击穿动作的开始电压必须为图2所示的反接时从电源20提供的电压以上。
试着考虑将具有如上所述的电路结构的半导体装置作为IC密封到树脂的封装中的情况。此时，如图3的(A)所示，半导体装置10具备在表面配置有电路的P型半导体衬底31、由绝缘膏或绝缘膜构成的绝缘粘接材料32、裸片连接盘33、引线34、导线35和密封树脂36。
通过光刻法等公知的半导体技术，在P型半导体衬底31上制作了上述电路。绝缘粘接材料32将P型半导体衬底31和裸片连接盘33以电绝缘的状态粘接起来。裸片连接盘33的反面露出到半导体装置10的外部，且裸片连接盘33将P型半导体衬底31所发出的热量散出到半导体装置10的外部。而且，裸片连接盘33支承P型半导体衬底31。导线35对P型半导体衬底31上制作的上述电路的外部连接用端子(例如电源端子11)和引线34进行电连接。引线34被用于半导体装置10与设置有电路的安装基板的电连接。密封树脂36对P型半导体衬底31、绝缘粘接材料32、裸片连接盘33、引线34和导线35进行密封。
在图1的半导体装置10的电路结构的情况下，NMOS晶体管14的背栅的电压等于内部接地节点17的电压。因此，如图3的(B)所示，P型半导体衬底31成为内部接地节点17的电压。在此，由于使用了绝缘粘接材料32，所以P型半导体衬底31和裸片连接盘33没有被电连接。于是，即使裸片连接盘33受到外部的电影响，P型半导体衬底31的电压也不会受到影响而依然是内部接地节点17的电压。
此外，如图4所示，也可以使用PMOS晶体管而不是NMOS晶体管。此时，PMOS晶体管24的栅极与接地端子(第一电源端子)12连接，PMOS晶体管24的源极和背栅连接于内部电源节点16(内部第二电源节点)，PMOS晶体管24的漏极与电源端子(第二电源端子)11连接。PMOS晶体管25的栅极与电源端子11连接，PMOS晶体管25的源极和背栅连接于内部电源节点16，PMOS晶体管25的漏极与接地端子12连接。内部电路13的电源端子与内部电源节点16连接，内部电路13的接地端子与连接于接地端子12的内部接地节点(内部第一电源节点)17连接。即，内部电路13将内部电源节点16与接地端子12之间的电压作为工作用电源。在此，电源端子11经由PMOS晶体管24连接于内部电源节点16，接地端子12与内部接地节点17连接。
标号说明
10：半导体装置
11：电源端子
12：接地端子
13：内部电路
14、15：NMOS晶体管
16：内部电源节点
17：内部接地节点
20：电源
21：电源端子
22：接地端子

Claims (8)

1.一种半导体装置，其特征在于，具备：
第一个第一导电型MOS晶体管，其具有与第一电源端子连接的栅极、与内部第二电源节点连接的源极和背栅、以及与第二电源端子连接的漏极；
第二个第一导电型MOS晶体管，其具有与所述第二电源端子连接的栅极、与所述内部第二电源节点连接的源极和背栅、以及与所述第一电源端子连接的漏极；以及
内部电路，其基于所述第一电源端子与所述内部第二电源节点之间的电压进行工作。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第一个第一导电型MOS晶体管和所述第二个第一导电型MOS晶体管、以及所述内部电路是在同一半导体衬底上制作的，
所述半导体衬底通过绝缘粘接材料以电绝缘状态被粘接到裸片连接盘，并被密封到树脂的封装中。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述第一电源端子是电源端子，
所述第二电源端子是接地端子，
所述内部第二电源节点是内部接地节点，
所述第一个第一导电型MOS晶体管和所述第二个第一导电型MOS晶体管是NMOS晶体管。
4.根据权利要求1或2所述的半导体装置，其特征在于，
所述第一电源端子是接地端子，
所述第二电源端子是电源端子，
所述内部第二电源节点是内部电源节点，
所述第一个第一导电型MOS晶体管和所述第二个第一导电型MOS晶体管是PMOS晶体管。
5.根据权利要求1至4中任意一项所述的半导体装置，其特征在于，
所述第一个第一导电型MOS晶体管的栅极绝缘膜具有从电源提供的电压以上的破坏电压。
6.根据权利要求1至4中任意一项所述的半导体装置，其特征在于，
所述第二个第一导电型MOS晶体管的栅极绝缘膜具有从电源提供的电压以上的破坏电压。
7.根据权利要求1至6中任意一项所述的半导体装置，其特征在于，
在所述第一个第一导电型MOS晶体管中，当漏极被施加ESD浪涌时，寄生二极管的击穿动作的开始电压是从电源提供的电压以上、且所述第二个第一导电型MOS晶体管的栅极绝缘膜的破坏电压以下的电压，能够使ESD浪涌电流流过。
8.根据权利要求1至6中任意一项所述的半导体装置，其特征在于，
在所述第二个第一导电型MOS晶体管中，当漏极被施加ESD浪涌时，寄生二极管的击穿动作的开始电压是从电源提供的电压以上、且所述第一个第一导电型MOS晶体管的栅极绝缘膜的破坏电压以下的电压，能够使ESD浪涌电流流过。
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