CN104635419B - Preparation method, the mask plate of a kind of array substrate and its display panel - Google Patents
Preparation method, the mask plate of a kind of array substrate and its display panel Download PDFInfo
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- CN104635419B CN104635419B CN201510106454.1A CN201510106454A CN104635419B CN 104635419 B CN104635419 B CN 104635419B CN 201510106454 A CN201510106454 A CN 201510106454A CN 104635419 B CN104635419 B CN 104635419B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/54—Absorbers, e.g. of opaque materials
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/60—Substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The present invention provides preparation method, the mask plate of a kind of array substrate and its display panel, the mask plate includes substrate, the substrate includes non-transparent region, partially transparent area and transmission region, non-transparent material layer is provided on the non-transparent region, partial light permeability material layer is provided in the partially transparent area, the transmission region is not provided with light screening material, and the transmission region is arranged in the partially transparent area or the non-transparent region is arranged in the partially transparent area.Mask plate provided by the invention can be realized gate mask plate and via hole mask plate shares, to reduce the usage quantity of mask plate, reduce product development and production cost.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate and its preparation method of display panel, cover
Diaphragm plate.
Background technique
In TFT-LCD manufacturing, the manufacturing process of array substrate needs to carry out 4-7 exposure technology, it is therefore desirable to 4-7
Block mask plate (Mask), for example, the array substrate of common twisted-nematic (Twisted Nematic, TN) mode needs grid
Mask plate (Gate Mask), active layer mask plate (Active Mask), source-drain electrode mask plate (S/D Mask), via hole mask plate
(Via Mask), pixel electrode mask plate (ITO Mask) totally five pieces of mask plates.Every piece of mask plate is worth ten thousand people of 100-200
Coin, therefore only one product just needs to spend substantial contribution on purchase mask plate, improves the cost of product development and production.
Summary of the invention
To solve the above problems, the present invention provides preparation method, the mask plate of a kind of array substrate and its display panel, use
It is excessively high in the production cost for solving the problems, such as display panel caused by mask plate in the prior art.
To solve the above problems, the present invention provides a kind of mask plate, including substrate, the substrate include non-transparent region,
Partially transparent area and transmission region, are provided with non-transparent material layer on the non-transparent region, in the partially transparent area
It is provided with partial light permeability material layer, the transmission region is not provided with light screening material, and the transmission region setting is saturating in the part
In the light region or non-transparent region is arranged in the partially transparent area.
Optionally, when the transmission region is arranged in the partially transparent area, the transmission region and part are thoroughly
Light region is used to form grid line, grid and public electrode wire, and the transmission region is also used to be formed the first via hole and the second via hole；
Or
When the non-transparent region is arranged in the partially transparent area, the non-transparent region and partial light permeability area
Domain is used to form grid line, grid and public electrode wire, and the non-transparent region is also used to be formed the first via hole and the second via hole.
Optionally, the constituent material of the non-transparent material layer includes metal material, the structure of the partial light permeability material layer
It include metal oxide or resin at material.
Optionally, the metal material includes crome metal, and the metal oxide includes chromium oxide.
The present invention also provides a kind of preparation methods of array substrate, comprising:
Grid metal film is formed on substrate；
Grid line is formed by patterning processes using mask plate and grid, the mask plate include any of the above-described mask plate；
Sequentially form gate insulation layer, active layer film and drain metallic film；
Active layer, source electrode and drain electrode are formed by patterning processes；
Passivation layer is formed, the drain region is corresponded in the passivation layer by patterning processes using the mask plate and is formed
First via hole,
Form transparent conductive film；
Pixel electrode is formed by patterning processes, the pixel electrode is connected by first via hole and the drain electrode.
Optionally, while the use mask plate forms grid line and grid by patterning processes, public electrode wire is formed；
It is described that the first mistake of the drain region formation is corresponded in the passivation layer by patterning processes using the mask plate
While hole, the public electrode wire region is corresponded in the gate insulation layer and passivation layer and forms the second via hole；
While the formation pixel electrode by patterning processes, public electrode is formed, the public electrode passes through described
Second via hole is connect with the public electrode wire.
Optionally, while the use mask plate forms grid line and grid by patterning processes, public electrode wire is formed
The step of include:
Negative photoresist is applied in the grid metal film, negative photoresist is exposed using the mask plate aobvious
To be formed, region is fully retained in negative photoresist to shadow, negative photoresist part retains region and negative photoresist completely removes area
Domain, the negative photoresist, which is fully retained region and negative photoresist part and retains region and correspond to, forms grid line, grid and public affairs
The graphics field of common-battery polar curve, the negative photoresist completely remove region corresponding to other areas except the graphics field
Domain；
The grid metal film is performed etching to form grid line, grid and public electrode wire；
Remove remaining negative photoresist；
It is described that the first mistake of the drain region formation is corresponded in the passivation layer by patterning processes using the mask plate
While hole, corresponding to the step of public electrode wire region forms the second via hole in the gate insulation layer and passivation layer includes:
Apply positive photoresist on the passivation layer, use the mask plate to positive photoresist be exposed development with
Region is fully retained in formation positive photoresist, positive photoresist part retains region and positive photoresist completely removes region, institute
It states positive photoresist removal region and corresponds to the graphics field for forming the first via hole and the second via hole, the positive photoresist is complete
Retain region and positive photoresist part and retains other regions that region corresponds to except the graphics field；
The passivation layer and gate insulation layer are performed etching to form the first via hole and the second via hole；
Remove remaining positive photoresist.
Optionally, while the use mask plate forms grid line and grid by patterning processes, public electrode wire is formed
The step of include:
Positive photoresist is applied in the grid metal film, positive photoresist is exposed using the mask plate aobvious
To be formed, region is fully retained in positive photoresist to shadow, positive photoresist part retains region and positive photoresist completely removes area
Domain, the positive photoresist, which is fully retained region and positive photoresist part and retains region and correspond to, forms grid line, grid and public affairs
The graphics field of common-battery polar curve, positive photoresist removal region correspond to other regions except the graphics field；
The grid metal film is performed etching to form grid line, grid and public electrode wire；
Remove remaining positive photoresist；
It is described that the first mistake of the drain region formation is corresponded in the passivation layer by patterning processes using the mask plate
While hole, corresponding to the step of public electrode wire region forms the second via hole in the gate insulation layer and passivation layer includes:
Apply negative photoresist on the passivation layer, use the mask plate to negative photoresist be exposed development with
Region is fully retained in formation negative photoresist, negative photoresist part retains region and negative photoresist completely removes region, institute
It states negative photoresist removal region and corresponds to the graphics field for forming the first via hole and the second via hole, the negative photoresist is complete
Retain region and negative photoresist part and retains other regions that region corresponds to except the graphics field；
The passivation layer and gate insulation layer are performed etching to form the first via hole and the second via hole；
Remove remaining negative photoresist.
The present invention also provides a kind of preparation method of display panel, the preparation method including any of the above-described array substrate.
The present invention have it is following the utility model has the advantages that
In array substrate provided by the invention and its preparation method of display panel, mask plate, the mask plate includes base
Plate, the substrate include non-transparent region, partially transparent area and transmission region, are provided on the non-transparent region non-transparent
Material layer is provided with partial light permeability material layer in the partially transparent area, and the transmission region is not provided with light screening material, described
Transmission region is arranged in the partially transparent area or the non-transparent region is arranged in the partially transparent area.
Mask plate provided by the invention can be realized gate mask plate and via hole mask plate shares, to reduce the use number of mask plate
Amount, reduces product development and production cost.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram for mask plate that the embodiment of the present invention one provides；
Fig. 2 is a kind of structural schematic diagram of mask plate provided by Embodiment 2 of the present invention；
Fig. 3 is a kind of flow chart of the preparation method for array substrate that the embodiment of the present invention three provides；
Fig. 4 a~Fig. 4 c is the schematic diagram that embodiment three forms grid and public electrode wire；
Fig. 5 a~Fig. 5 c is the schematic diagram that embodiment three forms via hole；
Fig. 6 is a kind of schematic diagram for exposure technology that the embodiment of the present invention four provides；
Fig. 7 is the schematic diagram for another exposure technology that the embodiment of the present invention four provides.
Specific embodiment
To make those skilled in the art more fully understand technical solution of the present invention, the present invention is mentioned with reference to the accompanying drawing
The array substrate and its preparation method of display panel, mask plate of confession are described in detail.
Embodiment one
Fig. 1 is a kind of structural schematic diagram for mask plate that the embodiment of the present invention one provides.As shown in Figure 1, the mask plate
101 include substrate, and the substrate includes non-transparent region 102, partially transparent area 103 and transmission region 104.It is described non-transparent
It is provided with non-transparent material layer on region 102, partial light permeability material layer is provided in the partially transparent area 103, it is described
Light region 104 is not provided with light screening material, and the transmission region 104 is arranged in the partially transparent area 103.In patterning processes
In the process, the transmission region 104 and partially transparent area 103 are used to form grid line, grid and public electrode wire, and described
Transmission region 104 is also used to be formed the first via hole and the second via hole, so as to realize that gate mask plate and via hole mask plate are total
With, reach reduce mask plate usage quantity, reduce product development and production cost purpose.
In the present embodiment, the constituent material of the non-transparent material layer includes metal material, the partial light permeability material layer
Constituent material include metal oxide or resin.Preferably, the metal material includes crome metal, the metal oxide
Including chromium oxide.
In mask plate provided in this embodiment, the mask plate includes substrate, and the substrate includes non-transparent region, part
Transmission region and transmission region are provided with non-transparent material layer on the non-transparent region, are arranged in the partially transparent area
There is partial light permeability material layer, the transmission region is not provided with light screening material, and the transmission region is arranged in the partial light permeability area
In the domain or non-transparent region is arranged in the partially transparent area.Technical solution provided in this embodiment can be real
Existing gate mask plate and via hole mask plate share, to reduce the usage quantity of mask plate, reduce product development and production
Cost.
Embodiment two
Fig. 2 is a kind of structural schematic diagram of mask plate provided by Embodiment 2 of the present invention.As shown in Fig. 2, the mask plate
101 include substrate, and the substrate includes non-transparent region 102, partially transparent area 103 and transmission region 104.It is described non-transparent
It is provided with non-transparent material layer on region 102, partial light permeability material layer is provided in the partially transparent area 103, it is described
Light region 104 is not provided with light screening material, and the non-transparent region 102 is arranged in the partially transparent area 103.In composition work
During skill, the non-transparent region 102 and partially transparent area 103 are used to form grid line, grid and public electrode wire, and
The non-transparent region 102 is also used to be formed the first via hole and the second via hole, so as to realize that gate mask plate and via hole are covered
Diaphragm plate shares, and reaches the usage quantity for reducing mask plate, reduces the purpose of product development and production cost.
In the present embodiment, the constituent material of the non-transparent material layer includes metal material, the partial light permeability material layer
Constituent material include metal oxide or resin.Preferably, the metal material includes crome metal, the metal oxide
Including chromium oxide.
In mask plate provided in this embodiment, the mask plate includes substrate, and the substrate includes non-transparent region, part
Transmission region and transmission region are provided with non-transparent material layer on the non-transparent region, are arranged in the partially transparent area
There is partial light permeability material layer, the transmission region is not provided with light screening material, and the transmission region is arranged in the partial light permeability area
In the domain or non-transparent region is arranged in the partially transparent area.Technical solution provided in this embodiment can be real
Existing gate mask plate and via hole mask plate share, to reduce the usage quantity of mask plate, reduce product development and production
Cost.
Embodiment three
The present embodiment carries out the preparation process of array substrate detailed further below.It should be noted that in the present embodiment
The array substrate is TN mode, but the array substrate of other modes, for example, the array substrate of ADS mode and VA mode
Preparation method also belong to protection scope of the present invention.
Fig. 3 is a kind of flow chart of the preparation method for array substrate that the embodiment of the present invention three provides.As shown in figure 3, institute
Stating preparation method includes:
Step 3001 forms grid metal film on substrate.
Step 3002 forms grid line and grid by patterning processes using mask plate.
In the present embodiment, the mask plate that the mask plate uses above-described embodiment one to provide, particular content can refer to above-mentioned
Description in embodiment one, details are not described herein again.
Fig. 4 a~Fig. 4 c is the schematic diagram that embodiment three forms grid and public electrode wire.As shown in Fig. 4 a~Fig. 4 c,
Grid metal film 105 is formed on substrate, negative photoresist 106 is applied in the grid metal film 105, using the mask plate
101 pairs of negative photoresists 106 be exposed be developed to negative photoresist be fully retained region, negative photoresist part retain
Region and negative photoresist completely remove region, and region and negative photoresist part reserved area is fully retained in the negative photoresist
Domain corresponds to the graphics field for forming grid line, grid 108 and public electrode wire 107, and negative photoresist removal region is corresponding
Other regions except the graphics field perform etching the grid metal film 105 to form grid line, 108 and of grid
Public electrode wire 107 is finally peeled away remaining negative photoresist 106.Optionally, the substrate is quartz base plate.
Step 3003 sequentially forms gate insulation layer, active layer film and drain metallic film.
Step 3004 forms active layer, source electrode and drain electrode by patterning processes.
In the present embodiment, gate insulation layer, active is sequentially formed on the grid line, grid 108 and public electrode wire 107
Layer film and drain metallic film form active layer 201, source electrode 202 and drain electrode 203 by patterning processes.
Step 3005 forms passivation layer, corresponds to the leakage in the passivation layer by patterning processes using the mask plate
Polar region domain forms the first via hole.
It is described that the drain region is corresponded in the passivation layer by patterning processes using the mask plate in the present embodiment
While forming the first via hole, the public electrode wire region is corresponded in the gate insulation layer and passivation layer and forms the second via hole.
Fig. 5 a~Fig. 5 c is the schematic diagram that embodiment three forms via hole.As shown in Fig. 5 a~Fig. 5 c, in the source electrode 202 and drain electrode 203
On form passivation layer 204, positive photoresist 205 is applied on the passivation layer 204, using the mask plate 101 to positivity
Photoresist 205, which is exposed, to be developed to positive photoresist region, positive photoresist part is fully retained to retain region and just
Property photoresist completely remove region, positive photoresist removal region, which corresponds to, forms the first via hole and the second via hole 206
Graphics field, the positive photoresist are fully retained region and positive photoresist part and retain region and correspond to the graphics field
Except other regions, the passivation layer 204 and gate insulation layer 109 are performed etching to form the first via hole and the second via hole
206, it is finally peeled away remaining positive photoresist 205.
Step 3006 forms transparent conductive film.
Step 3007, by patterning processes formed pixel electrode, the pixel electrode by first via hole with it is described
Drain electrode connection.
In the present embodiment, form transparent conductive film on the passivation layer, by patterning processes formed pixel electrode and
Public electrode, the pixel electrode are connected by first via hole and the drain electrode, and the public electrode passes through described second
Via hole is connect with the public electrode wire.
In the preparation method of array substrate provided in this embodiment, the mask plate includes substrate, and the substrate includes non-
Transmission region, partially transparent area and transmission region are provided with non-transparent material layer on the non-transparent region, and the part is saturating
Partial light permeability material layer is provided on light region, the transmission region is not provided with light screening material, and the transmission region is arranged in institute
It states in partially transparent area or the non-transparent region is arranged in the partially transparent area.It is provided in this embodiment to cover
Diaphragm plate can be realized gate mask plate and via hole mask plate shares, to reduce the usage quantity of mask plate, reduce product
Exploitation and production cost.
Example IV
The present embodiment carries out the preparation process of array substrate detailed further below.It should be noted that in the present embodiment
The array substrate is TN mode, but the array substrate of other modes, for example, the array substrate of ADS mode and VA mode
Preparation method also belong to protection scope of the present invention.
The present embodiment provides a kind of preparation methods of array substrate.Referring to Fig. 3, the preparation method includes:
Step 3001 forms grid metal film on substrate.
Step 3002 forms grid line and grid by patterning processes using mask plate.
In the present embodiment, the mask plate that the mask plate uses above-described embodiment two to provide, particular content can refer to above-mentioned
Description in embodiment two, details are not described herein again.
Fig. 6 is a kind of schematic diagram for exposure technology that the embodiment of the present invention four provides.Referring to Fig. 6, Fig. 4 b and Fig. 4 c, in base
Grid metal film 105 is formed on plate, positive photoresist 205 is applied in the grid metal film 105, using the mask plate
101 pairs of positive photoresists 205 be exposed be developed to positive photoresist be fully retained region, positive photoresist part retain
Region and positive photoresist completely remove region, and region and positive photoresist part reserved area is fully retained in the positive photoresist
Domain corresponds to the graphics field for forming grid line, grid 108 and public electrode wire 107, and positive photoresist removal region is corresponding
Other regions except the graphics field perform etching the grid metal film 105 to form grid line, 108 and of grid
Public electrode wire 107 is finally peeled away remaining positive photoresist 205.
Step 3003 sequentially forms gate insulation layer, active layer film and drain metallic film.
Step 3004 forms active layer, source electrode and drain electrode by patterning processes.
In the present embodiment, gate insulation layer, active is sequentially formed on the grid line, grid 108 and public electrode wire 107
Layer film and drain metallic film form active layer 201, source electrode 202 and drain electrode 203 by patterning processes.
Step 3005 forms passivation layer, corresponds to the leakage in the passivation layer by patterning processes using the mask plate
Polar region domain forms the first via hole.
It is described that the drain region is corresponded in the passivation layer by patterning processes using the mask plate in the present embodiment
While forming the first via hole, the public electrode wire region is corresponded in the gate insulation layer and passivation layer and forms the second via hole.
Fig. 7 is the schematic diagram for another exposure technology that the embodiment of the present invention four provides.Referring to Fig. 7, Fig. 5 b and Fig. 5 c, in the source electrode
202 and drain electrode 203 on formed passivation layer 204, on the passivation layer 204 apply negative photoresist 106, using the exposure mask
Plate 101 negative photoresist 106 is exposed be developed to negative photoresist be fully retained region, negative photoresist part protect
Region and negative photoresist is stayed to completely remove region, negative photoresist removal region, which corresponds to, forms the first via hole and second
The graphics field of via hole 206, the negative photoresist are fully retained region and negative photoresist part and retain region and correspond to institute
State other regions except graphics field, to the passivation layer 204 and gate insulation layer 109 perform etching with formed the first via hole and
Second via hole 206 is finally peeled away remaining negative photoresist 106.
Step 3006 forms transparent conductive film.
Step 3007, by patterning processes formed pixel electrode, the pixel electrode by first via hole with it is described
Drain electrode connection.
In the present embodiment, form transparent conductive film on the passivation layer, by patterning processes formed pixel electrode and
Public electrode, the pixel electrode are connected by first via hole and the drain electrode, and the public electrode passes through described second
Via hole is connect with the public electrode wire.
In the preparation method of array substrate provided in this embodiment, the mask plate includes substrate, and the substrate includes non-
Transmission region, partially transparent area and transmission region are provided with non-transparent material layer on the non-transparent region, and the part is saturating
Partial light permeability material layer is provided on light region, the transmission region is not provided with light screening material, and the transmission region is arranged in institute
It states in partially transparent area or the non-transparent region is arranged in the partially transparent area.It is provided in this embodiment to cover
Diaphragm plate can be realized gate mask plate and via hole mask plate shares, to reduce the usage quantity of mask plate, reduce product
Exploitation and production cost.
Embodiment five
The present embodiment carries out the preparation process of display panel detailed further below.It should be noted that in the present embodiment
The display panel is TN mode, but the display panel of other modes, for example, the display panel of ADS mode and VA mode
Preparation method also belong to protection scope of the present invention.
The preparation method for present embodiments providing a kind of display panel is provided including above-described embodiment three or example IV
The preparation method of array substrate, particular content can refer to the description of above-described embodiment three or example IV, and details are not described herein again.
In the preparation method of display panel provided in this embodiment, the mask plate includes substrate, and the substrate includes non-
Transmission region, partially transparent area and transmission region are provided with non-transparent material layer on the non-transparent region, and the part is saturating
Partial light permeability material layer is provided on light region, the transmission region is not provided with light screening material, and the transmission region is arranged in institute
It states in partially transparent area or the non-transparent region is arranged in the partially transparent area.It is provided in this embodiment to cover
Diaphragm plate can be realized gate mask plate and via hole mask plate shares, to reduce the usage quantity of mask plate, reduce product
Exploitation and production cost.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (5)
1. a kind of mask plate, which is characterized in that including substrate, the substrate include non-transparent region, partially transparent area and thoroughly
Light region is provided with non-transparent material layer on the non-transparent region, partial light permeability material is provided in the partially transparent area
The bed of material, the transmission region are not provided with light screening material, and the transmission region setting is in the partially transparent area or described
Non-transparent region is arranged in the partially transparent area；
When the transmission region is arranged in the partially transparent area, the transmission region and partially transparent area are for leading to
It crosses etching after being exposed development to negative photoresist and forms grid line, grid and public electrode wire, the transmission region is also used to
The first via hole and the second via hole are formed by etching after being exposed development to positive photoresist；Or
When the non-transparent region is arranged in the partially transparent area, the non-transparent region and partially transparent area are used
In by positive photoresist is exposed development after etching form grid line, grid and public electrode wire, the non-transparent region
It is also used to form the first via hole and the second via hole by etching after being exposed development to negative photoresist.
2. mask plate according to claim 1, which is characterized in that the constituent material of the non-transparent material layer includes metal
Material, the constituent material of the partial light permeability material layer include metal oxide or resin.
3. mask plate according to claim 2, which is characterized in that the metal material includes crome metal, the metal oxygen
Compound includes chromium oxide.
4. a kind of preparation method of array substrate characterized by comprising
Grid metal film is formed on substrate；
Grid line and grid are formed by patterning processes using mask plate, the mask plate includes claim 1-3 any described
Mask plate；
Sequentially form gate insulation layer, active layer film and drain metallic film；
Active layer, source electrode and drain electrode are formed by patterning processes；
Passivation layer is formed, the drain region is corresponded in the passivation layer by patterning processes using the mask plate and forms first
Via hole；
Form transparent conductive film；
Pixel electrode is formed by patterning processes, the pixel electrode is connected by first via hole and the drain electrode；
While the use mask plate forms grid line and grid by patterning processes, public electrode wire is formed；
It is described that the first via hole of the drain region formation is corresponded in the passivation layer by patterning processes using the mask plate
Meanwhile the public electrode wire region is corresponded in the gate insulation layer and passivation layer and forms the second via hole；
While the formation pixel electrode by patterning processes, public electrode is formed, the public electrode passes through described second
Via hole is connect with the public electrode wire；
It is described that grid are formed by patterning processes using mask plate when the transmission region is arranged in the partially transparent area
While line and grid, formed public electrode wire the step of include:
Apply negative photoresist in the grid metal film, use the mask plate to negative photoresist be exposed development with
Region is fully retained in formation negative photoresist, negative photoresist part retains region and negative photoresist completely removes region, institute
It states negative photoresist and region and negative photoresist part is fully retained retains region and correspond to and form grid line, grid and public electrode
The graphics field of line, the negative photoresist completely remove region corresponding to other regions except the graphics field；
The grid metal film is performed etching to form grid line, grid and public electrode wire；
Remove remaining negative photoresist；
It is described that the first via hole of the drain region formation is corresponded in the passivation layer by patterning processes using the mask plate
Meanwhile the step of public electrode wire region forms the second via hole is corresponded in the gate insulation layer and passivation layer and includes:
Positive photoresist is applied on the passivation layer, positive photoresist is exposed using the mask plate and is developed to
Region is fully retained in positive photoresist, positive photoresist part retains region and positive photoresist and completely removes region, it is described just
Property photoresist removal region correspond to and form the graphics field of the first via hole and the second via hole, the positive photoresist is fully retained
Region and positive photoresist part retain other regions that region corresponds to except the graphics field；
The passivation layer and gate insulation layer are performed etching to form the first via hole and the second via hole；
Remove remaining positive photoresist；
It is described to be formed using mask plate by patterning processes when the non-transparent region is arranged in the partially transparent area
While grid line and grid, formed public electrode wire the step of include:
Apply positive photoresist in the grid metal film, use the mask plate to positive photoresist be exposed development with
Region is fully retained in formation positive photoresist, positive photoresist part retains region and positive photoresist completely removes region, institute
It states positive photoresist and region and positive photoresist part is fully retained retains region and correspond to and form grid line, grid and public electrode
The graphics field of line, positive photoresist removal region correspond to other regions except the graphics field；
The grid metal film is performed etching to form grid line, grid and public electrode wire；
Remove remaining positive photoresist；
It is described that the first via hole of the drain region formation is corresponded in the passivation layer by patterning processes using the mask plate
Meanwhile the step of public electrode wire region forms the second via hole is corresponded in the gate insulation layer and passivation layer and includes:
Negative photoresist is applied on the passivation layer, negative photoresist is exposed using the mask plate and is developed to
Region is fully retained in negative photoresist, negative photoresist part retains region and negative photoresist completely removes region, described negative
Property photoresist removal region correspond to and form the graphics field of the first via hole and the second via hole, the negative photoresist is fully retained
Region and negative photoresist part retain other regions that region corresponds to except the graphics field；
The passivation layer and gate insulation layer are performed etching to form the first via hole and the second via hole；
Remove remaining negative photoresist.
5. a kind of preparation method of display panel, which is characterized in that the preparation side including array substrate as claimed in claim 4
Method.
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| CN110739317A (en) * | 2019-11-26 | 2020-01-31 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display panel |
| CN114038737B (en) * | 2021-08-17 | 2022-08-26 | 重庆康佳光电技术研究院有限公司 | Mask plate using method, light-emitting device and manufacturing method thereof |
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