CN101060123A - A TFT LCD array base plate and its manufacture method - Google Patents

A TFT LCD array base plate and its manufacture method Download PDF

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Publication number
CN101060123A
CN101060123A CN 200610074457 CN200610074457A CN101060123A CN 101060123 A CN101060123 A CN 101060123A CN 200610074457 CN200610074457 CN 200610074457 CN 200610074457 A CN200610074457 A CN 200610074457A CN 101060123 A CN101060123 A CN 101060123A
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layer
electrode
mask
mow
drain electrode
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CN 200610074457
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CN100544004C (en
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邓朝勇
林承武
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN 200610074457 priority Critical patent/CN100544004C/en
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US11/737,954 priority patent/US7952099B2/en
Priority to KR1020070039430A priority patent/KR100898694B1/en
Priority to JP2007113400A priority patent/JP2007294970A/en
Publication of CN101060123A publication Critical patent/CN101060123A/en
Application granted granted Critical
Publication of CN100544004C publication Critical patent/CN100544004C/en
Priority to US13/096,380 priority patent/US8354305B2/en
Priority to JP2011103041A priority patent/JP5564464B2/en
Priority to US13/735,166 priority patent/US8642404B2/en
Priority to US14/056,199 priority patent/US20140038371A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)

Abstract

The related TFT LCD array substrate comprises: a glass substrate with grid wire and grid electrode, an insulation medium layer on the electrode, a semi-conductor layer, an ohmic contact layer, a transparent pixel electrode, a source/drain electrode, a data line, and a passive layer. Compared with current prior, this invention simplifies process, improves efficiency, and can use same magnetron sputtering device to continual deposit the pixel layer and source/drain electrode.

Description

A kind of TFT LCD array base palte and manufacture method thereof
Technical field
The present invention relates to a kind of Thin Film Transistor-LCD (TFT LCD) array base palte and manufacture method thereof, relate in particular to the structure and the method for 4 photoetching of a kind of usefulness (4Mask) technology manufacturing array substrate.
Background technology
The liquid crystal display that with TFT LCD is representative has had development at full speed as a kind of important flat panel display mode in nearly ten years, get more and more people's extensive concerning.Because the cut-throat competition between each manufacturer and the continuous progress of TFT LCD manufacturing technology, display quality is good, and the LCD that price is more cheap is constantly introduced to the market.Therefore, adopt advanced more manufacturing technology, simplify production technology, reducing production costs becomes the important assurance that TFT LCD production firm is survived in cut-throat competition.
The manufacturing technology of TFT LCD array base palte has experienced from the evolution of 7 photoetching techniques (7Mask), 5 photoetching techniques (5Mask) up till now, and the 5Mask technology becomes the main flow that present TFT LCD array base palte is made.
Part manufacturer also begins now at 4Mask technology, the 4Mask technology is to be benchmark with the 5Mask technology, utilize gray tone photoetching (Gray Tone Mask) technology, active layer photoetching (ActiveMask) and source-drain electrode photoetching (S/D Mask) are merged into a Mask, by adjusting etching (Etch) technology, thereby finish the function of original Active Mask and S/D Mask, promptly reach the effect of twice Mask technology by Mask technology.
Gray Tone Mask technology is to use the figure that has strip (Slit) on Mask, by the interference and the diffraction effect of light, forms translucent graphics field on Mask.In exposure process, light can only partly see through translucent area.By the control exposure, shine on the photoresist after can making light by the Gray Tone zone on the Mask, photoresist can only partly be exposed, and other parts can fully be exposed.After the development, complete exposure area does not have photoresist, and fully the thickness of exposed areas photoresist will be less than complete unexposed zone, thereby forms 3-D solid structure on photoresist.By the transmitance in control Gray Tone zone, i.e. " duty ratio " of lines zone and white space can be controlled the thickness of photoresist.Thereby thisly be collectively referred to as Gray Tone Mask technology in the method for using translucent graphic on photoresist, to form the different three-D pattern of thickness on the mask blank.
The 5Mask technology comprises photoetching process 5 times, and they are respectively gate electrode photoetching (Gate Mask), active layer photoetching (Active Mask), source-drain electrode photoetching (S/D Mask), via hole photoetching (ViaHole Mask) and pixel electrode photoetching (Pixel Mask).In each Mask processing step, comprise one or many thin film deposition (Thin Film Deposition) technology and etching technics (comprising dry etching Dry Etch and wet etching Wet Etch) technology again respectively, formed the cyclic process of 5 thin film deposition → photoetching → etchings.Specific embodiment such as Fig. 2.
The typical pixel cells of the resulting TFT LCD of the 5Mask technological process array base palte that process is above as shown in Figure 1.
Summary of the invention
The present invention seeks at Developing Trend in Technology, a kind of minimizing photoetching process is provided, thereby reduce processing step, improve production capacity and reduce cost; And the raising usage ratio of equipment, reduce the process time, the TFT LCD array base palte and the manufacture method thereof of enhancing productivity.
To achieve these goals, the invention provides a kind of TFT LCD array base palte, a kind of TFT LCD array base palte, comprise: substrate, be formed at grid line and gate electrode on the substrate, be formed at insulating medium layer, active layer and ohmic contact layer on the gate electrode, transparent pixels electrode, source-drain electrode, data wire, and passivation layer, it is characterized in that: described ohmic contact layer is specially the microcrystal silicon material layer, the transparent pixels electrode be positioned at the microcrystal silicon material layer the top and with microcrystal silicon material layer ohmic contact, source-drain electrode is formed at the top of transparent pixels electrode.
Wherein, described grid line and gate electrode can be one deck, two-layer or sandwich construction, as adopting the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps are one of AlNd, Al, Cu Mo, MoW, Cr or composite membrane that combination in any constituted.Described insulating medium layer is specially the monofilm of SiNx, SiOx or SiOxNy, perhaps is one of SiNx, SiOx, SiOxNy or composite membrane that combination in any constituted.Described source-drain electrode is specially the monofilm of Mo, MoW or Cr, perhaps is one of Mo, MoW, Cr or composite membrane that combination in any constituted.
In order to realize the foregoing invention purpose, the present invention also provides a kind of manufacture method of TFT LCD array base palte simultaneously, it is characterized in that, comprising:
Step 1 adopts magnetron sputtering technique to deposit a gate metal layer on substrate, carries out mask and etching, obtains grid line and gate electrode;
Step 2 adopts chemical vapour deposition technique to deposit an insulating medium layer on the substrate of completing steps one, an active layer, and an ohmic contact layer carries out mask and etching, forms the film crystal tube portion;
Step 3, adopt magnetron sputtering technique on the substrate of completing steps two, to deposit a transparent pixels electrode layer, a source-drain electrode metal level carries out mask and etching with the gray tone mask plate, forms transparent pixels electrode, source-drain electrode and film crystal tube portion channel part;
Step 4 adopts chemical vapour deposition technique to deposit a passivation layer on the substrate of completing steps three, carries out mask and etching, forms via hole and raceway groove is formed protection, exposes the binding lead-in wire simultaneously.
Wherein, when adopting gray tone mask plate mask to carry out mask in the described step 3, make the corresponding transparent pixels electrode of the semi-transparent part of mask plate part, corresponding source-drain electrode of mask plate lightproof part and data wire part, the corresponding remainder in the complete light transmission part of mask plate.The ohmic contact layer that deposits in the described step 2 is specially the microcrystal silicon material layer.Transparent pixels electrode layer described in the described step 3 and source-drain electrode metal level are to deposit continuously in identical or different equipment.The deposition gate metal layer is specially the monofilm of depositing Al Nd, Al, Cu, Mo, MoW or Cr in the described step 1, perhaps among depositing Al Nd, Al, Cu, Mo, MoW or the Cr one of or composite membrane that combination in any constituted.The deposition insulating medium layer is specially the monofilm of deposition SiNx, SiOx or SiOxNy in the described step 2, perhaps deposits one of SiNx, SiOx, SiOxNy or composite membrane that combination in any constituted.Sedimentary origin drain electrode metal level is specially the monofilm of deposition Mo, MoW or Cr in the described step 3, perhaps deposits one of Mo, MoW, Cr or composite membrane that combination in any constituted.
The present invention and existing 5 lithographic fabrication processes relatively mainly contain following effect: a kind of new the TFT LCD array base palte and the manufacture method thereof that are different from existing 5Mask and 4Mask technology are provided; By being 4Mask technology, thereby reach the purpose that reduces processing step, enhances productivity and reduce production costs with original 5Mask work simplification; By merging S/D Mask and ITO Mask, make that S/D metal level and ITO layer can successive sedimentations in same Sputter equipment, thereby when enhancing productivity, improved the Sputter usage ratio of equipment.
Below in conjunction with the drawings and specific embodiments the present invention is done further more detailed explanation.
Description of drawings
Fig. 1 is a TFT LCD array base palte typical pixel cells planar graph;
Fig. 2 is traditional 5Mask technological process;
Fig. 3 is technological process of the present invention;
The TFT LCD array base palte typical pixel cells planar graph of Fig. 4 for adopting the present invention to obtain;
Fig. 5 is Fig. 4 A-A cross section figure;
Fig. 6 is the planar graph through obtaining behind the Gate Mask;
Fig. 7 is Fig. 6 A-A cross section figure;
Fig. 8 is the planar graph through obtaining behind the Active Mask;
Fig. 9 is Fig. 8 A-A cross section figure;
Figure 10 is the planar graph through obtaining behind the G/T S/D Mask
Figure 11 is Figure 10 A-A cross section figure;
Figure 12 is through resulting plane and cross section figure behind the Via Hole Mask;
Figure 13 is Figure 12 A-A cross section figure.
Identify among the figure:
1, glass substrate; 2, gate electrode; 3, insulating barrier; 4, semiconductor layer; 5, transparent pixels electrode layer; 6, source-drain electrode; 7, passivation layer.
Embodiment
Below, describe preferred implementation of the present invention in detail with reference to accompanying drawing.In order to realize the present invention, the specific embodiment of employing is seen Fig. 3.
Step 1 adopts magnetically controlled sputter method on glass substrate 1, deposition gate metal layer, Mo/AlND/Mo (400/4000/600 ).Carry out the gate metal layer mask then, and carry out wet etching, form grid line and gate electrode 2, as Fig. 6 and Fig. 7.
As flexible mode, deposition obtains the monofilm that gate metal layer can be AlNd, Al, Cu, Mo, MoW or Cr in this step, also can be for one of Al Nd, Al, Cu, Mo, MoW, Cr or composite membrane that combination in any constituted, as the composite membrane of Mo/AlNd/Mo or AlNd/Mo metal.
Step 2 on the basis of finishing the gate metal layer etching, adopts PECVD to deposit gate insulation layer 3 successively, semiconductor layer 4, ohmic contact layer, i.e. SiNx/a-Si/uc-Si (5000 /2000 /500 ).For the transparent pixels electrode that guarantees the back and the ohmic contact of semiconductor layer, ohmic contact layer adopts microcrystal silicon (uc-Si) material rather than n+a-Si herein; Next carry out the active layer mask, process active layer etching obtains the active layer part of TFT, as Fig. 8 and (not expressing in the ohmic contact layer uc-Si partial graph) shown in Figure 9.
As flexible mode, the gate insulation layer in this step can be one of the monofilm of SiNx, SiOx or SiOxNy or SiNx, SiOx, SiOxNy or composite membrane that combination in any constituted.
Step 3, adopt magnetically controlled sputter method, successive sedimentation transparent pixels electrode layer 5, as ITO (500 ), former drain electrode layer, as Mo (3000 ), adopt the gray tone mask technique to carry out mask, the mask plate of transparent pixels electrode part is semi-transparent part, and the mask plate of source-drain electrode and data wire part is complete shield portions, the mask plate of remainder is complete light transmission part, behind G/T S/D Etch, carry out the uc-Si etching, obtain transparent pixels electrode and source at last and leak and data wire, and form the TFT raceway groove, as Figure 10 and Figure 11 (uc-Si of channel part partly expresses among the figure); S/D metal level and transparent pixels electrode layer can be in the successive sedimentations of same Sputter equipment in this step, thereby when enhancing productivity, improve the Sputter usage ratio of equipment.
As flexible mode, former drain electrode layer can be one of the monofilm of Mo, MoW or Cr or Mo, MoW, Cr or composite membrane that combination in any constituted; Metal electrode layer is leaked in the source can successive sedimentation in different Sputter equipment with the transparent pixels electrode layer.
Step 4 adopts plasma reinforced chemical vapour deposition (PECVD) to carry out passivation layer 7 depositions, and thickness is about 2600 , carries out passivation layer mask and etching, forms via hole and raceway groove is formed protection, exposes binding (Pad) lead-in wire simultaneously, as Figure 12 and Figure 13.
Adopt the manufacture method of 4Mask technology by above method, obtained complete tft array substrate, reducing processing step, reduce production cost and improved production efficiency, simultaneously by Sputter equipment successive sedimentation S/D metal level and ITO layer, improved Sputter efficiency of equipment and utilance, in addition, the present invention also provides a kind of new manufacture method that is different from the TFT LCD array base palte that has 5Mask technology and 4Mask technology now.
By above-mentioned technological process, obtain of the present invention a kind of TFT LCD array base palte as shown in Figure 4 and Figure 5.Be substrate 1, be formed at grid line and gate electrode 2 on the substrate 1, be formed at insulating medium layer 3, semiconductor layer 4 and ohmic contact layer on the gate electrode, transparent pixels electrode 5, source-drain electrode 6 data wires, and passivation layer 7, wherein ohmic contact layer is made of the microcrystal silicon material, and transparent pixels electrode 6 is positioned at the top of ohmic contact layer, and by microcrystal silicon material realization ohmic contact, source-drain electrode 6 is formed at the top of transparent pixels electrode 5.
Present embodiment has only provided realizes the specific embodiment of the present invention, but device architecture in this scheme and process conditions can change, as, adopt negative photoresist, the layers of material structure and the thickness of deposition, the basic deposition and the etching condition that adopt can change according to the specific requirement of LCD, but spirit and category that this variation can not depart from transparent pixels electrode layer and the successive sedimentation of S/D electrode layer and adopt the gray tone mask technique to form under same Mask, otherwise be considered as of the present inventionly being equal to or replacing.

Claims (11)

1, a kind of TFT LCD array base palte, comprise: substrate, be formed at grid line and gate electrode on the substrate, be formed at insulating medium layer, active layer and ohmic contact layer on the gate electrode, transparent pixels electrode, source-drain electrode, data wire, and passivation layer, it is characterized in that: described ohmic contact layer is specially the microcrystal silicon material layer, the transparent pixels electrode be positioned at the microcrystal silicon material layer the top and with microcrystal silicon material layer ohmic contact, source-drain electrode is formed at the top of transparent pixels electrode.
2, array base palte according to claim 1, it is characterized in that: described grid line and gate electrode are specially the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps are one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.
3, array base palte according to claim 1 is characterized in that: described insulating medium layer is specially the monofilm of SiNx, SiOx or SiOxNy, perhaps is one of SiNx, SiOx, SiOxNy or composite membrane that combination in any constituted.
4, array base palte according to claim 1 is characterized in that: described source-drain electrode is specially the monofilm of Mo, MoW or Cr, perhaps is one of Mo, MoW, Cr or composite membrane that combination in any constituted.
5, a kind of manufacture method of TFT LCD array base palte is characterized in that: comprising:
Step 1 adopts magnetron sputtering technique to deposit a gate metal layer on substrate, carries out mask and etching, obtains grid line and gate electrode;
Step 2 adopts chemical vapour deposition technique to deposit an insulating medium layer on the substrate of completing steps one, an active layer, and an ohmic contact layer carries out mask and etching, forms the film crystal tube portion;
Step 3, adopt magnetron sputtering technique on the substrate of completing steps two, to deposit a transparent pixels electrode layer, a source-drain electrode metal level carries out mask and etching with the gray tone mask plate, forms transparent pixels electrode, source-drain electrode and film crystal tube portion channel part;
Step 4 adopts chemical vapour deposition technique to deposit a passivation layer on the substrate of completing steps three, carries out mask and etching, forms via hole and raceway groove is formed protection, exposes the binding lead-in wire simultaneously.
6, method according to claim 5, it is characterized in that: when adopting gray tone mask plate mask to carry out mask in the described step 3, make the corresponding transparent pixels electrode of the semi-transparent part of mask plate part, corresponding source-drain electrode of mask plate lightproof part and data wire part, the corresponding remainder in the complete light transmission part of mask plate.
7, method according to claim 5 is characterized in that: the ohmic contact layer that deposits in the described step 2 is specially the microcrystal silicon material layer.
8, method according to claim 5 is characterized in that: transparent pixels electrode layer described in the described step 3 and source-drain electrode metal level are to deposit continuously in identical or different equipment.
9, according to the arbitrary described method of claim 5 to 8, it is characterized in that: the deposition gate metal layer is specially the monofilm of depositing Al Nd, Al, Cu, Mo, MoW or Cr in the described step 1, perhaps among depositing Al Nd, Al, Cu, Mo, MoW or the Cr one of or composite membrane that combination in any constituted.
10, according to the arbitrary described method of claim 5 to 8, it is characterized in that: the deposition insulating medium layer is specially the monofilm of deposition SiNx, SiOx or SiOxNy in the described step 2, perhaps deposits one of SiNx, SiOx, SiOxNy or composite membrane that combination in any constituted.
11, according to the arbitrary described method of claim 5 to 8, it is characterized in that: sedimentary origin drain electrode metal level is specially the monofilm of deposition Mo, MoW or Cr in the described step 3, perhaps deposits one of Mo, MoW, Cr or composite membrane that combination in any constituted.
CN 200610074457 2006-04-21 2006-04-21 A kind of TFT LCD array base palte and manufacture method thereof Active CN100544004C (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
CN 200610074457 CN100544004C (en) 2006-04-21 2006-04-21 A kind of TFT LCD array base palte and manufacture method thereof
US11/737,954 US7952099B2 (en) 2006-04-21 2007-04-20 Thin film transistor liquid crystal display array substrate
KR1020070039430A KR100898694B1 (en) 2006-04-21 2007-04-23 Tft lcd array substrate and manufacturing method thereof
JP2007113400A JP2007294970A (en) 2006-04-21 2007-04-23 Tft-lcd array substrate and its manufacturing method
US13/096,380 US8354305B2 (en) 2006-04-21 2011-04-28 Thin film transistor liquid crystal display array substrate and manufacturing method thereof
JP2011103041A JP5564464B2 (en) 2006-04-21 2011-05-02 TFT-LCD array substrate and manufacturing method thereof
US13/735,166 US8642404B2 (en) 2006-04-21 2013-01-07 Thin film transistor liquid crystal display array substrate and manufacturing method thereof
US14/056,199 US20140038371A1 (en) 2006-04-21 2013-10-17 Thin film transistor liquid crystal display array substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200610074457 CN100544004C (en) 2006-04-21 2006-04-21 A kind of TFT LCD array base palte and manufacture method thereof

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CN101060123A true CN101060123A (en) 2007-10-24
CN100544004C CN100544004C (en) 2009-09-23

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Cited By (12)

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Publication number Priority date Publication date Assignee Title
CN101667572A (en) * 2008-09-04 2010-03-10 三星电子株式会社 Thin film transistor array panel and method for manufacturing the same
CN102122673A (en) * 2010-11-30 2011-07-13 友达光电股份有限公司 Oxide semiconductor thin film transistor structure and manufacturing method thereof
US8199270B2 (en) 2008-12-30 2012-06-12 Beijing Boe Optoelectronics Technology Co., Ltd. TFT-LCD array substrate and method of manufacturing the same
CN102598281A (en) * 2009-11-03 2012-07-18 应用材料公司 Thin film transistors having multiple doped silicon layers
CN102629578A (en) * 2011-09-29 2012-08-08 京东方科技集团股份有限公司 TFT array substrate and manufacturing method thereof and display device
CN103199112A (en) * 2013-03-20 2013-07-10 北京京东方光电科技有限公司 Array substrate, preparation method of array substrate and display panel
CN101510031B (en) * 2008-02-15 2013-09-04 乐金显示有限公司 Array substrate, liquid crystal display module including the array substrate and method of fabricating the array substrate
WO2013131384A1 (en) * 2012-03-05 2013-09-12 京东方科技集团股份有限公司 Thin-film transistor array substrate, manufacturing method therefor, and electronic device
CN103715137A (en) * 2013-12-26 2014-04-09 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
CN104635419A (en) * 2015-03-11 2015-05-20 京东方科技集团股份有限公司 Array substrate as well as preparation method of display panel, and mask plate
CN105629598A (en) * 2016-03-11 2016-06-01 深圳市华星光电技术有限公司 FFS mode array substrate and manufacturing method
CN109884830A (en) * 2019-02-28 2019-06-14 京东方科技集团股份有限公司 Array substrate and preparation method thereof, display device, mask plate

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101510031B (en) * 2008-02-15 2013-09-04 乐金显示有限公司 Array substrate, liquid crystal display module including the array substrate and method of fabricating the array substrate
CN101667572A (en) * 2008-09-04 2010-03-10 三星电子株式会社 Thin film transistor array panel and method for manufacturing the same
US8199270B2 (en) 2008-12-30 2012-06-12 Beijing Boe Optoelectronics Technology Co., Ltd. TFT-LCD array substrate and method of manufacturing the same
CN101770124B (en) * 2008-12-30 2014-09-10 北京京东方光电科技有限公司 Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof
CN102598281B (en) * 2009-11-03 2015-06-10 应用材料公司 Thin film transistors having multiple doped silicon layers
CN102598281A (en) * 2009-11-03 2012-07-18 应用材料公司 Thin film transistors having multiple doped silicon layers
CN102122673B (en) * 2010-11-30 2013-01-02 友达光电股份有限公司 Oxide semiconductor thin film transistor structure and manufacturing method thereof
CN102122673A (en) * 2010-11-30 2011-07-13 友达光电股份有限公司 Oxide semiconductor thin film transistor structure and manufacturing method thereof
CN102629578A (en) * 2011-09-29 2012-08-08 京东方科技集团股份有限公司 TFT array substrate and manufacturing method thereof and display device
WO2013131384A1 (en) * 2012-03-05 2013-09-12 京东方科技集团股份有限公司 Thin-film transistor array substrate, manufacturing method therefor, and electronic device
US8952387B2 (en) 2012-03-05 2015-02-10 Boe Technology Group Co., Ltd. Thin film transistor array substrate and method for manufacturing the same
CN103199112A (en) * 2013-03-20 2013-07-10 北京京东方光电科技有限公司 Array substrate, preparation method of array substrate and display panel
WO2014146362A1 (en) * 2013-03-20 2014-09-25 北京京东方光电科技有限公司 Array substrate and preparation method thereof, and display panel
US9685460B2 (en) 2013-12-26 2017-06-20 Boe Technology Group Co., Ltd. Array substrate, method for manufacturing the same, and display device
CN103715137A (en) * 2013-12-26 2014-04-09 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
CN103715137B (en) * 2013-12-26 2018-02-06 京东方科技集团股份有限公司 Array base palte and its manufacture method, display device
CN104635419A (en) * 2015-03-11 2015-05-20 京东方科技集团股份有限公司 Array substrate as well as preparation method of display panel, and mask plate
CN104635419B (en) * 2015-03-11 2019-05-24 京东方科技集团股份有限公司 Preparation method, the mask plate of a kind of array substrate and its display panel
CN105629598A (en) * 2016-03-11 2016-06-01 深圳市华星光电技术有限公司 FFS mode array substrate and manufacturing method
CN109884830A (en) * 2019-02-28 2019-06-14 京东方科技集团股份有限公司 Array substrate and preparation method thereof, display device, mask plate

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