CN104635419A - Array substrate as well as preparation method of display panel, and mask plate - Google Patents
Array substrate as well as preparation method of display panel, and mask plate Download PDFInfo
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- CN104635419A CN104635419A CN201510106454.1A CN201510106454A CN104635419A CN 104635419 A CN104635419 A CN 104635419A CN 201510106454 A CN201510106454 A CN 201510106454A CN 104635419 A CN104635419 A CN 104635419A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/54—Absorbers, e.g. of opaque materials
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1303—Apparatus specially adapted to the manufacture of LCDs
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/60—Substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
The invention provides an array substrate, a preparation method of a display panel, and a mask plate. The mask plate comprises a baseplate, wherein the baseplate comprises a light-proof area, a partial light-transmission area and a light transmission area; the light-proof area is provided with a light-proof material layer, the partial light-transmission area is provided with a partial-light-transmission material layer, the light transmission area is not provided with a light shading material, the light transmission area is arranged in the partial light-transmission area, or the light-proof area is arranged in the partial light-transmission area. By adopting the mask plate, the sharing of a grid mask plate and a through-hole mask plate can be realized, so that the use amount of the mask plate can be reduced, and the development and production cost of products can be reduced.
Description
Technical field
The present invention relates to display technique field, particularly relate to the preparation method of a kind of array base palte and display panel thereof, mask plate.
Background technology
In TFT-LCD manufacturing, the manufacture process of array base palte needs to carry out 4-7 exposure technology, therefore 4-7 block mask plate (Mask) is needed, such as, the array base palte of common twisted-nematic (Twisted Nematic, TN) pattern needs gate mask plate (Gate Mask), active layer mask plate (Active Mask), source-drain electrode mask plate (S/D Mask), via hole mask plate (Via Mask), pixel electrode mask plate (ITO Mask) totally five pieces of mask plates.Every block mask plate is worth 100-200 ten thousand Renminbi, and therefore only a product just needs to spend substantial contribution on purchase mask plate, improves product development and production cost.
Summary of the invention
For solving the problem, the invention provides the preparation method of a kind of array base palte and display panel thereof, mask plate, the problem that the production cost for solving the display panel that mask plate in prior art causes is too high.
For solving the problem, the invention provides a kind of mask plate, comprise substrate, described substrate comprises alternatively non-transparent region, partial light permeability region and transmission region, described alternatively non-transparent region is provided with alternatively non-transparent material layer, and described partial light permeability region is provided with partial light permeability material layer, and described transmission region does not arrange light screening material, described transmission region is arranged in described partial light permeability region, or described alternatively non-transparent region is arranged in described partial light permeability region.
Optionally, when described transmission region is arranged in described partial light permeability region, described transmission region and partial light permeability region are for the formation of grid line, grid and public electrode wire, and described transmission region is also for the formation of the first via hole and the second via hole; Or
When described alternatively non-transparent region is arranged in described partial light permeability region, described alternatively non-transparent region and partial light permeability region are for the formation of grid line, grid and public electrode wire, and described alternatively non-transparent region is also for the formation of the first via hole and the second via hole.
Optionally, the constituent material of described alternatively non-transparent material layer comprises metal material, and the constituent material of described partial light permeability material layer comprises metal oxide or resin.
Optionally, described metal material comprises crome metal, and described metal oxide comprises chromium oxide.
The present invention also provides a kind of preparation method of array base palte, comprising:
Substrate is formed grid metallic film;
Adopt mask plate to form grid line and grid by patterning processes, described mask plate comprises above-mentioned arbitrary mask plate;
Form gate insulation layer, active layer film and source and drain metallic film successively;
Active layer, source electrode and drain electrode is formed by patterning processes;
Form passivation layer, adopt described mask plate to form the first via hole by patterning processes in the corresponding described drain region of described passivation layer,
Form transparent conductive film;
Form pixel electrode by patterning processes, described pixel electrode is connected with described drain electrode by described first via hole.
Optionally, described employing mask plate forms public electrode wire while forming grid line and grid by patterning processes;
The described mask plate of described employing while the corresponding described drain region of described passivation layer forms the first via hole, forms second via hole at described gate insulation layer and the corresponding described public electrode wire region of passivation layer by patterning processes;
Described by while patterning processes formation pixel electrode, form public electrode, described public electrode is connected with described public electrode wire by described second via hole.
Optionally, while described employing mask plate forms grid line and grid by patterning processes, the step forming public electrode wire comprises:
Described grid metallic film applies negative photoresist, adopt described mask plate to carry out exposure imaging to negative photoresist and remove region completely to form the complete reserve area of negative photoresist, negative photoresist part reserve area and negative photoresist, the complete reserve area of described negative photoresist and negative photoresist part reserve area correspond to the graphics field forming grid line, grid and public electrode wire, and described negative photoresist removes region completely corresponding to other region outside described graphics field;
Etch to form grid line, grid and public electrode wire to described grid metallic film;
Peel off remaining negative photoresist;
The described mask plate of described employing is by patterning processes while the corresponding described drain region of described passivation layer forms the first via hole, and the step forming the second via hole at described gate insulation layer and the corresponding described public electrode wire region of passivation layer comprises:
Described passivation layer applies positive photoresist, adopt described mask plate to carry out exposure imaging to positive photoresist and remove region completely to form the complete reserve area of positive photoresist, positive photoresist part reserve area and positive photoresist, the graphics field that region corresponds to formation first via hole and the second via hole removed by described positive photoresist, and the complete reserve area of described positive photoresist and positive photoresist part reserve area correspond to other region outside described graphics field;
Etch to form the first via hole and the second via hole to described passivation layer and gate insulation layer;
Peel off remaining positive photoresist.
Optionally, while described employing mask plate forms grid line and grid by patterning processes, the step forming public electrode wire comprises:
Described grid metallic film applies positive photoresist, adopt described mask plate to carry out exposure imaging to positive photoresist and remove region completely to form the complete reserve area of positive photoresist, positive photoresist part reserve area and positive photoresist, the complete reserve area of described positive photoresist and positive photoresist part reserve area correspond to the graphics field forming grid line, grid and public electrode wire, and described positive photoresist removes region corresponding to other region outside described graphics field;
Etch to form grid line, grid and public electrode wire to described grid metallic film;
Peel off remaining positive photoresist;
The described mask plate of described employing is by patterning processes while the corresponding described drain region of described passivation layer forms the first via hole, and the step forming the second via hole at described gate insulation layer and the corresponding described public electrode wire region of passivation layer comprises:
Described passivation layer applies negative photoresist, adopt described mask plate to carry out exposure imaging to negative photoresist and remove region completely to form the complete reserve area of negative photoresist, negative photoresist part reserve area and negative photoresist, described negative photoresist removes the graphics field that region corresponds to formation first via hole and the second via hole, and the complete reserve area of described negative photoresist and negative photoresist part reserve area correspond to other region outside described graphics field;
Etch to form the first via hole and the second via hole to described passivation layer and gate insulation layer;
Peel off remaining negative photoresist.
The present invention also provides a kind of preparation method of display panel, comprises the preparation method of above-mentioned arbitrary array base palte.
The present invention has following beneficial effect:
In the preparation method of array base palte provided by the invention and display panel thereof, mask plate, described mask plate comprises substrate, described substrate comprises alternatively non-transparent region, partial light permeability region and transmission region, described alternatively non-transparent region is provided with alternatively non-transparent material layer, described partial light permeability region is provided with partial light permeability material layer, described transmission region does not arrange light screening material, described transmission region is arranged in described partial light permeability region, or described alternatively non-transparent region is arranged in described partial light permeability region.Mask plate provided by the invention can realize gate mask plate and via hole mask plate shares, thus decreases the usage quantity of mask plate, reduces product development and production cost.
Accompanying drawing explanation
The structural representation of a kind of mask plate that Fig. 1 provides for the embodiment of the present invention one;
The structural representation of a kind of mask plate that Fig. 2 provides for the embodiment of the present invention two;
The process flow diagram of the preparation method of a kind of array base palte that Fig. 3 provides for the embodiment of the present invention three;
Fig. 4 a ~ Fig. 4 c is the schematic diagram that embodiment three forms grid and public electrode wire;
Fig. 5 a ~ Fig. 5 c is the schematic diagram that embodiment three forms via hole;
The schematic diagram of a kind of exposure technology that Fig. 6 provides for the embodiment of the present invention four;
The schematic diagram of the another kind of exposure technology that Fig. 7 provides for the embodiment of the present invention four.
Embodiment
For making those skilled in the art understand technical scheme of the present invention better, below in conjunction with accompanying drawing, the preparation method of array base palte provided by the invention and display panel thereof, mask plate are described in detail.
Embodiment one
The structural representation of a kind of mask plate that Fig. 1 provides for the embodiment of the present invention one.As shown in Figure 1, described mask plate 101 comprises substrate, and described substrate comprises alternatively non-transparent region 102, partial light permeability region 103 and transmission region 104.Described alternatively non-transparent region 102 is provided with alternatively non-transparent material layer, described partial light permeability region 103 is provided with partial light permeability material layer, described transmission region 104 does not arrange light screening material, and described transmission region 104 is arranged in described partial light permeability region 103.In patterning process, described transmission region 104 and partial light permeability region 103 are for the formation of grid line, grid and public electrode wire, and described transmission region 104 is also for the formation of the first via hole and the second via hole, thus gate mask plate and via hole mask plate can be realized share, reach the usage quantity reducing mask plate, reduce the object of product development and production cost.
In the present embodiment, the constituent material of described alternatively non-transparent material layer comprises metal material, and the constituent material of described partial light permeability material layer comprises metal oxide or resin.Preferably, described metal material comprises crome metal, and described metal oxide comprises chromium oxide.
In the mask plate that the present embodiment provides, described mask plate comprises substrate, described substrate comprises alternatively non-transparent region, partial light permeability region and transmission region, described alternatively non-transparent region is provided with alternatively non-transparent material layer, described partial light permeability region is provided with partial light permeability material layer, described transmission region does not arrange light screening material, and described transmission region is arranged in described partial light permeability region, or described alternatively non-transparent region is arranged in described partial light permeability region.The technical scheme that the present embodiment provides can realize gate mask plate and via hole mask plate shares, thus decreases the usage quantity of mask plate, reduces product development and production cost.
Embodiment two
The structural representation of a kind of mask plate that Fig. 2 provides for the embodiment of the present invention two.As shown in Figure 2, described mask plate 101 comprises substrate, and described substrate comprises alternatively non-transparent region 102, partial light permeability region 103 and transmission region 104.Described alternatively non-transparent region 102 is provided with alternatively non-transparent material layer, described partial light permeability region 103 is provided with partial light permeability material layer, described transmission region 104 does not arrange light screening material, and described alternatively non-transparent region 102 is arranged in described partial light permeability region 103.In patterning process, described alternatively non-transparent region 102 and partial light permeability region 103 are for the formation of grid line, grid and public electrode wire, and described alternatively non-transparent region 102 is also for the formation of the first via hole and the second via hole, thus gate mask plate and via hole mask plate can be realized share, reach the usage quantity reducing mask plate, reduce the object of product development and production cost.
In the present embodiment, the constituent material of described alternatively non-transparent material layer comprises metal material, and the constituent material of described partial light permeability material layer comprises metal oxide or resin.Preferably, described metal material comprises crome metal, and described metal oxide comprises chromium oxide.
In the mask plate that the present embodiment provides, described mask plate comprises substrate, described substrate comprises alternatively non-transparent region, partial light permeability region and transmission region, described alternatively non-transparent region is provided with alternatively non-transparent material layer, described partial light permeability region is provided with partial light permeability material layer, described transmission region does not arrange light screening material, and described transmission region is arranged in described partial light permeability region, or described alternatively non-transparent region is arranged in described partial light permeability region.The technical scheme that the present embodiment provides can realize gate mask plate and via hole mask plate shares, thus decreases the usage quantity of mask plate, reduces product development and production cost.
Embodiment three
The preparation process of the present embodiment array substrate is described in detail as follows.It should be noted that, the array base palte described in the present embodiment is TN pattern, but the array base palte of other pattern, and such as, the preparation method of the array base palte of ADS pattern and VA pattern also belongs to protection scope of the present invention.
The process flow diagram of the preparation method of a kind of array base palte that Fig. 3 provides for the embodiment of the present invention three.As shown in Figure 3, described preparation method comprises:
Step 3001, on substrate, form grid metallic film.
Step 3002, employing mask plate form grid line and grid by patterning processes.
In the present embodiment, the mask plate that described mask plate adopts above-described embodiment one to provide, particular content can refer to the description in above-described embodiment one, repeats no more herein.
Fig. 4 a ~ Fig. 4 c is the schematic diagram that embodiment three forms grid and public electrode wire.As shown in Fig. 4 a ~ Fig. 4 c, substrate is formed grid metallic film 105, described grid metallic film 105 applies negative photoresist 106, described mask plate 101 pairs of negative photoresists 106 are adopted to carry out exposure imaging to form the complete reserve area of negative photoresist, negative photoresist part reserve area and negative photoresist remove region completely, the complete reserve area of described negative photoresist and negative photoresist part reserve area correspond to and form grid line, the graphics field of grid 108 and public electrode wire 107, described negative photoresist removes region corresponding to other region outside described graphics field, etch to form grid line to described grid metallic film 105, grid 108 and public electrode wire 107, finally peel off remaining negative photoresist 106.Optionally, described substrate is quartz base plate.
Step 3003, form gate insulation layer, active layer film and source and drain metallic film successively.
Step 3004, be formed with active layer, source electrode and drain electrode by patterning processes.
In the present embodiment, on described grid line, grid 108 and public electrode wire 107, form gate insulation layer, active layer film and source and drain metallic film successively, be formed with active layer 201, source electrode 202 and drain electrode 203 by patterning processes.
Step 3005, formation passivation layer, adopt described mask plate to form the first via hole by patterning processes in the corresponding described drain region of described passivation layer.
In the present embodiment, the described mask plate of described employing while the corresponding described drain region of described passivation layer forms the first via hole, forms second via hole at described gate insulation layer and the corresponding described public electrode wire region of passivation layer by patterning processes.Fig. 5 a ~ Fig. 5 c is the schematic diagram that embodiment three forms via hole.As shown in Fig. 5 a ~ Fig. 5 c, passivation layer 204 is formed on described source electrode 202 and drain electrode 203, described passivation layer 204 applies positive photoresist 205, described mask plate 101 pairs of positive photoresists 205 are adopted to carry out exposure imaging to form the complete reserve area of positive photoresist, positive photoresist part reserve area and positive photoresist remove region completely, the graphics field that region corresponds to formation first via hole and the second via hole 206 removed by described positive photoresist, the complete reserve area of described positive photoresist and positive photoresist part reserve area correspond to other region outside described graphics field, etch to form the first via hole and the second via hole 206 to described passivation layer 204 and gate insulation layer 109, finally peel off remaining positive photoresist 205.
Step 3006, formation transparent conductive film.
Step 3007, form pixel electrode by patterning processes, described pixel electrode is connected with described drain electrode by described first via hole.
In the present embodiment, described passivation layer forms transparent conductive film, form pixel electrode and public electrode by patterning processes, described pixel electrode is connected with described drain electrode by described first via hole, and described public electrode is connected with described public electrode wire by described second via hole.
In the preparation method of the array base palte that the present embodiment provides, described mask plate comprises substrate, described substrate comprises alternatively non-transparent region, partial light permeability region and transmission region, described alternatively non-transparent region is provided with alternatively non-transparent material layer, described partial light permeability region is provided with partial light permeability material layer, described transmission region does not arrange light screening material, and described transmission region is arranged in described partial light permeability region, or described alternatively non-transparent region is arranged in described partial light permeability region.The mask plate that the present embodiment provides can realize gate mask plate and via hole mask plate shares, thus decreases the usage quantity of mask plate, reduces product development and production cost.
Embodiment four
The preparation process of the present embodiment array substrate is described in detail as follows.It should be noted that, the array base palte described in the present embodiment is TN pattern, but the array base palte of other pattern, and such as, the preparation method of the array base palte of ADS pattern and VA pattern also belongs to protection scope of the present invention.
The present embodiment provides a kind of preparation method of array base palte.See Fig. 3, described preparation method comprises:
Step 3001, on substrate, form grid metallic film.
Step 3002, employing mask plate form grid line and grid by patterning processes.
In the present embodiment, the mask plate that described mask plate adopts above-described embodiment two to provide, particular content can refer to the description in above-described embodiment two, repeats no more herein.
The schematic diagram of a kind of exposure technology that Fig. 6 provides for the embodiment of the present invention four.See Fig. 6, Fig. 4 b and Fig. 4 c, substrate is formed grid metallic film 105, described grid metallic film 105 applies positive photoresist 205, described mask plate 101 pairs of positive photoresists 205 are adopted to carry out exposure imaging to form the complete reserve area of positive photoresist, positive photoresist part reserve area and positive photoresist remove region completely, the complete reserve area of described positive photoresist and positive photoresist part reserve area correspond to and form grid line, the graphics field of grid 108 and public electrode wire 107, described positive photoresist removes region corresponding to other region outside described graphics field, etch to form grid line to described grid metallic film 105, grid 108 and public electrode wire 107, finally peel off remaining positive photoresist 205.
Step 3003, form gate insulation layer, active layer film and source and drain metallic film successively.
Step 3004, be formed with active layer, source electrode and drain electrode by patterning processes.
In the present embodiment, on described grid line, grid 108 and public electrode wire 107, form gate insulation layer, active layer film and source and drain metallic film successively, be formed with active layer 201, source electrode 202 and drain electrode 203 by patterning processes.
Step 3005, formation passivation layer, adopt described mask plate to form the first via hole by patterning processes in the corresponding described drain region of described passivation layer.
In the present embodiment, the described mask plate of described employing while the corresponding described drain region of described passivation layer forms the first via hole, forms second via hole at described gate insulation layer and the corresponding described public electrode wire region of passivation layer by patterning processes.The schematic diagram of the another kind of exposure technology that Fig. 7 provides for the embodiment of the present invention four.See Fig. 7, Fig. 5 b and Fig. 5 c, passivation layer 204 is formed on described source electrode 202 and drain electrode 203, described passivation layer 204 applies negative photoresist 106, described mask plate 101 pairs of negative photoresists 106 are adopted to carry out exposure imaging to form the complete reserve area of negative photoresist, negative photoresist part reserve area and negative photoresist remove region completely, described negative photoresist removes the graphics field that region corresponds to formation first via hole and the second via hole 206, the complete reserve area of described negative photoresist and negative photoresist part reserve area correspond to other region outside described graphics field, etch to form the first via hole and the second via hole 206 to described passivation layer 204 and gate insulation layer 109, finally peel off remaining negative photoresist 106.
Step 3006, formation transparent conductive film.
Step 3007, form pixel electrode by patterning processes, described pixel electrode is connected with described drain electrode by described first via hole.
In the present embodiment, described passivation layer forms transparent conductive film, form pixel electrode and public electrode by patterning processes, described pixel electrode is connected with described drain electrode by described first via hole, and described public electrode is connected with described public electrode wire by described second via hole.
In the preparation method of the array base palte that the present embodiment provides, described mask plate comprises substrate, described substrate comprises alternatively non-transparent region, partial light permeability region and transmission region, described alternatively non-transparent region is provided with alternatively non-transparent material layer, described partial light permeability region is provided with partial light permeability material layer, described transmission region does not arrange light screening material, and described transmission region is arranged in described partial light permeability region, or described alternatively non-transparent region is arranged in described partial light permeability region.The mask plate that the present embodiment provides can realize gate mask plate and via hole mask plate shares, thus decreases the usage quantity of mask plate, reduces product development and production cost.
Embodiment five
The preparation process of the present embodiment to display panel is described in detail as follows.It should be noted that, the display panel described in the present embodiment is TN pattern, but the display panel of other pattern, and such as, the preparation method of the display panel of ADS pattern and VA pattern also belongs to protection scope of the present invention.
Present embodiments provide a kind of preparation method of display panel, comprise the preparation method of the array base palte that above-described embodiment three or embodiment four provide, particular content can refer to the description of above-described embodiment three or embodiment four, repeats no more herein.
In the preparation method of the display panel that the present embodiment provides, described mask plate comprises substrate, described substrate comprises alternatively non-transparent region, partial light permeability region and transmission region, described alternatively non-transparent region is provided with alternatively non-transparent material layer, described partial light permeability region is provided with partial light permeability material layer, described transmission region does not arrange light screening material, and described transmission region is arranged in described partial light permeability region, or described alternatively non-transparent region is arranged in described partial light permeability region.The mask plate that the present embodiment provides can realize gate mask plate and via hole mask plate shares, thus decreases the usage quantity of mask plate, reduces product development and production cost.
Be understandable that, the illustrative embodiments that above embodiment is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (9)
1. a mask plate, it is characterized in that, comprise substrate, described substrate comprises alternatively non-transparent region, partial light permeability region and transmission region, described alternatively non-transparent region is provided with alternatively non-transparent material layer, and described partial light permeability region is provided with partial light permeability material layer, and described transmission region does not arrange light screening material, described transmission region is arranged in described partial light permeability region, or described alternatively non-transparent region is arranged in described partial light permeability region.
2. mask plate according to claim 1, it is characterized in that, when described transmission region is arranged in described partial light permeability region, described transmission region and partial light permeability region are for the formation of grid line, grid and public electrode wire, and described transmission region is also for the formation of the first via hole and the second via hole; Or
When described alternatively non-transparent region is arranged in described partial light permeability region, described alternatively non-transparent region and partial light permeability region are for the formation of grid line, grid and public electrode wire, and described alternatively non-transparent region is also for the formation of the first via hole and the second via hole.
3. mask plate according to claim 1, is characterized in that, the constituent material of described alternatively non-transparent material layer comprises metal material, and the constituent material of described partial light permeability material layer comprises metal oxide or resin.
4. mask plate according to claim 3, is characterized in that, described metal material comprises crome metal, and described metal oxide comprises chromium oxide.
5. a preparation method for array base palte, is characterized in that, comprising:
Substrate is formed grid metallic film;
Adopt mask plate to form grid line and grid by patterning processes, described mask plate comprises the arbitrary described mask plate of claim 1-4;
Form gate insulation layer, active layer film and source and drain metallic film successively;
Active layer, source electrode and drain electrode is formed by patterning processes;
Form passivation layer, adopt described mask plate to form the first via hole by patterning processes in the corresponding described drain region of described passivation layer;
Form transparent conductive film;
Form pixel electrode by patterning processes, described pixel electrode is connected with described drain electrode by described first via hole.
6. the preparation method of array base palte according to claim 5, is characterized in that, described employing mask plate forms public electrode wire while forming grid line and grid by patterning processes;
The described mask plate of described employing while the corresponding described drain region of described passivation layer forms the first via hole, forms second via hole at described gate insulation layer and the corresponding described public electrode wire region of passivation layer by patterning processes;
Described by while patterning processes formation pixel electrode, form public electrode, described public electrode is connected with described public electrode wire by described second via hole.
7. the preparation method of array base palte according to claim 6, is characterized in that, while described employing mask plate forms grid line and grid by patterning processes, the step forming public electrode wire comprises:
Described grid metallic film applies negative photoresist, adopt described mask plate to carry out exposure imaging to negative photoresist and remove region completely to form the complete reserve area of negative photoresist, negative photoresist part reserve area and negative photoresist, the complete reserve area of described negative photoresist and negative photoresist part reserve area correspond to the graphics field forming grid line, grid and public electrode wire, and described negative photoresist removes region completely corresponding to other region outside described graphics field;
Etch to form grid line, grid and public electrode wire to described grid metallic film;
Peel off remaining negative photoresist;
The described mask plate of described employing is by patterning processes while the corresponding described drain region of described passivation layer forms the first via hole, and the step forming the second via hole at described gate insulation layer and the corresponding described public electrode wire region of passivation layer comprises:
Described passivation layer applies positive photoresist, adopt described mask plate to carry out exposure imaging to positive photoresist and remove region completely to form the complete reserve area of positive photoresist, positive photoresist part reserve area and positive photoresist, the graphics field that region corresponds to formation first via hole and the second via hole removed by described positive photoresist, and the complete reserve area of described positive photoresist and positive photoresist part reserve area correspond to other region outside described graphics field;
Etch to form the first via hole and the second via hole to described passivation layer and gate insulation layer;
Peel off remaining positive photoresist.
8. the preparation method of array base palte according to claim 6, is characterized in that, while described employing mask plate forms grid line and grid by patterning processes, the step forming public electrode wire comprises:
Described grid metallic film applies positive photoresist, adopt described mask plate to carry out exposure imaging to positive photoresist and remove region completely to form the complete reserve area of positive photoresist, positive photoresist part reserve area and positive photoresist, the complete reserve area of described positive photoresist and positive photoresist part reserve area correspond to the graphics field forming grid line, grid and public electrode wire, and described positive photoresist removes region corresponding to other region outside described graphics field;
Etch to form grid line, grid and public electrode wire to described grid metallic film;
Peel off remaining positive photoresist;
The described mask plate of described employing is by patterning processes while the corresponding described drain region of described passivation layer forms the first via hole, and the step forming the second via hole at described gate insulation layer and the corresponding described public electrode wire region of passivation layer comprises:
Described passivation layer applies negative photoresist, adopt described mask plate to carry out exposure imaging to negative photoresist and remove region completely to form the complete reserve area of negative photoresist, negative photoresist part reserve area and negative photoresist, described negative photoresist removes the graphics field that region corresponds to formation first via hole and the second via hole, and the complete reserve area of described negative photoresist and negative photoresist part reserve area correspond to other region outside described graphics field;
Etch to form the first via hole and the second via hole to described passivation layer and gate insulation layer;
Peel off remaining negative photoresist.
9. a preparation method for display panel, is characterized in that, comprises the preparation method of the arbitrary described array base palte of claim 5-8.
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