CN110739317A - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
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- CN110739317A CN110739317A CN201911174172.XA CN201911174172A CN110739317A CN 110739317 A CN110739317 A CN 110739317A CN 201911174172 A CN201911174172 A CN 201911174172A CN 110739317 A CN110739317 A CN 110739317A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The embodiment of the invention provides array substrates and a preparation method thereof, and a display panel, which can reduce the risk of an open circuit of a second metal layer or a short circuit of a 0 th metal layer and a second metal layer in an overlapping area of a metal layer and the second metal layer, and ensure the yield of the array substrate, wherein the array substrate comprises a substrate, a 1 th metal layer, a 2 th insulating layer and a second metal layer which are sequentially stacked on the substrate, a 3 rd metal layer comprises at least th signal lines, the second metal layer comprises at least second signal lines, a th signal line crosses the second signal line, the th signal line is close to the side of the substrate , a groove is arranged in an overlapping area of the th signal line and the second signal line, and a th signal line overlapping part of the second signal line is positioned in the groove.
Description
Technical Field
The invention relates to the field of display, in particular to an array substrate, a preparation method of the array substrate and a display panel.
Background
At present, a Thin Film Transistor (TFT) is a main driving element of a liquid crystal display panel and a self-luminous display device such as an Organic Light-Emitting Diode (OLED) display panel, and during a process of manufacturing the TFT, an overlapping region between an th signal line and a second signal line crossing each other may be broken or short-circuited due to a process, so that the display panel may not operate normally, and a yield of the display panel may be reduced.
Disclosure of Invention
The embodiment of the invention provides array substrates, a preparation method thereof and a display panel, which can reduce the risk that a second metal layer is broken or a metal layer and a second metal layer are short-circuited in an overlapping area of a metal layer and the second metal layer, and ensure the yield of the array substrates.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
, the embodiment of the invention provides array substrates, which comprise a substrate, a th metal layer, a th insulating layer and a second metal layer, wherein the th metal layer, the th insulating layer and the second metal layer are sequentially stacked on the substrate.
The th metal layer includes at least th signal lines, the second metal layer includes at least second signal lines, and the th signal lines cross the second signal lines.
A groove is arranged at the side of the signal line close to the substrate and at the overlapping area of the signal line and the second signal line, and the part of the signal line, which overlaps the second signal line, is positioned in the groove.
Optionally, the array substrate further includes a buffer layer disposed on the th metal layer near the substrate side, and the buffer layer includes the groove.
Alternatively, the recess is disposed on the substrate.
Optionally, at least of the signal lines include a plurality of gate lines, and at least of the second signal lines include a plurality of data lines.
Optionally, in a case where the groove is disposed on the buffer layer, an upper surface of a portion of the th signal line located in the groove is flush with an upper surface of the buffer layer.
Optionally, the array substrate further includes at least thin film transistors disposed in each sub-pixel region, and each thin film transistor includes an active pattern, a th gate insulation pattern, a gate, a source, and a drain sequentially disposed on the substrate.
The gate and the th signal line are in the same layer, and the source and the drain are in the same layer as the second signal line.
The array substrate further comprises a shading pattern arranged between the substrate and the buffer layer.
In each sub-pixel region, an orthographic projection of the light shielding pattern on the substrate covers an orthographic projection of at least active patterns of the thin film transistors on the substrate.
According to the array substrate provided by the embodiment of the invention, the signal line is close to the substrate side, the groove is arranged in the overlapped area of the 0 signal line and the second signal line, and the overlapped part of the 1 signal line and the second signal line is positioned in the groove, so 2 is used, when the insulating layer covering the signal line is manufactured after the signal line is manufactured, the gradient of the side surface of the signal line can be reduced, and the insulating layer directly covers the signal line under the condition of smaller climbing gradient, so that the risk of breakage of the insulating layer can be reduced, the risk of disconnection or sharp point of the second signal line in the overlapped area of the signal line is ensured when the second signal line is formed subsequently, and the yield of the array substrate is ensured.
In another aspect, embodiments of the present invention provide kinds of display panels, including the array substrate described above, where the display panel is a liquid crystal display panel or a self-luminous display panel.
In another aspect, the present invention provides a methods for preparing an array substrate, including:
a buffer layer is formed on a substrate, the buffer layer including a plurality of grooves.
An th metal layer, a th insulating layer and a second metal layer are sequentially formed on the buffer layer, the th metal layer comprises at least signal lines, the second metal layer comprises at least second signal lines, and the th signal lines are intersected with the second signal lines, wherein the part, overlapped with the second signal lines, of the th signal line is positioned in grooves.
Optionally, at least of the signal lines include a plurality of gate lines, and at least of the second signal lines include a plurality of data lines.
After the buffer layer is formed, the method for preparing the array substrate further includes forming at least thin film transistors in each subpixel region.
The thin film transistor comprises an active pattern, an th gate insulation pattern, a gate electrode, a source electrode and a drain electrode which are sequentially formed on the substrate.
Wherein the gate and the th signal line are formed in synchronization, and the source and the drain are formed in synchronization with the second signal line.
The th signal line is formed in synchronization with the th gate insulating pattern.
Optionally, the forming of the buffer layer, the active pattern, the th gate insulation pattern, the th metal layer includes:
a buffer film is formed on the substrate, and an th photoresist film is formed.
And exposing the th photoresist film by using a half-tone mask plate to obtain a th photoresist complete remaining part, a th photoresist half remaining part and a th photoresist complete removing part, wherein the th photoresist complete removing part corresponds to a region where the groove is to be formed.
And removing the th photoresist complete reserved part and the th photoresist half reserved part.
Forming the active pattern.
A gate insulating film and an th metal film are sequentially formed, and a second photoresist film is formed on the th metal film.
And exposing the second photoresist film by using the halftone mask plate to obtain a second photoresist complete reserved part, a second photoresist semi-reserved part and a second photoresist complete removed part, wherein the second photoresist complete reserved part and the second photoresist semi-reserved part correspond to a region of the gate insulating layer to be formed, and the second photoresist film and the photoresist film are respectively made of positive photoresist and negative photoresist or negative photoresist and positive photoresist.
And sequentially etching the th metal film and the gate insulation film to obtain the th metal layer including the th signal line and the gate and the th gate insulation pattern.
Optionally, sequentially etching the th metal film and the gate insulating film to obtain the th metal layer and the th gate insulating pattern, including:
and carrying out wet etching on the th metal film to obtain the th metal layer.
And carrying out dry etching on the gate insulating film to obtain the th gate insulating pattern.
Optionally, before forming the buffer layer, the method further includes forming a light-shielding layer.
In each sub-pixel region, the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of at least active patterns of the thin film transistors on the substrate.
The embodiment of the invention provides a preparation method of array substrates, which is characterized in that a groove is manufactured before a metal layer and a second metal layer are manufactured, so that 0 is used, when a insulating layer covering a th signal line is manufactured after a th signal line is manufactured, the gradient of the side surface of the th signal line can be reduced, the insulating layer directly covers the th signal line under the condition of smaller climbing gradient, and therefore, the risk that the insulating layer is broken is reduced, the risk that the second signal line is broken or sharp points are generated in the overlapped area of the second signal line and the th signal line when the second signal line is formed subsequently is ensured, and the yield of the array substrates is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of lcd panels according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of electroluminescent display panels according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of array substrates applied to a liquid crystal display panel according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of array substrates applied to an electroluminescent display panel according to an embodiment of the present invention;
fig. 5 is a schematic structural view of an array substrate in the related art;
FIG. 6 is a schematic structural diagram of the region S in FIG. 4 according to an embodiment of the present invention;
FIG. 7 is a schematic view of of FIG. 6 taken along AA' according to an embodiment of the present invention;
FIG. 8 is another schematic cross-sectional views along AA' of FIG. 6 according to an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view along AA' of another of FIG. 6 according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of another S regions according to an embodiment of the present invention;
FIG. 11 is a schematic cross-sectional view along BB' of samples of FIG. 10 according to an embodiment of the present invention;
FIG. 12 is another schematic cross-sectional views along BB' of FIG. 10 according to an embodiment of the present invention;
fig. 13 is a schematic flow chart illustrating a method for manufacturing array substrates according to an embodiment of the present invention;
FIG. 14a is a schematic diagram illustrating a process of preparing a buffer film and a th photoresist film in a method of preparing array substrates according to an embodiment of the present invention;
FIG. 14b is a schematic view showing the process of exposing and developing th photoresist in the preparation method of array substrates according to the embodiment of the present invention;
fig. 14c is a schematic diagram illustrating a process of etching a groove in the preparation method of array substrates according to the embodiment of the present invention;
fig. 14d is a schematic view illustrating a process of forming active patterns in the method of manufacturing array substrates according to an embodiment of the present invention;
fig. 14e is a schematic view illustrating a process of preparing a gate insulating film, a th metal film and a second photoresist in the method of preparing array substrates according to an embodiment of the present invention;
fig. 14f is a schematic process diagram of exposing and developing a second photoresist in the preparation method of array substrates according to the embodiment of the present invention;
fig. 14g is a schematic diagram illustrating a process of etching the gate insulating film and the th metal film in the preparation method of array substrates according to an embodiment of the present invention;
fig. 15 is a schematic flow chart illustrating another preparation method of array substrates according to an embodiment of the present invention.
Reference numerals:
1-liquid crystal display panel, 3-electroluminescent display panel, 10-substrate, 12-counter substrate, 13-liquid crystal layer, 14-upper polarizer, 15-lower polarizer, 43-buffer layer, 61- gate insulating pattern, 62-active pattern, 63-light shielding pattern, 51- insulating layer, 70-halftone mask, 70 a-transparent portion, 70 b-semi-transparent portion, 70 c-opaque portion, 110- substrate, 111-thin film transistor, 112-pixel electrode, 113-common electrode, 120-second substrate, 121-color filter layer, 122-black matrix pattern, 310-third substrate, 311- electrode, 312-light emitting functional layer, 313-second electrode, 314-pixel defining layer, 315-flat layer, 411- signal line, 412- metal film, 430-second signal line, 430-groove, 433-second photoresist film, 3-gate insulating film, 1-gate line, 10-substrate, 12-counter substrate, 13-liquid crystal display panel, 13-liquid crystal layer, 14-upper polarizer, 15-lower polarizer, 43-bottom insulating pattern, 61-gate insulating pattern, 111-thin film, 310-gate line, 310-fourth photoresist film, 510-fifth photoresist film.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only partial embodiments of of the present invention, rather than all embodiments.
Embodiments of the present invention provide Display panels, which may be a Liquid Crystal Display (LCD) panel or a self-luminous Display panel, the self-luminous Display panel includes of an electroluminescent Display panel and a photoluminescent Display panel, wherein the electroluminescent Display panel may be an Organic Light-Emitting Diode (OLED) Display panel or a Quantum Dot electroluminescent (QLED) Display panel, and the photoluminescent Display panel may be a Quantum Dot photoluminescent Display panel.
When the display panel is a liquid crystal display panel, as shown in fig. 1, the main structure of the liquid crystal display panel 1 includes an array substrate 11, a counter substrate 12, and a liquid crystal layer 13 disposed between the array substrate 11 and the counter substrate 12.
In embodiments, as shown in fig. 1, the array substrate 11 includes a thin film transistor 111, a pixel electrode 112, and a common electrode 113 disposed on a th substrate 110, wherein the pixel electrode 112 and the common electrode 113 may be disposed on the same layer, in which case, the pixel electrode 112 and the common electrode 113 are both comb-teeth structures including a plurality of strip-shaped sub-electrodes, the pixel electrode 112 and the common electrode 113 may also be disposed on different layers, in which case, as shown in fig. 1, a insulating layer 114 is disposed between the pixel electrode 112 and the common electrode 113, and in which case, as shown in fig. 1, a second insulating layer 115 is disposed between the common electrode 113 and the thin film transistor 111.
In still other embodiments, the common electrode 113 is disposed on the opposing substrate 12.
As shown in fig. 1, the opposite substrate 12 includes a second substrate 120, and a Color filter layer 121 disposed on the second substrate 120, in which case, the opposite substrate 12 may also be referred to as a Color Filter (CF) substrate, the Color filter layer 121 includes at least th Color filter unit, a second Color filter unit, and a third Color filter unit, and the th Color filter unit, the second Color filter unit, and the third Color filter unit are correspondingly located in sub-pixels, wherein the th Color, the second Color, and the third Color are three primary colors, such as red, green, and blue, the opposite substrate 12 further includes a black matrix pattern 122 disposed on the second substrate 120, and the black matrix pattern 122 is used for spacing the th Color filter unit, the second Color filter unit, and the third Color filter unit.
As shown in fig. 1, the liquid crystal display panel 1 further includes an upper polarizer 14 disposed on the side of the counter substrate 12 away from the liquid crystal layer 13 and a lower polarizer 15 disposed on the side of the array substrate 11 away from the liquid crystal layer 13 .
For the self-luminous display panel, the self-luminous display panel is taken as the electroluminescent display panel 3. as shown in fig. 2, the electroluminescent display panel includes an array substrate 11, the array substrate 11 includes a third substrate 310 and a pixel driving circuit disposed on the third substrate 310 and located in each sub-pixel, the pixel driving circuit includes a plurality of thin film transistors 111, and of the thin film transistors are driving transistors.
The light emitting device includes th electrode 311, light emitting function layer 312, and second electrode 313 for example, th electrode 311 is anode 311, second electrode 313 is cathode, anode 311 is electrically connected to pixel driving circuit through via hole on flat layer 315. opening regions of pixel defining layer 314 are disposed corresponding to each light emitting device .
The light emitting device may be kinds of a bottom emission type light emitting device, a top emission type light emitting device, and a double-sided emission type light emitting device.
In some embodiments , the light emitting functional layer 312 includes a light emitting layer in other embodiments , the light emitting functional layer 312 includes or more of an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), a Hole Transport Layer (HTL), and a Hole Injection Layer (HIL) in addition to the light emitting layer.
The structure of the photoluminescent display panel is similar to that of the electroluminescent display panel 3, and is not described in detail here.
Based on the above, the array substrate 11 is included in both the liquid crystal display panel and the electroluminescent display panel or the photoluminescent display panel, and the performance of the array substrate 11 has a great influence on the display effect of these display panels.
The embodiment of the invention provides array substrates 11, which can be used in the liquid crystal display panel 1 or the self-luminous display panel.
As shown in fig. 3 and 4, the array substrate 11 includes a substrate 10, an th metal layer, a th insulating layer 51 and a second metal layer sequentially stacked on the substrate 10, the th metal layer includes at least signal lines 411, the second metal layer includes at least second signal lines 422, and the signal lines 411 cross the second signal lines 422.
As shown in fig. 6 and 7, a groove 430 is provided at a region where the th signal line 411 is close to the substrate 10 side and the th signal line 411 overlaps the second signal line 422, and a portion of the th signal line 411 overlapping the second signal line 422 is located within the groove 430.
As shown in fig. 3, when the array substrate 11 is applied to the liquid crystal display panel 1, at least of the signal lines 411 may include a plurality of gate lines 4111, and at least of the second signal lines 422 may include a plurality of data lines 4221.
On this basis, the th metal layer may further include, for example, a gate electrode electrically connected to the gate line 4111 for constituting a thin film transistor, and the second metal layer may further include, for example, a source electrode and a drain electrode electrically connected to the data line 4221 and the pixel electrode, respectively, for constituting a thin film transistor, as will be apparent to those skilled in the art, the thin film transistor further includes an active pattern and a gate insulating layer (or th gate insulating pattern).
As shown in fig. 4, when the array substrate 11 is applied to the electroluminescent display panel 3, at least of the signal lines 411 may include a plurality of gate lines 4111, and at least of the second signal lines 422 may include a plurality of data lines 4221 and a plurality of power signal lines 4222. the gate lines 4111, the data lines 4221 and the power signal lines 4222 are electrically connected to a pixel driving circuit for providing signals to the pixel driving circuit.
Fig. 4 illustrates an example of a pixel driving circuit 3T1C in the array substrate 11, where T1 is a driving transistor, T2 is a switching transistor, T3 is a sensing transistor, a gate of T2 is electrically connected to a gate line 4111, a th pole of T2 is electrically connected to a data line 4221, a second pole of T2 is electrically connected to a gate of T1 through a th connection electrode, a th pole of T1 is electrically connected to a power signal line 4222, a second pole of T1 is electrically connected to a th pole of T3 through a second connection electrode, a gate of T3 is electrically connected to a gate line 4111 of a lower row, or a portion of the gate line 4111 serves as a gate of T3, and a second pole of T3 is electrically connected to a sensing signal line 4223, a th electrode 311 of a light emitting device may be electrically connected to a second pole of T1.
On this basis, the th metal layer may further include, for example, gate electrodes for constituting respective transistors such as T1, T2 and T3, and the second metal layer may further include, for example, source and drain electrodes for constituting respective transistors such as T1, T2 and T3.
In addition, the second signal line 422 may further include a plurality of sensing signal lines 4223, for example.
It should be noted that, in order to distinguish two poles of the transistor except for the gate, is directly described as , and is directly described as a second pole, for example, the pole of the above transistor may be the source, and the second pole may be the drain, or the pole of the transistor may be the drain, and the second pole is the source.
Optionally, the thickness of the th metal layer is 200-1000nm, and the thickness of the second metal layer is 200-1000 nm.
Optionally, the th metal layer and the second metal layer are made of or more metal materials selected from aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), and the like.
As shown in FIG. 5, in order to reduce the resistance of the th and second signal lines 411, 422, the th and second signal lines 411, 422 can be formed by using thicker metal material, so that after the 1 th metal layer including the 0 th signal line 411 is manufactured, when the th insulating layer 51 is manufactured, the th insulating layer 51 needs to climb on the side of the th signal line 411 to cover the th signal line 411. since the th insulating layer 51 at the climbing position is thinner, the th insulating layer 51 is easily broken, and thus, when the second metal layer including the second signal line 422 is formed later, the second signal line 422 is broken or pointed at the climbing position, and then the second signal line 422 is broken due to the breaking or pointed discharge due to the pointed discharge, the th insulating layer 51 breaks down, which causes the th and second signal lines 411 422 to be short-circuited.
According to the array substrate 11 provided by the embodiment of the invention, the signal line 411 is close to the substrate 10 side, the groove 430 is arranged in the overlapped area of the 0 signal line 411 and the second signal line 422, and the overlapped part of the 1 signal line 411 and the second signal line 422 is positioned in the groove 430, so 2 is used, when the insulating layer 51 covering the signal line 411 is manufactured after the signal line 411 is manufactured, the slope of the side surface of the signal line 411 can be reduced, and the insulating layer 51 directly covers the signal line 411 under the condition that the climbing slope is smaller, so that the risk of breaking the insulating layer 51 can be reduced, and the risk of breaking or tip breaking of the second signal line 422 in the overlapped area of the signal line 411 is ensured when the second signal line 422 is formed subsequently, thereby ensuring the yield of the array substrate 11.
Optionally, as shown in fig. 6-8 and 10-12, the array substrate further includes a buffer layer 43 disposed on the th metal layer near the substrate 10 , where the buffer layer 43 includes a groove 430, and the groove 430 is formed simultaneously when the buffer layer 43 is formed, so that the process is simple and easy to implement.
When the buffer layer 43 includes the grooves 430, the grooves 430 may penetrate the buffer layer 43 as shown in fig. 7 and 11, or the grooves 430 may not penetrate the buffer layer 43 as shown in fig. 8 and 12.
Alternatively, as shown in fig. 9, the groove 430 is provided on the substrate 10.
The cross-sectional shape of the groove 430 in a direction perpendicular to the substrate 10 is illustrated as an inverted trapezoid in fig. 7 to 12, but the embodiment of the present invention is not limited thereto, and the cross-sectional shape of the groove 430 may be, for example, a rectangle or other regular shape.
Alternatively, as shown in fig. 6-8 and 10-12, in the case where the recess 430 is provided in the buffer layer 43, the upper surface of the portion of the -th signal line 411 located in the recess 430 is flush with the upper surface of the buffer layer 43, wherein the upper surface of the buffer layer 43 refers to the surface of the buffer layer 43 away from the substrate 10.
By making the th signal line 411 in the groove 430 flush with the upper surface of the buffer layer 43, the th signal line 411 can be directly covered by the th insulating layer 51 without climbing when the th insulating layer 51 is manufactured subsequently, so that the th insulating layer 51 can be prevented from being broken, and when the second signal line 422 is formed subsequently, no open circuit or sharp point is generated in the overlapping area of the second signal line 422 and the th signal line 411, thereby ensuring the yield of the array substrate 11.
Optionally, as shown in fig. 10 to 12, the array substrate 11 further includes at least thin film transistors disposed in each sub-pixel region S, and each thin film transistor includes an active pattern 62, a th gate insulating pattern 61, a gate electrode, and source and drain electrodes sequentially disposed on the substrate 10.
The gate 64 and the signal line 411 are on the same layer and the source and the drain are on the same layer as the second signal line 422. that is, in this case, the metal layer includes the signal line 411 and the gate constituting each thin film transistor, and the second metal layer includes the second signal line 422 and the source and the drain constituting each thin film transistor.
On this basis, the array substrate 11 further includes a light-shielding pattern 63 disposed between the substrate 10 and the buffer layer 43, and an orthographic projection of the light-shielding pattern 63 on the substrate 10 covers an orthographic projection of the active patterns 62 of at least thin film transistors on the substrate 10, wherein the light-shielding pattern 63 may be electrically connected with of source and drain electrodes of the thin film transistors, for example.
Fig. 10 shows the display panel as an electroluminescent display panel, and the array substrate 11 includes three thin film transistors, that is, the pixel driving circuit in the array substrate 11 is 3T1C, and the three thin film transistors are respectively the driving transistor T1, the switching transistor T2, and the sensing transistor T3. Wherein the light blocking pattern 63 covers at least the active pattern 62 of the driving transistor T1. At this time, the light-shielding layer 63 is electrically connected to the source of the driving transistor T1.
By arranging the light-shielding layer 63, and because the orthographic projection of the light-shielding layer 63 on the substrate 10 covers the projection of the active patterns 62 of at least thin film transistors on the substrate 10, the light-shielding layer 63 can completely cover the active patterns 62 of at least thin film transistors, and the active patterns 62 covered by the light-shielding layer are prevented from being irradiated by light incident to the substrate 10 from the outside to influence the performance of the corresponding thin film transistors.
As shown in fig. 13, an embodiment of the present invention provides a method for preparing array substrates, including:
s10, as shown in fig. 14c, a buffer layer 43 is formed on the substrate 10, the buffer layer 43 including a plurality of grooves 430.
S11, as shown in FIG. 7 and FIG. 8, a metal layer, a insulation layer 51 and a second metal layer are sequentially formed on the buffer layer 43, wherein the metal layer comprises at least signal lines 411 of , the second metal layer comprises at least signal lines 422, the signal lines 411 cross the second signal lines 422, and the portions of any signal lines 411 which are overlapped with the second signal lines 422 are located in grooves 430.
The embodiment of the invention provides a preparation method of array substrates, which is characterized in that a groove 430 is made before a metal layer and a second metal layer are made, so that 0 is used, when a insulating layer 51 covering a signal line 411 is made after the signal line 411 is made, the slope of the side surface of the signal line 411 can be reduced, the insulating layer 51 directly covers the signal line 411 under the condition of smaller climbing slope, and therefore, the risk of breaking the insulating layer 51 is reduced, and when the second signal line 422 is formed subsequently, the risk of breaking or sharp-pointed ends of the second signal line 422 in the overlapped area of the signal line 411 is ensured, and the yield of the array substrates is ensured.
Optionally, at least of the signal lines 411 include a plurality of gate lines 4111, and at least of the second signal lines 422 include a plurality of data lines 4221.
Based on this, the method of manufacturing the array substrate further includes forming at least thin film transistors in each sub-pixel region S, the thin film transistors including an active pattern 62, a th gate insulating pattern 61, a gate electrode and source and drain electrodes sequentially formed on the substrate 10, wherein the gate electrode and the th signal line 411 are formed in synchronization, the source and drain electrodes are formed in synchronization with the second signal line 422, and the th signal line 411 is formed in synchronization with the th gate insulating pattern 61, after forming the buffer layer 43.
The gate 64 and the th signal line 411, i.e., the th metal layer includes the gate 64 and the th signal line 411 the source 65 and the drain 66 are formed in synchronization with the second signal line 422, i.e., the second metal layer includes the source 65 and the drain 66 and the second signal line 422.
In the case where the th metal layer includes the gate and the th signal line 411, and the th signal line 411 is formed in synchronization with the th gate insulating pattern 61, the second gate insulating pattern 67 of the same layer as the th gate insulating pattern 61 remains on the th signal line 411 side closer to the substrate 10 .
Thus, a portion of the th signal line 411 overlapping the second signal line 422 and the second gate insulating pattern 67 under the th signal line 411 are located within the groove 430.
Optionally, the forming of the buffer layer 43, the active pattern 62, the th gate insulation pattern 61, and the th metal layer includes:
s31, as shown in FIG. 14a, a buffer film 431 is formed on the substrate 10, and a th photoresist film 432 is formed.
S32, as shown in FIG. 14b, exposing the th photoresist film 432 by using a half-tone mask 70 to obtain a th photoresist complete remaining portion 432a, a th photoresist half remaining portion 432b and a th photoresist complete removing portion 432c, wherein the th photoresist complete removing portion 432c corresponds to a region where the groove 430 is to be formed.
S33, as shown in fig. 14c, the buffer film 431 is etched to obtain the buffer layer 43 including the groove 430, and the th photoresist full remaining portion 432a and the th photoresist half remaining portion 432b are removed.
S34, as shown in fig. 14d, the active pattern 62 is formed.
S35, as shown in fig. 14e, a gate insulating film 611 and a metal film 412 are sequentially formed, and a second photoresist film 433 is formed on the metal film 412.
S36, as shown in fig. 14f, the second photoresist film 433 is exposed by using the above halftone mask 70, so as to obtain a second photoresist complete-remaining portion 433c, a second photoresist half-remaining portion 433b, and a second photoresist complete-removal portion 433a, where the second photoresist complete-remaining portion 433c and the second photoresist half-remaining portion 433b correspond to a region of the gate insulating layer 61 to be formed.
The materials of the second photoresist film 433 and the th photoresist film 432 are respectively positive photoresist and negative photoresist, or negative photoresist and positive photoresist.
Referring to fig. 14b and 14f, the main principle of the halftone mask 70 is explained as follows:
referring to fig. 14b, the half-tone mask 70 can selectively expose and develop the photoresist by exposing the photoresist to light with different intensities in different regions. The halftone mask 70 includes a transparent portion 70a, a translucent portion 70b, and an opaque portion 70 c.
Taking the material of the th photoresist film 432 as a negative photoresist and the material of the second photoresist film 433 as a positive photoresist as an example, when the th photoresist film 432 is exposed, the th photoresist fully-remaining portion 432a may correspond to the transparent portion 70a of the halftone mask plate 70, the th photoresist fully-remaining portion 432b may correspond to the translucent portion 70b of the halftone mask plate 70, and the th photoresist fully-removed portion 432c corresponds to the opaque portion 70c of the halftone mask plate 70.
After the second photoresist film 433 is exposed, the second photoresist full remaining portion 433c may correspond to the opaque portion 70c of the half-tone mask plate 70, the second photoresist half remaining portion 432b may correspond to the semi-transparent portion 70b of the half-tone mask plate 70, and the second photoresist full removed portion 433a may correspond to the transparent portion 70a of the half-tone mask plate 70.
On this basis, since the materials of the second photoresist film 433 and the th photoresist film 432 are respectively a positive photoresist and a negative photoresist, or a negative photoresist and a positive photoresist, it can be known that, after the th photoresist film 432 is exposed, the th photoresist completely-removed portion 432c and the second photoresist completely-retained portion 433c after the subsequent exposure of the second photoresist film 433 correspond to the same region of the substrate 10, the th photoresist half-retained portion 432b and the second photoresist half-retained portion 433b correspond to the same region of the substrate 10, and the th photoresist completely-retained portion 432a and the second photoresist completely-removed portion 433a correspond to the same region of the substrate 10.
Based on this, since the th photoresist completely removed portion 432c corresponds to a region where the groove 430 is to be formed, and the second photoresist completely remaining portion 433c and the second photoresist half-remaining portion 433b correspond to a region where the th metal layer is to be formed, it can be known that the second photoresist half-remaining portion 433b corresponds to other regions except the groove 430 in the region where the th metal layer is to be formed.
S37, as shown in fig. 14g, the th metal film 412 and the gate insulating film 611 are sequentially etched to obtain a th metal layer and a gate insulating pattern 61.
Meanwhile, since the th photoresist semi-reserved part 432b and the second photoresist semi-reserved part 433b correspond to the same region of the substrate 10 and the other regions except the groove 430 in the region where the gate insulation pattern 61 is to be formed, when the buffer film 431 is etched to form the buffer layer, only the region of the buffer film 431 corresponding to the groove 430 is etched, the th photoresist semi-reserved part 432b is reserved in the region where the active pattern is formed subsequently, the buffer film 431 corresponding to the buffer film 431 is prevented from being etched, the region corresponding to the active pattern is prevented from being uneven, and polymer residues are formed during etching, so that the characteristic degradation of a thin film transistor manufactured subsequently is prevented.
In addition, the gate insulating pattern 61 and the th metal layer may be simultaneously formed using patterning processes, simplifying the manufacturing process.
Optionally, sequentially etching the th metal film 412 and the gate insulating film 611 to obtain a th metal layer and the gate insulating layer 61, including:
s371, carry on the wet etching to the th metal film 412, get the th metal layer.
And S372, carrying out dry etching on the gate insulating film 611 to obtain a gate insulating pattern 61.
The th metal film 412 is etched by wet etching, and the gate insulating film 611 is etched by dry etching, so that the boundary of the pattern of the th metal layer formed is recessed with respect to the boundary of the pattern of the corresponding gate insulating pattern 61, thereby preventing the th metal layer from contacting the active pattern 62.
Optionally, as shown in fig. 15, before forming the buffer layer 43, the method for preparing the array substrate further includes:
s01, forming a light-shielding layer 63 disposed between the substrate 10 and the buffer layer 43, wherein an orthographic projection of the light-shielding layer 63 on the substrate 10 covers an orthographic projection of at least active patterns 63 on the substrate 10 in each subpixel region, as shown in fig. 11 and 12.
By providing the light-shielding layer 63 and covering the projection of the active layer 62 on the substrate 10 due to the orthographic projection of the light-shielding layer 63 on the substrate 10, the light-shielding layer 63 can completely cover the active pattern 163, and the active layer 62 is prevented from being irradiated by light incident on the substrate 10 from the outside to affect the performance thereof. On this basis, by electrically connecting the light shielding layer 63 with the second metal layer, a stable voltage can be generated on the light shielding layer 63, so that the light shielding layer 63 can be prevented from being in a suspended state, and the working stability of the array substrate can be ensured.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
- The array substrate of species is characterized by comprising a substrate, a th metal layer, a th insulating layer and a second metal layer, wherein the th metal layer, the th insulating layer and the second metal layer are sequentially stacked on the substrate;the th metal layer includes at least th signal lines, the second metal layer includes at least second signal lines, the th signal lines intersect the second signal lines;a groove is arranged at the side of the signal line close to the substrate and at the overlapping area of the signal line and the second signal line, and the part of the signal line, which overlaps the second signal line, is positioned in the groove.
- 2. The array substrate of claim 1, further comprising a buffer layer disposed on the side of the metal layer close to the substrate , the buffer layer comprising the groove;alternatively, the first and second electrodes may be,the groove is arranged on the substrate.
- 3. The array substrate of claim 1 or 2, wherein at least of the signal lines comprise gate lines and at least of the second signal lines comprise data lines.
- 4. The array substrate of claim 2, wherein in a case that the groove is disposed on a buffer layer, an upper surface of a portion of the th signal line located in the groove is flush with an upper surface of the buffer layer.
- 5. The array substrate of claim 3, further comprising at least thin film transistors disposed in each sub-pixel region, the thin film transistors comprising an active pattern, a th gate insulating pattern, a gate electrode, and source and drain electrodes sequentially disposed on the substrate;the gate and the th signal line are in the same layer, and the source and the drain are in the same layer as the second signal line;the array substrate further comprises a shading pattern arranged between the substrate and the buffer layer;in each sub-pixel region, an orthographic projection of the light shielding pattern on the substrate covers an orthographic projection of at least active patterns of the thin film transistors on the substrate.
- 6, kinds of display panel, which is characterized by comprising the array substrate of any of claims 1-5, wherein the display panel is a liquid crystal display panel or a self-luminous display panel.
- The preparation method of the array substrate of 7, kinds, characterized by, including:forming a buffer layer on a substrate, the buffer layer including a plurality of grooves;an th metal layer, a th insulating layer and a second metal layer are sequentially formed on the buffer layer, the th metal layer comprises at least signal lines, the second metal layer comprises at least second signal lines, and the th signal lines are intersected with the second signal lines, wherein the part, overlapped with the second signal lines, of the th signal line is positioned in grooves.
- 8. The method of claim 7, wherein at least of the signal lines comprise gate lines and at least of the second signal lines comprise data lines;after the buffer layer is formed, the preparation method of the array substrate further comprises forming at least thin film transistors in each subpixel region;the thin film transistor comprises an active pattern, an th gate insulation pattern, a gate, a source electrode and a drain electrode which are sequentially formed on the substrate;wherein the gate and the th signal line are formed in synchronization, and the source and the drain are formed in synchronization with the second signal line;the th signal line is formed in synchronization with the th gate insulating pattern.
- 9. The method of claim 8, wherein forming the buffer layer, the active pattern, the gate insulation pattern, and the metal layer comprises:forming a buffer film on the substrate and forming an th photoresist film;exposing the th photoresist film by using a half-tone mask plate to obtain a th photoresist complete remaining part, a th photoresist half remaining part and a th photoresist complete removing part, wherein the th photoresist complete removing part corresponds to an area in which the groove is to be formed;etching the buffer film to obtain the groove, and removing the th photoresist complete reserved part and the th photoresist half reserved part;forming the active pattern;sequentially forming a gate insulating film and an th metal film, and forming a second photoresist film on the th metal film;exposing the second photoresist film by using the halftone mask plate to obtain a second photoresist complete reserved part, a second photoresist semi-reserved part and a second photoresist complete removed part, wherein the second photoresist complete reserved part and the second photoresist semi-reserved part correspond to a region of the gate insulation pattern to be formed, and the second photoresist film and the photoresist film are respectively made of positive photoresist and negative photoresist, or negative photoresist and positive photoresist;and sequentially etching the th metal film and the gate insulation film to obtain the th metal layer including the th signal line and the gate and the th gate insulation pattern.
- 10. The method of claim 9, wherein the etching the th metal film and the gate insulation film sequentially to obtain the th metal layer and the th gate insulation pattern comprises:wet etching is carried out on the th metal film to obtain the th metal layer;and carrying out dry etching on the gate insulating film to obtain the th gate insulating pattern.
- 11. The method for manufacturing an array substrate according to claim 8, wherein before forming the buffer layer, the method further comprises forming a light-shielding layer;in each sub-pixel region, the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of at least active patterns of the thin film transistors on the substrate.
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