CN104932152B - The manufacturing method of liquid crystal display panel and liquid crystal display panel - Google Patents
The manufacturing method of liquid crystal display panel and liquid crystal display panel Download PDFInfo
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- CN104932152B CN104932152B CN201510349216.3A CN201510349216A CN104932152B CN 104932152 B CN104932152 B CN 104932152B CN 201510349216 A CN201510349216 A CN 201510349216A CN 104932152 B CN104932152 B CN 104932152B
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- liquid crystal
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Abstract
The present invention provides a kind of liquid crystal display panel and its manufacturing method, the liquid crystal display panel includes array substrate and color membrane substrates, and the array substrate includes data line, scan line, thin film transistor (TFT) and open region.The array substrate further includes patterning flatness layer, it is formed on the data line, the scan line and the thin film transistor (TFT), and expose the open region, the patterning flatness layer being wherein located in the scan line forms a columnar projections, the columnar projections are supported between the array substrate and the color membrane substrates, without additionally making introns, to save the photosensitive type introns processing procedure on color membrane substrates.
Description
【Technical field】
The present invention relates to field of liquid crystal display, more particularly to the manufacturer of a kind of liquid crystal display panel and liquid crystal display panel
Method.
【Background technology】
Traditional liquid crystal display panel includes colored filter (CF, Color filter) substrate, array substrate and liquid
It is brilliant.The color membrane substrates include the first glass substrate, black matrix (BM, Black Matrix) layer, colored pattern layers and protective layer
(OC, Over Coat) layer, it is one which, which is cascading,
Body；Array substrate includes the second glass substrate, grid line layer, insulating layer, semiconductor layer, metal layer and passivation layer, second glass
Glass substrate, grid line layer, insulating layer, semiconductor layer, metal layer and passivation layer are cascading and are integrated.
It is supported with introns (Spacer) between the color membrane substrates and array substrate of traditional liquid crystal display panel.
Color membrane substrates and array substrate are stacked together, and due to introns be placed between and there are the gap of fixed range,
Liquid crystal is placed in the gap.Generally in low temperature polycrystalline silicon (LTPS, Low Temperature Poly-silicon) film crystal
In pipe liquid crystal display (i.e. LTPS-TFT LCD), introns are reached using photosensitive type introns (Photo Spacer, PS)
At.For in the product of small-medium size, photosensitive type introns are formed on color membrane substrates, specific color filter producing process is black
It, will be between photosensitive type by using the photoetching process of photomask (Photomask) after the completion of matrix layer, colored pattern layers and protective layer
Every the specific region of sub- formation on the protection layer.
However, make photosensitive type introns be formed in color membrane substrates needed compared to the processing procedure for making traditional color membrane substrates it is more
Primary high-cost photoetching process, is unfavorable for the reduction of cost.
【Invention content】
It is an object of the present invention to provide a kind of liquid crystal display panel, the flatness layer in array substrate forms one
Columnar projections are as introns, to save the photosensitive type introns processing procedure on color membrane substrates.
It is another object of the present invention to provide a kind of manufacturing methods of liquid crystal display panel, can pass through halftoning light
Carving technology through single exposure can be fabricated to flatness layer and as the columnar projections of introns, to save on color membrane substrates
Photosensitive type introns processing procedure.
To solve the above problems, the preferred embodiment of the present invention provides a kind of liquid crystal display panel comprising including battle array
Row substrate and color membrane substrates, the array substrate include data line, scan line and thin film transistor (TFT), the data line and described are swept
It retouches line and defines open region.The array substrate further includes patterning flatness layer, is formed in the data line, the scan line
And on the thin film transistor (TFT), and the open region is exposed, wherein the patterning flatness layer in the scan line
A columnar projections are formed, the columnar projections are supported between the array substrate and the color membrane substrates.
In a preferred embodiment of the invention, the patterning flatness layer for forming the columnar projections has one first thickness
Degree, being located at the patterning flatness layer on the data line has a second thickness, and the first thickness is more than described the
Two thickness.Preferably, the first thickness is between 2.8 to 3.2 microns, the second thickness between 2.1 to 2.6 microns it
Between.In addition, having a thickness of liquid crystal box between the array substrate and the color membrane substrates, the first thickness is equal to the liquid
Brilliant box thickness.
In a preferred embodiment of the invention, the thin film transistor (TFT) is low-temperature polysilicon film transistor, and the liquid crystal
Display panel is fringe field switching mode display panel.Preferably, the array substrate includes underlay substrate and in the scanning
Buffer layer, semiconductor layer, gate insulating layer, barrier metal layer, the interlayer being sequentially formed on line position on the underlay substrate are situated between
Electric layer, the patterning flatness layer, common electrode layer, passivation layer and pixel electrode layer.
Similarly, to solve the above problems, another preferred embodiment of the present invention provides a kind of liquid crystal display panel
Manufacturing method comprising：There is provided include data line, scan line and thin film transistor (TFT) array substrate, the data line and described
Scan line defines open region；Coating flat layer is in the array substrate；It is described flat using halftoning photoetching process patterning
Smooth layer, to form the figure for being located on the data line, the scan line and the thin film transistor (TFT) and exposing the open region
Case flatness layer, wherein the patterning flatness layer in the scan line forms a columnar projections；And in conjunction with described
Array substrate and color membrane substrates so that the columnar projections are supported between the array substrate and the color membrane substrates.
In a preferred embodiment of the invention, the patterning flatness layer for forming the columnar projections has one first thickness
Degree, being located at the patterning flatness layer on the data line has a second thickness, and the first thickness is more than described the
Two thickness.Preferably, the first thickness is between 2.8 to 3.2 microns, the second thickness between 2.1 to 2.6 microns it
Between.
In a preferred embodiment of the invention, after in conjunction with the array substrate and the color membrane substrates, the array substrate and
There is a thickness of liquid crystal box, the first thickness to be equal to the thickness of liquid crystal box between the color membrane substrates.
Compared with the existing technology, the flatness layer in array substrate of the present invention is convex through halftoning photoetching process formation column
It rises as the introns between array substrate and color membrane substrates, and gets rid of the flatness layer in open region originally, to reach array
Enough thickness of liquid crystal box between substrate and color membrane substrates, without additionally making introns, to save in color membrane substrates
On photosensitive type introns processing procedure.
For the above of the present invention can be clearer and more comprehensible, preferred embodiment cited below particularly, Bing coordinates institute's accompanying drawings, makees
Detailed description are as follows：
【Description of the drawings】
Fig. 1 is the schematic top plan view of the array substrate of the liquid crystal display panel of the present invention；
Diagrammatic cross-section of the liquid crystal display panel in AA ' line segments that Fig. 2 is Fig. 1；
Diagrammatic cross-section of the liquid crystal display panel in BB ' line segments that Fig. 3 is Fig. 1；
Fig. 4 is the flow chart of the manufacturing method of the liquid crystal display panel of the preferred embodiment of the present invention；
Fig. 5 A are the schematic diagram of step S10；
Fig. 5 B are the schematic diagram of step S20；
Fig. 5 C are the schematic diagram of step S30；
Fig. 5 D are the schematic diagram of step S40.
【Specific implementation mode】
The explanation of following embodiment is to refer to additional schema, to illustrate the particular implementation that the present invention can be used to implement
Example.
Referring to figs. 1 to Fig. 3, Fig. 1 is the schematic top plan view of the array substrate of the liquid crystal display panel of the present invention, Fig. 2 Fig. 1
Liquid crystal display panel AA ' line segments diagrammatic cross-section, Fig. 3 be Fig. 1 liquid crystal display panel BB ' line segments section illustrate
Figure.As shown, the liquid crystal display panel 10 of the present embodiment includes array substrate 20 and color membrane substrates 30 and between the two
Liquid crystal layer (not shown).
As shown in Figure 1, Fig. 1 is painted a dot structure in array substrate 20, include data line in array substrate 20
210, scan line 220 and thin film transistor (TFT) 230, the data line 210 and the scan line 220 define open region 240, wherein
It open region 240 can transparent area.
In this embodiment, thin film transistor (TFT) 230 is low temperature polycrystalline silicon (LTPS, Low Temperature Poly-
Silicon) thin film transistor (TFT).Specifically, as shown in Fig. 2, array substrate 20 is including underlay substrate 201 and in the scanning
Buffer layer (Buffer layers) 202, semiconductor layer 203, the grid being sequentially formed on 220 position of line on the underlay substrate 201
Insulating layer (GI layers) 204, barrier metal layer (GE layers) 205, interlayer dielectric layer (ILD layer) 206, patterning flatness layer (PLN layers)
207, common electrode layer 208, passivation layer 209 and pixel electrode layer 210.Color membrane substrates 30 include glass substrate 301, black matrix
(BM) 302, color blocking layer 303 and protective layer (OC) 304 thereon.
In this embodiment, setting public electrode is had no on color membrane substrates 30, and the common electrode layer of array substrate 20
208, passivation layer 209 and pixel electrode layer 210 are all on the same substrate, therefore the liquid crystal display panel 10 of the present embodiment is one
Kind generates fringe field switching (FFS, Fringe Filed Switching) pattern display panel of horizontal component of electric field.However it is of the invention
It is not limited to this, (Advanced-Super Dimensional Switching, referred to as ADS, advanced super Wei Chang are opened AD-SDS
Close) liquid of type, IPS (In Plane Switch, transverse electric field effect) type, TN (Twist Nematic, twisted-nematic) type etc.
LCD panel is all in the scope of the invention.
It is noted that the patterning flatness layer 207 is formed in the data line 210, scan line 220 and film crystal
On pipe 230, and expose the open region 240.That is, the patterning flatness layer 207 and not all covering of the present embodiment
On interlayer dielectric layer 206, but there is borehole in open region 240, and exposes the interlayer dielectric layer 206 of open region 240.
With reference to figure 1 and Fig. 2, the patterning flatness layer 207 being located in the scan line 220 forms a columnar projections
2071, the columnar projections 2071 are supported between array substrate 20 and color membrane substrates 30, and as the interval between two substrates
Son.
The diagrammatic cross-section of the liquid crystal display panel 10 positioned at the data line 210 is painted with reference to figure 1 and Fig. 3, Fig. 3, this
The array substrate 20 at place includes underlay substrate 201 and is sequentially formed at the underlay substrate on 220 position of the scan line
Gate insulating layer (GI layers) 204, interlayer dielectric layer (ILD layer) 206, source metal layer 211, patterning flatness layer (PLN on 201
Layer) 207, common electrode layer 208, passivation layer 209 and pixel electrode layer 210.
As shown in Figures 2 and 3, the patterning flatness layer 207 for forming the columnar projections 2071 has one first thickness
T1 is spent, the patterning flatness layer being located on the data line has a second thickness T2, and the first thickness T1 is more than
Second thickness T2.Specifically, in this embodiment, the first thickness T1 is described between 2.8 to 3.2 microns (μm)
Second thickness T2 is between 2.1 to 2.6 microns.If Fig. 2 such as shows, have one between array substrate 20 and the color membrane substrates 30
Thickness of liquid crystal box (Cell gap) Cg, the first thickness T1 are equal to the thickness of liquid crystal box Cg.That is, the present embodiment
Columnar projections 2071 are equal to thickness of liquid crystal box Cg as the introns between two substrates, the i.e. height of columnar projections 2071.
The manufacturing method that will be detailed below the liquid crystal display panel of the present embodiment, also referring to Fig. 4 to Fig. 5 D, figure
4 be the flow chart of the manufacturing method of the liquid crystal display panel of the preferred embodiment of the present invention, and Fig. 5 A to 5D are step S10 to S40's
Schematic diagram.The manufacturing method of the liquid crystal display panel of the present embodiment starts from step S10.
Fig. 5 A are please referred to, in step slo, provide the battle array including data line 210, scan line 220 and thin film transistor (TFT) 230
Row substrate 20, the data line 210 and the scan line 220 define open region 240, then execute step S20.Namely carry
Be sequentially formed at for underlay substrate 201 and on 220 position of the scan line buffer layer 202 on the underlay substrate 201,
Semiconductor layer 203, gate insulating layer 204, barrier metal layer 205, interlayer dielectric layer 206.This step is those skilled in the art institute
It is well known, it is no longer described in detail herein.
Fig. 5 B are please referred to, in step S20, then coating flat layer 207 executes step in the array substrate 20
S30.Specifically, flatness layer 207 is transparent organic material.
Fig. 5 C are please referred to, in step s 30, the flatness layer 207 are patterned using halftoning photoetching process, to form position
In on the data line 210, the scan line 220 and the thin film transistor (TFT) 230 and exposing the pattern of the open region 240
Change flatness layer 207, then execute step S40, wherein the patterning flatness layer 207 formation in the scan line 220
One columnar projections 2071.It is covered it is noted that above-mentioned halftoning photoetching process includes coating photoresist layer, prebake, halftoning
The processes such as mould exposure, development, rear roasting, etching, stripping photoresist.
Fig. 5 D are please referred to, in step s 40, form common electrode layer 208, passivation layer 209 and pixel electrode layer 210, so
Step S50 is executed afterwards.What this step was well known to those skilled in the art, it is no longer described in detail herein.
Referring again to Fig. 2, in step s 50, in conjunction with the array substrate 20 and color membrane substrates 30 so that the column is convex
2071 are played to be supported between the array substrate 20 and the color membrane substrates 30, and as the introns between two substrates.
Likewise, the patterning flatness layer 207 for forming the columnar projections 2071 has first thickness T1, it is located at institute
Stating the patterning flatness layer 207 on data line 220 has second thickness T2, and first thickness T1 is more than the second thickness
T2.Preferably, it can easily be set between 2.8 to 3.2 microns the first thickness T1 to through halftoning photoetching process,
The second thickness T2 is set as between 2.1 to 2.6 microns.As shown in Fig. 2, associative array substrate 20 and color membrane substrates 30
Afterwards, there is thickness of liquid crystal box Cg, and first thickness T1 is equal to liquid crystal cell between the array substrate 20 and the color membrane substrates 30
Thickness Cg.
In conclusion the flatness layer 207 in array substrate 20 of the present invention is convex through halftoning photoetching process formation column
207 are played as the introns between array substrate 20 and color membrane substrates 30, and gets rid of the flatness layer in open region 240 originally
207, to reach enough thickness of liquid crystal box Cg between array substrate 20 and color membrane substrates 30, without additional production room every
Son, to save the photosensitive type introns processing procedure on color membrane substrates.
Although the present invention is disclosed above with preferred embodiment, above preferred embodiment Bing is non-to limit the present invention,
Those skilled in the art, without departing from the spirit and scope of the present invention, can make it is various change and retouch, therefore this
The range that claim of the protection domain of invention being subject to defines.
Claims (10)
1. a kind of manufacturing method of liquid crystal display panel, which is characterized in that including：
There is provided include interlayer dielectric layer, data line, scan line and thin film transistor (TFT) array substrate, the data line and described sweep
It retouches line and defines open region, wherein the interlayer dielectric layer is exposed in the open region；
Coating flat layer is in the array substrate；
Using halftoning photoetching process, successively include coating photoresist layer in the flatness layer, prebake, half-tone mask exposure,
The processes such as development, rear roasting, etching, stripping photoresist pattern the flatness layer, to be formed positioned at the data line, the scanning
On line and the thin film transistor (TFT) and the patterning flatness layer of the open region is exposed, wherein the institute in the scan line
It states patterning flatness layer and forms a columnar projections；And
In conjunction with the array substrate and color membrane substrates so that the columnar projections are supported in the array substrate and the color film base
Between plate.
2. the manufacturing method of liquid crystal display panel according to claim 1, which is characterized in that form the columnar projections
The patterning flatness layer has a first thickness, and being located at the patterning flatness layer on the data line has one second thickness
Degree, and the first thickness is more than the second thickness.
3. the manufacturing method of liquid crystal display panel according to claim 2, which is characterized in that the first thickness between
Between 2.8 to 3.2 microns, the second thickness is between 2.1 to 2.6 microns.
4. the manufacturing method of liquid crystal display panel according to claim 2, which is characterized in that in conjunction with the array substrate and
After the color membrane substrates, there is a thickness of liquid crystal box, described first thickness etc. between the array substrate and the color membrane substrates
In the thickness of liquid crystal box.
5. a kind of liquid crystal display panel, including array substrate and color membrane substrates, the array substrate includes interlayer dielectric layer, data
Line, scan line and thin film transistor (TFT), the data line and the scan line define open region, which is characterized in that the array
Substrate further includes：
Flatness layer is patterned, is formed on the data line, the scan line and the thin film transistor (TFT), and exposes described open
The interlayer dielectric layer is exposed in mouth region, the open region, wherein the patterning flatness layer in the scan line is formed
One columnar projections, the columnar projections are supported between the array substrate and the color membrane substrates.
6. liquid crystal display panel according to claim 5, which is characterized in that form the patterning of the columnar projections
Flatness layer has a first thickness, and the patterning flatness layer being located on the data line has a second thickness, and described
First thickness is more than the second thickness.
7. liquid crystal display panel according to claim 6, which is characterized in that the first thickness is between 2.8 to 3.2 microns
Between, the second thickness is between 2.1 to 2.6 microns.
8. liquid crystal display panel according to claim 6, which is characterized in that the array substrate and the color membrane substrates it
Between have a thickness of liquid crystal box, the first thickness be equal to the thickness of liquid crystal box.
9. liquid crystal display panel according to claim 5, which is characterized in that the thin film transistor (TFT) is that low temperature polycrystalline silicon is thin
Film transistor, and the liquid crystal display panel is fringe field switching mode display panel.
10. liquid crystal display panel according to claim 9, which is characterized in that the array substrate includes underlay substrate, simultaneously
Buffer layer on the underlay substrate, semiconductor layer, gate insulating layer, grid metal are sequentially formed in the scan line position
Layer, the interlayer dielectric layer, the patterning flatness layer, common electrode layer, passivation layer and pixel electrode layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510349216.3A CN104932152B (en) | 2015-06-23 | 2015-06-23 | The manufacturing method of liquid crystal display panel and liquid crystal display panel |
| PCT/CN2015/085403 WO2016206164A1 (en) | 2015-06-23 | 2015-07-29 | Liquid crystal display panel and method for manufacturing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510349216.3A CN104932152B (en) | 2015-06-23 | 2015-06-23 | The manufacturing method of liquid crystal display panel and liquid crystal display panel |
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| CN104932152A CN104932152A (en) | 2015-09-23 |
| CN104932152B true CN104932152B (en) | 2018-11-02 |
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| CN105223740B (en) * | 2015-11-05 | 2019-01-22 | 深圳市华星光电技术有限公司 | Array substrate and its manufacturing method, liquid crystal display panel |
| CN105974678B (en) * | 2016-07-19 | 2019-05-07 | 武汉华星光电技术有限公司 | Show equipment and its liquid crystal display panel, liquid crystal display die set |
| CN106292038A (en) * | 2016-10-17 | 2017-01-04 | 武汉华星光电技术有限公司 | A kind of display panels |
| CN109003579B (en) * | 2018-07-12 | 2020-05-05 | 武汉华星光电半导体显示技术有限公司 | Pixel structure |
| CN108897178A (en) * | 2018-08-31 | 2018-11-27 | 武汉华星光电技术有限公司 | Colored filter substrate and display panel |
| TWI707180B (en) * | 2019-11-08 | 2020-10-11 | 友達光電股份有限公司 | Opposite substrate |
| CN110928016B (en) * | 2019-12-13 | 2022-02-22 | 武汉华星光电技术有限公司 | Display panel, display device and manufacturing method of display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2002350860A (en) * | 2001-05-22 | 2002-12-04 | Matsushita Electric Ind Co Ltd | Method for producing liquid crystal display device |
| JP2002350868A (en) * | 2001-05-29 | 2002-12-04 | Matsushita Electric Ind Co Ltd | Liquid crystal display device and its manufacturing method |
| KR100433662B1 (en) * | 2001-05-30 | 2004-05-31 | 비오이 하이디스 테크놀로지 주식회사 | Apparatus for In Plane Switching Liquid Crystal Display |
| KR20030032248A (en) * | 2001-10-17 | 2003-04-26 | 비오이 하이디스 테크놀로지 주식회사 | Apparatus for thin film transistor liquid crystal display and method for manufacturing the same |
| JP2006220706A (en) * | 2005-02-08 | 2006-08-24 | Sanyo Epson Imaging Devices Corp | Method of manufacturing electrooptical device, electrooptical device, and electronic equipment |
| KR101189275B1 (en) * | 2005-08-26 | 2012-10-09 | 삼성디스플레이 주식회사 | Thin film transistor array panel and method for manufacturing the same |
| CN202720426U (en) * | 2012-08-10 | 2013-02-06 | 京东方科技集团股份有限公司 | Liquid crystal display (LCD) substrate and LCD device |
| CN103091897B (en) * | 2013-02-01 | 2015-08-12 | 信利半导体有限公司 | A kind of liquid crystal indicator |
| CN103293776A (en) * | 2013-05-07 | 2013-09-11 | 北京京东方光电科技有限公司 | Array substrate and preparation method and display device thereof |
| KR102101734B1 (en) * | 2013-12-13 | 2020-04-21 | 삼성디스플레이 주식회사 | Liquid crystal display apparatus and method for manufacturing the same |
| CN103852929A (en) * | 2014-03-04 | 2014-06-11 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN104330926A (en) * | 2014-12-02 | 2015-02-04 | 合肥京东方光电科技有限公司 | Display substrate as well as manufacturing method and display panel |
| CN104538357B (en) * | 2015-01-13 | 2018-05-01 | 合肥京东方光电科技有限公司 | Make the method and array base palte of array base palte |
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| WO2016206164A1 (en) | 2016-12-29 |
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