CN104932166B - A kind of array base palte and preparation method thereof, display panel, display device - Google Patents

A kind of array base palte and preparation method thereof, display panel, display device Download PDF

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Publication number
CN104932166B
CN104932166B CN201510197509.4A CN201510197509A CN104932166B CN 104932166 B CN104932166 B CN 104932166B CN 201510197509 A CN201510197509 A CN 201510197509A CN 104932166 B CN104932166 B CN 104932166B
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Prior art keywords
passivation layer
array base
base palte
electrode
layer
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CN104932166A (en
Inventor
黄明
刘增利
王玉亮
彭俊林
杨磊
聂坤坤
袁帅
周传鹏
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1339Gaskets; Spacers; Sealing of cells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • G02F1/136295Materials; Compositions; Manufacture processes
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention discloses a kind of array base palte and preparation method thereof, display panel, display device, is entered with to avoid outside water vapour in array base palte, improves the reliability of display panel.The array base palte includes gate insulator, the first passivation layer, organic film and the second passivation layer being arranged on underlay substrate, wherein, second passivation layer is provided with void region, and the void region is corresponding with the region for being bonded sealant.

Description

A kind of array base palte and preparation method thereof, display panel, display device
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof, display panel, display Device.
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) is currently used flat-panel monitor, and LCD is shown Device with its low-voltage, low-power consumption, be suitable for circuit integrate, it is light and handy portable the advantages that and be subject to widely research and application.
With the development of LCD technology, to wanting for the response speed of liquid crystal display panel, resolution ratio and aperture opening ratio Ask continuous improvement.The prior art increase aperture opening ratio generally use organic film as passivation layer a part lower public electrode and Capacitance between source/drain lines.Main purpose is the influence for reducing source/drain signal to public electrode, and then reduces source Influence of the pole/drain signal to liquid crystal deflection near source/drain lines, so as to reduce black matrix above signal wire and scan line Size, and then improve liquid crystal display panel pixel aperture opening ratio.
As shown in Figure 1, the display panel of the prior art includes the array base palte 11 and color membrane substrates 12 being oppositely arranged, and Liquid crystal layer 13 and sealant 14 between array base palte 11 and color membrane substrates 12, specifically, array base palte 11 are included successively It is arranged on gate insulator 111 on underlay substrate 110, the first passivation layer 112, organic film 113, first electrode layer 114, Two passivation layers 115 and the second electrode lay 116.It will be noted from fig. 1 that sealant 14 is located on the second passivation layer 115.
For the display characteristic of the display panel shown in proof diagram 1, reliability survey is carried out to the display panel shown in Fig. 1 Display panel shown in Fig. 1, i.e., be put into the test environment of high temperature, high humidity and high pressure after a period of time by examination, tests display surface Whether the display characteristic of plate changes, the temperature during test of reliability that the general prior art uses for 60 DEG C, humidity 80%, pressure When being by force 240 small for two atmospheric pressure, time.Test result shows that the display characteristic of the display panel is deteriorated, and main cause is When carrying out the second 115 plated film of passivation layer, temperature during due to plated film is less than 200 DEG C, the second passivation layer 115 that plated film obtains Characteristic is poor, and therefore, the temperature in actual production process during plated film is more than 200 DEG C, and organic film 113 is more than 150 DEG C Situation lower surface can distil, and the organic film of distillation can participate in the initial reaction of 115 plated film of the second passivation layer, and reaction influences the Two passivation layers 115 and the below adhesiveness between film layer, in the case where carrying out reliability test condition, extraneous steam is easy to from viscous The poor interface of attached property enters inside display panel, and bubble 15 is internally formed in display panel, so that display panel Display characteristic is deteriorated.
In conclusion the display panel of the prior art is in actual use, extraneous steam be easy to from adhesiveness compared with The interface of difference enters in display panel, so as to influence the display characteristic of display panel, the reliability of display panel is poor.
The content of the invention
An embodiment of the present invention provides a kind of array base palte and preparation method thereof, display panel, display device, with to avoid Extraneous steam enters in array base palte, improves the reliability of display panel.
A kind of array base palte provided in an embodiment of the present invention, including be arranged on underlay substrate gate insulator, first Passivation layer, organic film and the second passivation layer, wherein,
Second passivation layer is provided with void region, and the void region is corresponding with the region for being bonded sealant.
By array base palte provided in an embodiment of the present invention, including the gate insulator, first blunt being arranged on underlay substrate Change layer, organic film and the second passivation layer, wherein, second passivation layer is provided with void region, and the void region is with using Corresponded in the region of fitting sealant.Since region corresponding with the region for being bonded sealant is not set in the embodiment of the present invention The second passivation layer is put, compared with prior art, can effectively avoid extraneous steam because the second passivation layer Interface Adhesion sex chromosome mosaicism Into in array base palte, the reliability of array base palte is improved.
It is preferred that first passivation layer is provided with void region, which is set with second passivation layer Void region corresponds to.
In this way, the sealant being subsequently bonded directly is contacted with gate insulator, compared with prior art, can effectively avoid Extraneous steam improves the reliability of array base palte because the second passivation layer Interface Adhesion sex chromosome mosaicism enters in array base palte.
It is preferred that the array base palte includes the first electrode layer and the second electrode lay of insulation set, wherein,
The first electrode layer is pixel electrode, and the second electrode lay is public electrode;Or,
The first electrode layer is public electrode, and the second electrode lay is pixel electrode.
It is preferred that the first electrode layer is face electrode, the second electrode lay is strip electrode.
It is preferred that the material of the gate insulator is silica or silicon nitride.
It is preferred that the material of first passivation layer is silica or silicon nitride.
It is preferred that the material of second passivation layer is silica or silicon nitride.
The embodiment of the present invention additionally provides a kind of display panel, including the first substrate and second substrate being oppositely arranged, with And liquid crystal layer and sealant between the first substrate and the second substrate, wherein, the first substrate is above-mentioned Array base palte.
The embodiment of the present invention additionally provides a kind of display device, which includes above-mentioned display panel.
The embodiment of the present invention additionally provides a kind of production method of array base palte, the described method includes:
Make gate insulator, the first passivation layer, organic film and second successively on underlay substrate by patterning processes Passivation layer;
The second passivation layer of predeterminable area is removed by patterning processes;Or, remove the second passivation layer and the of predeterminable area One passivation layer;The predeterminable area is corresponding with the region for being bonded sealant.
Brief description of the drawings
Fig. 1 is the cross section structure schematic diagram at prior art display panel edge;
Fig. 2 is a kind of cross section structure schematic diagram at array base palte edge provided in an embodiment of the present invention;
Fig. 3 is the cross section structure schematic diagram at another array base palte edge provided in an embodiment of the present invention;
Fig. 4 is the cross section structure schematic diagram at another array base palte edge provided in an embodiment of the present invention;
Fig. 5 is a kind of cross section structure schematic diagram at display panel edge provided in an embodiment of the present invention;
Fig. 6 is a kind of production method flow chart of array base palte provided in an embodiment of the present invention;
Fig. 7 illustrates for the cross section structure at the array base palte edge after second passivation layer of making provided in an embodiment of the present invention Figure.
Embodiment
An embodiment of the present invention provides a kind of array base palte and preparation method thereof, display panel, display device, with to avoid Extraneous steam enters in array base palte, improves the reliability of display panel.
In order to make the object, technical solutions and advantages of the present invention clearer, the present invention is made below in conjunction with attached drawing into One step it is described in detail, it is clear that described embodiment only part of the embodiment of the present invention, rather than whole implementation Example.Based on the embodiments of the present invention, those of ordinary skill in the art are obtained without making creative work All other embodiment, belongs to the scope of protection of the invention.
The array base palte and display panel of specific embodiment of the invention offer are provided below in conjunction with the accompanying drawings.
Each layer film thickness and area size shape do not react the actual proportions of each film layer in attached drawing, and purpose is simply illustrated to say Bright present invention.
As shown in Fig. 2, the specific embodiment of the invention provides a kind of array base palte, including it is arranged on underlay substrate 110 Gate insulator 111, the first passivation layer 112,113 and second passivation layer 115 of organic film, wherein, the second passivation layer 115 is set Void region 20 is equipped with, void region 20 is corresponding with the region for being bonded sealant.
Preferably, should as shown in figure 3, the first passivation layer 112 in the specific embodiment of the invention is provided with void region 30 Void region 30 is corresponding with the void region 20 that the second passivation layer 115 is set.
Preferably, the material of gate insulator 111 is silica (SiO2) or silicon nitride in the specific embodiment of the invention (SiN), it is, of course, also possible to for SiO2 and SiN composite membrane, the specific embodiment of the invention is not to the tool of gate insulator 111 Body material limits.The material of the first passivation layer 112 in the specific embodiment of the invention is SiO2 or SiN, it is, of course, also possible to be The composite membrane of SiO2 and SiN, the specific embodiment of the invention do not limit the specific material of the first passivation layer 112.The present invention The material of the second passivation layer 115 in specific embodiment is SiO2 or SiN, it is, of course, also possible to be the composite membrane of SiO2 and SiN, The specific embodiment of the invention does not limit the specific material of the second passivation layer 115.
Preferably, as shown in figure 4, the array base palte in the specific embodiment of the invention includes the first electrode layer of insulation set 114 and the second electrode lay 116, wherein, first electrode layer 114 is pixel electrode, and the second electrode lay 116 is public electrode;Or, the One electrode layer 114 is public electrode, and the second electrode lay 116 is pixel electrode.Certainly, in actual setting, can also only set First electrode layer 114, is not provided with the second electrode lay, and first electrode layer 114 can also be set directly on underlay substrate 110.This First electrode layer 114 is face electrode in invention specific embodiment, and the second electrode lay 116 is strip electrode.
The material of first electrode layer 114 in the specific embodiment of the invention is tin indium oxide (ITO) or indium zinc oxide (IZO) Monofilm, or the composite membrane formed for ITO and IZO is of the invention it is, of course, also possible to be other types of transparent conductive film Specific embodiment does not limit the specific material of first electrode layer 114.The second electrode lay in the specific embodiment of the invention 116 material is the monofilm of ITO or IZO, or is the composite membrane that ITO and IZO is formed, it is, of course, also possible to be other types of Transparent conductive film, the specific embodiment of the invention do not limit the specific material of the second electrode lay 116.Preferably, this hair The material identical of the material of first electrode layer 114 and the second electrode lay 116 in bright specific embodiment.
Array base palte in the specific embodiment of the invention further includes the grid being arranged on underlay substrate, gate line, data The structures such as line, since these structures are not related to the improvement part of the specific embodiment of the invention, therefore do not elaborate here.
As shown in figure 5, the specific embodiment of the invention additionally provides a kind of display panel, including the first substrate being oppositely arranged 21 and second substrate 22, and liquid crystal layer 13 and sealant 14 between first substrate 21 and second substrate 22, wherein, One substrate 21 is array base palte described above.Compared with the display panel of the prior art, due in the specific embodiment of the invention Region corresponding with the region for being bonded sealant 14 is not provided with the second passivation layer, therefore can effectively avoid using Extraneous steam enters inside display panel from the poor interface of adhesiveness in journey, improves the display characteristic of display panel, improves The reliability of display panel.
Preferably, the first substrate 21 in the specific embodiment of the invention is array base palte, and second substrate 22 is color membrane substrates. Certainly, in the actual production process, color film layer can also be produced on first substrate 21, the specific embodiment of the invention is only with One substrate 21 is array base palte, and second substrate 22 is to be introduced exemplified by color membrane substrates.
Display panel in the specific embodiment of the invention can be fringing field rotation in surface (Fringe Field Switching, FFS) pattern display panel, or advanced super dimension switch (Advanced Super Dimension Switch, ADS) pattern display panel, or in-plane conversion (In-Plane-Switching, IPS) pattern Display panel, or twisted nematic (Twisted Nematic, TN) display panel.
The specific embodiment of the invention also provides a kind of display device, including above-mentioned display panel, which can be with Filled for displays such as liquid crystal panel, liquid crystal display, LCD TV, oled panel, OLED display, OLED TVs or Electronic Papers Put.
The production method of the array base palte of specific embodiment of the invention offer is provided below in conjunction with the accompanying drawings.
As shown in fig. 6, the specific embodiment of the invention additionally provides a kind of production method of array base palte, this method includes:
S601, made successively on underlay substrate by patterning processes gate insulator, the first passivation layer, organic film and Second passivation layer;
S602, the second passivation layer by patterning processes removal predeterminable area;Or, remove the second passivation layer of predeterminable area With the first passivation layer;The predeterminable area is corresponding with the region for being bonded sealant.
Specifically, as shown in fig. 7, first, gate insulator is made successively on underlay substrate 110 by patterning processes 111st, the first passivation layer 112,113 and second passivation layer 115 of organic film.Underlay substrate 110 in the specific embodiment of the invention For glass substrate, or it is the other types of substrates such as ceramic substrate.Preferably, the gate insulator in the specific embodiment of the invention 111 material is SiO or SiN;The material of first passivation layer 112 is SiO or SiN;The material of second passivation layer 115 for SiO or SiN, the specific embodiment of the invention is not to the specific material of gate insulator 111, the first passivation layer 112 and the second passivation layer 115 Material limits.Patterning processes in the specific embodiment of the invention include:Coating, exposure, development, etching and the removal of photoresist The part or all of process of photoresist.The specific embodiment of the invention makes grid successively by patterning processes on underlay substrate 110 Pole insulating layer 111, the first passivation layer 112, the specific production method and the prior art of 113 and second passivation layer 115 of organic film Identical, which is not described herein again.
The second passivation layer of predeterminable area, the predeterminable area and the area for being bonded sealant are removed by patterning processes Domain corresponds to, and specifically includes:
Photoresist is coated on the underlay substrate shown in Fig. 7, the photoresist of specific embodiment of the invention coating is with positivity light Illustrate exemplified by photoresist, the photoresist of coating is exposed, is developed, form photoresist reserved area and photoresist removes area, photoetching Glue removal area corresponds to the predeterminable area in the specific embodiment of the invention, and photoresist removes area and exposes the second passivation layer, then, right The second passivation layer exposed performs etching, and removes the second passivation layer exposed, afterwards, removes remaining photoresist, forms Fig. 2 Shown array base palte.
The second passivation layer and the first passivation layer of predeterminable area are removed by patterning processes, the predeterminable area is pasted with being used for The region for closing sealant corresponds to, and specifically includes:
Photoresist is coated on the underlay substrate shown in Fig. 7, the photoresist of specific embodiment of the invention coating is with positivity light Illustrate exemplified by photoresist, the photoresist of coating is exposed, is developed, form photoresist reserved area and photoresist removes area, photoetching Glue removal area corresponds to the predeterminable area in the specific embodiment of the invention, and photoresist removes area and exposes the second passivation layer, then, right The second passivation layer exposed performs etching, and removes the second passivation layer exposed, exposes the first passivation layer, and then to sudden and violent The first passivation layer exposed performs etching, and removes the first passivation layer exposed, afterwards, removes remaining photoresist, forms Fig. 3 institutes The array base palte shown.
In conclusion the specific embodiment of the invention provides a kind of array base palte and preparation method thereof, display panel, display dress Put, including gate insulator, the first passivation layer, organic film and the second passivation layer being arranged on underlay substrate, wherein, second Passivation layer is provided with void region, and the void region is corresponding with the region for being bonded sealant.Due to of the invention specific real Apply the second passivation layer in example and be provided with void region, the void region is corresponding with the region for being bonded sealant, and existing Technology is compared, and sealant does not directly contact setting with the second passivation layer, can effectively avoid outside water in use Vapour enters in display panel from the poor interface of adhesiveness, improves the display characteristic of display panel, improves the letter of display panel Lai Xing.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art God and scope.In this way, if these modifications and changes of the present invention belongs to the scope of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to comprising including these modification and variations.

Claims (9)

1. a kind of array base palte, including gate insulator, the first passivation layer, the organic film and second being arranged on underlay substrate Passivation layer, it is characterised in that
Second passivation layer is provided with void region, and the void region is corresponding with the region for being bonded sealant;
The material of second passivation layer is silica or silicon nitride.
2. array base palte according to claim 1, it is characterised in that first passivation layer is provided with void region, should Void region is corresponding with the void region that second passivation layer is set.
3. array base palte according to claim 1, it is characterised in that the array base palte includes the first electricity of insulation set Pole layer and the second electrode lay, wherein,
The first electrode layer is pixel electrode, and the second electrode lay is public electrode;Or,
The first electrode layer is public electrode, and the second electrode lay is pixel electrode.
4. array base palte according to claim 3, it is characterised in that the first electrode layer is face electrode, described second Electrode layer is strip electrode.
5. array base palte according to claim 1, it is characterised in that the material of the gate insulator is silica or nitrogen SiClx.
6. array base palte according to claim 1, it is characterised in that the material of first passivation layer is silica or nitrogen SiClx.
7. a kind of display panel, it is characterised in that including the first substrate and second substrate being oppositely arranged, and positioned at described Liquid crystal layer and sealant between one substrate and the second substrate, wherein, the first substrate is any power of claim 1-6 Array base palte described in.
8. a kind of display device, it is characterised in that the display device includes the display panel described in claim 7.
A kind of 9. production method of array base palte, it is characterised in that the described method includes:
Make gate insulator, the first passivation layer, organic film and the second passivation successively on underlay substrate by patterning processes Layer;
The second passivation layer of predeterminable area is removed by patterning processes;Or, remove the second passivation layer of predeterminable area and first blunt Change layer;The predeterminable area is corresponding with the region for being bonded sealant.
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CN105137667A (en) * 2015-10-16 2015-12-09 京东方科技集团股份有限公司 Display device and manufacturing method thereof
CN108169964A (en) * 2018-01-24 2018-06-15 京东方科技集团股份有限公司 Encapsulating structure, liquid crystal display panel and the liquid crystal display of liquid crystal display panel
CN108428804A (en) * 2018-04-19 2018-08-21 武汉华星光电技术有限公司 Oled display panel and its packaging method
CN110018595B (en) * 2019-04-25 2021-11-12 厦门天马微电子有限公司 Display panel and display device
CN111308816A (en) * 2020-02-28 2020-06-19 重庆京东方光电科技有限公司 Organic film, array substrate, display panel and display device
CN113867053B (en) * 2020-06-30 2023-05-16 京东方科技集团股份有限公司 Display panel and preparation method thereof
CN115167039A (en) * 2022-07-11 2022-10-11 广州华星光电半导体显示技术有限公司 Array substrate and liquid crystal display panel

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1560686A (en) * 2004-02-24 2005-01-05 友达光电股份有限公司 Liquid crystal display panel
CN102033371A (en) * 2009-09-24 2011-04-27 北京京东方光电科技有限公司 Array substrate and manufacturing method thereof
CN102854664A (en) * 2011-06-29 2013-01-02 奇美电子股份有限公司 Image display system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3939140B2 (en) * 2001-12-03 2007-07-04 株式会社日立製作所 Liquid crystal display
JP5259163B2 (en) * 2007-12-03 2013-08-07 三菱電機株式会社 Transflective liquid crystal display device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1560686A (en) * 2004-02-24 2005-01-05 友达光电股份有限公司 Liquid crystal display panel
CN102033371A (en) * 2009-09-24 2011-04-27 北京京东方光电科技有限公司 Array substrate and manufacturing method thereof
CN102854664A (en) * 2011-06-29 2013-01-02 奇美电子股份有限公司 Image display system

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