CN104521000A - 具有可调的高栅极-源极额定电压的iii族氮化物增强型晶体管 - Google Patents

具有可调的高栅极-源极额定电压的iii族氮化物增强型晶体管 Download PDF

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CN104521000A
CN104521000A CN201380041952.1A CN201380041952A CN104521000A CN 104521000 A CN104521000 A CN 104521000A CN 201380041952 A CN201380041952 A CN 201380041952A CN 104521000 A CN104521000 A CN 104521000A
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S·彭迪哈卡
N·特珀尔内尼
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Texas Instruments Inc
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Abstract

一种半导体器件包括增强型GaN FET(102)和耗尽型GaN FET(104)，耗尽型GaN FET(104)串联地电耦合在增强型GaN FET的栅极节点(120)和半导体器件的栅极端子(116)之间。耗尽型GaN FET的栅极节点(122)电耦合到增强型GaN FET的源极节点(106)和半导体器件的源极端子(108)，增强型GaN FET的漏极节点(110)电耦合到半导体器件的漏极端子(112)，并且耗尽型GaN FET的漏极节点(114)电耦合到半导体器件的栅极端子(116)。

Description

具有可调的高栅极-源极额定电压的III族氮化物增强型晶体管
技术领域
本发明涉及半导体器件领域，更具体地涉及半导体器件中的氮化镓场效应晶体管(GaN FET)。
背景技术
由诸如GaN的III-N材料制成的场效应晶体管(FET)与硅FET相比，呈现出电力开关所期望的性能(诸如高带隙和高热导率)。然而，具有半导体栅极的增强型GaN FET在栅极过偏压时，不期望地易受到过多的栅极泄漏电流的影响。类似地，具有绝缘栅极的增强型GaN FET在栅极过偏压时易受到栅极电介质击穿的影响。
发明内容
一种半导体器件包括增强型GaN FET和耗尽型GaN FET，增强型GaN FET具有p型半导体材料的栅极或绝缘栅极，并且耗尽型GaN FET串联地电耦合在增强型GaN FET的栅极节点和半导体器件的栅极端子之间。耗尽型GaN FET的栅极节点电耦合到增强型GaN FET的源极节点。
在半导体器件的工作期间，可将低于最大所需栅极-源极偏压的低栅极偏压施加到半导体器件的栅极端子；低栅极偏压通过耗尽型GaN FET传输并被施加到增强型GaN FET的栅极节点，其中耗尽型GaN FET两端几乎没有压降。可将高于最大所需栅极-源极偏压的高栅极偏压施加到半导体器件的栅极端子；高栅极偏压使耗尽型GaN FET进入夹断模式，以使耗尽型GaN FET的源极节点维持在夹断电压下，并且耗尽型GaN FET两端的漏极-源极压降随高栅极偏压的增加而增加，并且因此增强型GaNFET的栅极节点上的栅极偏压维持在低于最大所需栅极-源极偏压的夹断电压下。
附图说明
图1是示例性半导体器件的电路图。
图2-图4是示例性半导体器件的横截面视图。
具体实施方式
半导体器件包括增强型GaN FET和耗尽型GaN FET，增强型GaNFET具有p型半导体材料的栅极或绝缘栅极，并且耗尽型GaN FET串联地电耦合在增强型GaN FET的栅极节点和半导体器件的栅极端子之间。耗尽型GaN FET的栅极节点电耦合到增强型GaN FET的源极节点。
在半导体器件的工作期间，可将低于最大所需栅极-源极偏压的低栅极偏压施加到半导体器件的栅极端子；低栅极偏压通过耗尽型GaN FET传输并被施加到增强型GaN FET的栅极节点，其中耗尽型GaN FET两端几乎没有压降。可将高于最大所需栅极-源极偏压的高栅极偏压施加到半导体器件的栅极端子；高栅极偏压使耗尽型GaN FET进入夹断模式，以使耗尽型GaN FET的源极节点维持在夹断电压下，并且耗尽型GaN FET两端的漏极-源极压降随高栅极偏压的增加而增加，并且因此增强型GaNFET的栅极节点上的栅极偏压维持在低于最大所需栅极-源极偏压的夹断电压下。
术语“III-N”是指半导体材料，其中第III族元素(铝、镓、铟和硼)提供半导体材料中的一部分原子，而氮原子提供半导体材料中的剩余部分原子。III-N半导体材料的示例是氮化镓、氮化硼镓、氮化铝镓、氮化铟以及氮化铟铝镓。描述材料的元素化学式的术语并不暗示元素的特定化学计量。III-N材料可用变量下标书写，来表示一系列可能的化学计量。例如，氮化铝镓可写为AlxGa1-xN，并且氮化铟铝镓可写为InxAlyGa1-x-yN。术语GaN FET是指包括III-N半导体材料的场效应晶体管。
图1是示例性半导体器件的电路图。半导体器件100包括增强型GaNFET 102和耗尽型GaN FET 104。增强型GaN FET 102的源极节点106电耦合到半导体器件100的源极端子108。增强型GaN FET102的漏极节点110电耦合到半导体器件100的漏极端子112。
耗尽型GaN FET 104的漏极节点114电耦合到半导体器件100的栅极端子116。耗尽型GaN FET 104的源极节点118电耦合到增强型GaNFET 102的栅极节点120。耗尽型GaN FET 104的栅极节点122电耦合到半导体器件100的源极端子108。
当增强型GaN FET 102上的栅极-源极偏压超过最大所需栅极-源极偏压(例如5伏特)时，增强型GaN FET 102的栅极节点120会不期望地引起(draw)过多电流。增强型GaN FET 102的阈值电压小于最大所需栅极-源极偏压。耗尽型GaN FET 104的栅极-源极夹断电压小于增强型GaN FET的最大所需栅极-源极偏压。
图2-图4示出示例性半导体器件的横截面。参考图2，半导体器件200包括增强型GaN FET 202和耗尽型GaN FET 204。增强型GaN FET202在硅衬底224上形成。失配绝缘层226在硅衬底224上形成。失配绝缘层226可以是，例如，100至300纳米的氮化铝。
缓冲层228在失配绝缘层226上形成。缓冲层228可以具有，例如1至7微米的厚度，并且包括一叠AlxGa1-xN的渐变层，渐变层中，在失配绝缘层226处存在丰富的铝并且在缓冲层228的顶表面处存在丰富的镓。
电绝缘层230在缓冲层228上形成。电绝缘层230可以是，例如300至2000纳米的半绝缘氮化镓。电绝缘层608可以是，例如，半绝缘的，以提供电绝缘层230上方和下方的层之间期望水平的电绝缘。
低缺陷层232在电绝缘层230上形成。低缺陷层232可以是，例如25至1000纳米的氮化镓。可形成低缺陷层232，以便最小化可对电子迁移率有不利影响的晶体缺陷，这可能导致低缺陷层232掺杂例如具有低于1017cm-3的掺杂浓度的碳、铁或其他掺杂物质。
阻挡层234在低缺陷层232上形成。阻挡层234可以是，例如8至30纳米的AlxGa1-xN或InxAlyGa1-x-yN。阻挡层234中的第III族元素的组成可以是，例如24％-28％的氮化铝和72％-76％的氮化镓。在低缺陷层232上形成阻挡层234恰在阻挡层234下方的低缺陷层232中产生具有例如1x1012至2x1013cm-2的电子密度的二维电子气。
可选的盖层236可在阻挡层234上形成。盖层236可以是，例如2至5纳米的氮化镓。盖层236可减少阻挡层234中铝的氧化。
若存在盖层，则增强型栅极220在盖层236上形成，若没有形成盖层，则增强型栅极220在阻挡层234上形成。增强型栅极220包括p型III-N半导体(如氮化镓、氮化镓铝、氮化铟镓铝、氮化铟铝和氮化铝等)中的一层或更多层。增强型栅极220可具有金属栅极盖238，金属栅极盖238与增强型栅极220形成欧姆接触或者肖特基接触，以改善电性能。
源极触点206被形成通过盖层236并延伸到阻挡层234，以便形成到增强型GaN FET 202的低缺陷层232中的二维电子气的隧道连接。源极触点206可与增强型栅极220横向分离，例如500至1500纳米的距离。类似地，漏极触点210被形成通过盖层236并延伸到阻挡层234，以便形成到二维电子气的隧道连接。漏极触点210与增强型栅极220横向分离的距离取决于增强型GaN FET 202的最大工作电压。例如，在设计为其最大工作电压为200伏的增强型GaN FET 202中，漏极触点210可与增强型栅极220横向分离2至8微米的距离。在设计为其最大工作电压为600伏的增强型GaN FET 202中，漏极触点210可与增强型栅极220横向分离5至20微米的距离。
耗尽型GaN FET 204可与增强型GaN FET 202形成在相同的硅衬底224上，并使用相同的III-N层：失配绝缘层226、缓冲层228、电绝缘层230、低缺陷层232、阻挡层234以及可选的盖层236(如果存在的话)。若存在盖层236，则耗尽型栅极222在盖层236上形成，或者若不存在盖层236，则耗尽型栅极222在阻挡层234上形成。耗尽型栅极222可由例如100至300纳米的钨或钛钨形成。可使用蚀刻工艺或者可替代地使用剥离(liftoff)工艺对耗尽型栅极222图案化。形成源极触点218和漏极触点214，以形成到耗尽型GaN FET 204的二维电子气的隧道连接，如参考增强型GaN FET 202所描述的。
增强型GaN FET 202和/或耗尽型GaN FET 204可在图2所示的不同层结构中形成并以不同的层结构形成。例如，可省略电绝缘层230，使得阻挡层234在缓冲层228上形成。可使用蓝宝石衬底或绝缘体上的硅衬底来代替硅衬底224。
增强型GaN FET 202的增强型栅极220、源极触点206和漏极触点210，以及耗尽型GaN FET 204的耗尽型栅极222、源极触点218和漏极触点214彼此电耦合，并电耦合到半导体器件200的栅极端子216、源极端子208和漏极端子212，如参考图1的电路图所描述的。例如通过形成电介质层和图案化的金属互连层，可实现电耦合。
在半导体器件200的其中一种配置中，硅衬底224可电耦合到源极端子208。在另一种配置中，硅衬底224可电耦合到漏极端子212。在进一步的一种配置中，硅衬底224可与源极端子208和漏极端子212电绝缘。
在本示例的一个替代方案中，耗尽型GaN FET 204可在与增强型GaN FET 202分离的衬底上形成，并可进一步具有III-N半导体材料的不同的层结构。在这样的方案中，例如，通过引线键合或通过将增强型GaNFET 202和耗尽型GaN FET 204安装在具有导电引线的多芯片载体中，可实现电耦合。
参考图3，半导体器件300包括增强型GaN FET 302和耗尽型GaNFET 304。增强型GaN FET 302在硅衬底324上形成，例如，其具有失配绝缘层326、缓冲层328、电绝缘层330、低缺陷层332、阻挡层334以及可能的可选盖层336，如参考图2所描述的。形成源极触点306和漏极触点310，以形成到增强型GaN FET 302的二维电子气的隧道连接，如参考图2的增强型GaN FET 202所描述的。
在增强型GaN FET 302中，在可选的盖层336和增强型栅极320形成之前，凹槽340在增强型栅极320下的阻挡层334中形成。凹槽340的底部可以处于低缺陷层332顶表面上方例如5至15纳米。盖层336和增强型栅极320在凹槽340中基本共形。在凹槽340中形成增强型栅极320可为增强型GaN FET 302有利地提供较低的阈值电压。
耗尽型GaN FET 304可与增强型GaN FET 302形成在相同的硅衬底324上，使用相同的III-N层：失配绝缘层326、缓冲层328、电绝缘层330、低缺陷层332、阻挡层334和可选的盖层336(如果存在的话)。若存在盖层，则III-N半导体材料的耗尽型栅极322在盖层336上形成，若不存在盖层，则II-N半导体材料的耗尽型栅极322在阻挡层334上形成。耗尽型栅极322可由例如150至300纳米的III-N半导体材料(诸如氮化镓或氮化铝镓)形成。形成源极触点318和漏极触点314，以形成到耗尽型GaN FET 304的二维电子气的隧道连接，如参考增强型GaN FET 302所描述的。
如上所述，增强型GaN FET 302和/或耗尽型GaN FET 304可在相同的层结构中形成并以相同的层结构形成。可替代地，增强型GaN FET 302和/或耗尽型GaN FET 304可在与图3示出的不同的层结构中形成并以不同的层结构形成，例如参考图2所描述的。
增强型GaN FET 302的增强型栅极320、源极触点306和漏极触点310，以及耗尽型GaN FET 304的耗尽型栅极322、源极触点318和漏极触点314彼此电耦合，并电耦合到半导体器件300的栅极端子316、源极端子308和漏极端子312，如参考图1的电路图所描述的。硅衬底324可电耦合到源极端子308、漏极端子312，或与源极端子308和漏极端子312绝缘。
参考图4，一种半导体器件400包括增强型绝缘栅极GaN FET 402和耗尽型GaN FET 404。增强型绝缘栅极GaN FET 402形成在硅衬底424上，例如，具有失配绝缘层426、缓冲层428、电绝缘层430、低缺陷层432、阻挡层434以及可能的可选盖层436，如参考图2所描述的。形成源极触点406和漏极触点410，以形成到增强型绝缘栅极GaN FET 402的二维电子气的隧道连接，如参考图2的增强型GaN FET 202所描述的。
在增强型绝缘栅极GaN FET 402中，凹槽440在阻挡层434中形成。可选的盖层436和栅极电介质层442在凹槽440中形成，并且增强型绝缘栅极420在栅极电介质层442上形成。凹槽440的底部可以处于低缺陷层432的顶表面上方例如5纳米至15纳米。在凹槽440中形成增强型绝缘栅极420可为增强型绝缘栅极GaN FET 402有利地提供较低的阈值电压。
耗尽型GaN FET 404可与增强型绝缘栅极GaN FET 402形成在相同的硅衬底424上，使用相同的III-N层：失配绝缘层426、缓冲层428、电绝缘层430、低缺陷层432、阻挡层434以及可选的盖层436(如果存在的话)。若存在盖层，则III-N半导体材料的耗尽型栅极422在盖层436上形成，若不存在盖层，则III-N半导体材料的耗尽型栅极422在阻挡层434上形成。耗尽型栅极422可由例如150至300纳米的III-N半导体材料(诸如氮化镓或氮化铝镓)形成，或者可以是参考图2所描述的金属栅极。形成源极触点418和漏极触点414，以形成到耗尽型GaN FET 404的二维电子气的隧道连接，如参考增强型绝缘栅极GaN FET 402所描述的。
如上所述，增强型绝缘栅极GaN FET 402和/或耗尽型GaN FET 404可在相同的层结构中形成并以相同的层结构形成。可替代地，增强型绝缘栅极GaN FET 402和/或耗尽型GaN FET 404可在与图4示出的不同的层结构中形成并以不同的层结构形成，例如参考图2所描述的。
增强型绝缘栅极GaN FET 402中的增强型栅极420、源极触点406和漏极触点410，以及耗尽型GaN FET 404的耗尽型栅极422、源极触点418和漏极触点414彼此电耦合，并电耦合到半导体器件400的栅极端子416、源极端子408和漏极端子412，如参考图1的电路图所描述的。硅衬底424可电耦合到源极端子408、漏极端子412，或与源极端子408和漏极端子412绝缘。
本领域的技术人员将理解，在所要求保护的本发明的范围内，可对所述实施例进行修改，并且还可能有许多其他实施例。

Claims (20)

1.一种半导体器件，其包括：
增强型氮化镓场效应晶体管，即增强型GaN FET；以及
耗尽型GaN FET；
其中：
所述增强型GaN FET的源极节点电耦合到所述半导体器件的源极端子；
所述增强型GaN FET的漏极节点电耦合到所述半导体器件的漏极端子；
所述增强型GaN FET的栅极节点电耦合到所述耗尽型GaN FET的源极节点；
所述耗尽型GaN FET的栅极节点电耦合到所述增强型GaN FET的所述源极节点；以及
所述耗尽型GaN FET的漏极节点电耦合到所述半导体器件的栅极端子。
2.根据权利要求1所述的器件，其中所述增强型GaN FET的栅极包括在阻挡层上的p型III-N半导体材料层，所述阻挡层在氮化镓的低缺陷层上。
3.根据权利要求2所述的器件，其中所述增强型GaN FET的所述栅极包括在所述p型III-N半导体材料层上的金属层。
4.根据权利要求1所述的器件，其中所述增强型GaN FET的栅极是绝缘栅极。
5.根据权利要求1所述的器件，其中所述增强型GaN FET包括阻挡层中的凹槽，所述阻挡层在氮化镓的低缺陷层上，并且所述增强型GaNFET的栅极设置在所述凹槽中。
6.根据权利要求1所述的器件，其中所述增强型GaN FET包括阻挡层上的氮化镓的盖层，所述阻挡层在氮化镓的低缺陷层上。
7.根据权利要求1所述的器件，其中所述耗尽型GaN FET包括氮化镓的低缺陷层和所述低缺陷层上的阻挡层，所述阻挡层包括的半导体材料选自包括下列项的组中：AlxGa1-xN和InxAlyGa1-x-yN。
8.根据权利要求1所述的半导体器件，其中所述耗尽型GaN FET包括金属的耗尽型栅极。
9.根据权利要求1所述的器件，其中所述耗尽型GaN FET包括III-N半导体材料的耗尽型栅极。
10.根据权利要求1所述的器件，其中所述耗尽型GaN FET和所述增强型GaN FET在相同的衬底和相同的III-N半导体材料的层结构上形成。
11.一种形成半导体器件的过程，包括：
通过以下过程形成增强型GaN FET，所述过程包括：
在第一衬底上方形成包括氮化镓的第一低缺陷层；
在所述低缺陷层上方形成包括氮化铝镓的第一阻挡层，从而在所述第一低缺陷层中产生二维电子气，用于提供所述增强型GaN FET的导电沟道；以及
在所述第一阻挡层上方形成增强型栅极；
通过以下过程形成耗尽型GaN FET，所述过程包括：
在第二衬底上方形成包括氮化镓的第二低缺陷层；
在所述第二低缺陷层上方形成包括氮化铝镓的第二阻挡层，从而在所述第二低缺陷层中产生二维电子气，用于提供所述耗尽型GaNFET的导电沟道；以及
在所述第二阻挡层上方形成耗尽型栅极；
将所述增强型GaN FET的源极节点电耦合到所述半导体器件的源极端子；
将所述增强型GaN FET的漏极节点电耦合到所述半导体器件的漏极端子；
将所述增强型GaN FET的所述增强型栅极电耦合到所述耗尽型GaNFET的源极节点；
将所述耗尽型GaN FET的所述耗尽型栅极电耦合到所述增强型GaNFET的所述源极节点；以及
将所述耗尽型GaN FET的漏极节点电耦合到所述半导体器件的栅极端子。
12.根据权利要求11所述的过程，其中形成所述增强型GaN FET的所述步骤包括：通过在阻挡层上形成p型III-N半导体材料层以形成所述增强型GaN FET的栅极，所述阻挡层在氮化镓的低缺陷层上。
13.根据权利要求12所述的过程，还包括在所述增强型GaN FET的所述栅极的所述p型III-N半导体材料层上形成金属层。
14.根据权利要求11所述的过程，其中形成所述增强型GaN FET的所述步骤包括：通过在栅极电介质层上方形成金属栅极以形成所述增强型GaN FET的绝缘栅极，所述栅极电介质层在阻挡层上方，所述阻挡层在氮化镓的低缺陷层上。
15.根据权利要求11所述的过程，其中形成所述增强型GaN FET的所述步骤包括：在氮化镓的低缺陷层上的阻挡层中形成凹槽，以及在所述凹槽中形成所述增强型GaN FET的栅极。
16.根据权利要求11所述的过程，其中形成所述增强型GaN FET的所述步骤包括：在氮化镓的低缺陷层上的阻挡层上形成氮化镓的盖层。
17.根据权利要求11所述的过程，其中形成所述耗尽型GaN FET的所述步骤包括：形成氮化镓的低缺陷层并在所述低缺陷层上形成阻挡层，所述阻挡层包括的半导体材料选自包括以下项的组中：AlxGa1-xN和InxAlyGa1-x-yN。
18.根据权利要求11所述的过程，其中形成所述耗尽型GaN FET的所述步骤包括形成金属的耗尽型栅极。
19.根据权利要求11所述的过程，其中形成所述耗尽型GaN FET的所述步骤包括形成III-N半导体材料的耗尽型栅极。
20.根据权利要求11所述的过程，其中所述耗尽型GaN FET和所述增强型GaN FET在相同的衬底和III-N半导体材料的相同的层结构上形成。
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916427B2 (en) 2013-05-03 2014-12-23 Texas Instruments Incorporated FET dielectric reliability enhancement
JP6023825B2 (ja) * 2015-01-14 2016-11-09 株式会社豊田中央研究所 半導体装置
US20160293596A1 (en) * 2015-03-30 2016-10-06 Texas Instruments Incorporated Normally off iii-nitride transistor
US10205313B2 (en) 2015-07-24 2019-02-12 Symptote Technologies, LLC Two-transistor devices for protecting circuits from sustained overcurrent
JP6651186B2 (ja) 2015-09-21 2020-02-19 シンプトート テクノロジーズ エルエルシー 回路を保護するための単一トランジスタデバイスおよびそのための自己触媒電圧変換
US9685545B2 (en) * 2015-11-25 2017-06-20 Texas Instruments Incorporated Isolated III-N semiconductor devices
WO2018182704A1 (en) * 2017-03-31 2018-10-04 Intel Corporation Enhancement/depletion device pairs and methods of producing the same
US10734882B2 (en) * 2018-02-09 2020-08-04 Delta Electronics, Inc. Conversion circuit
US10784770B2 (en) 2018-02-09 2020-09-22 Delta Electronics, Inc. Conversion circuit
US11309887B2 (en) 2018-02-09 2022-04-19 Delta Electronics, Inc. Conversion circuit
US10784768B2 (en) 2018-02-09 2020-09-22 Delta Electronics, Inc. Conversion circuit and conversion circuitry
KR102395268B1 (ko) 2018-03-14 2022-05-04 엠베리온 오와이 표면 ｍｅｓｆｅｔ
US10516043B1 (en) * 2018-07-19 2019-12-24 Cree, Inc. Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors
US10840798B1 (en) 2018-09-28 2020-11-17 Dialog Semiconductor (Uk) Limited Bidirectional signaling method for high-voltage floating circuits
CN109742072B (zh) * 2019-01-04 2019-08-16 苏州汉骅半导体有限公司 集成增强型和耗尽型的hemt及其制造方法
JP7300840B2 (ja) 2019-02-04 2023-06-30 ローム株式会社 窒化物半導体装置の製造方法
WO2020191357A1 (en) * 2019-03-21 2020-09-24 Transphorm Technology, Inc. Integrated design for iii-nitride devices
US11101378B2 (en) 2019-04-09 2021-08-24 Raytheon Company Semiconductor structure having both enhancement mode group III-N high electron mobility transistors and depletion mode group III-N high electron mobility transistors
US11081578B2 (en) 2019-05-07 2021-08-03 Cambridge Gan Devices Limited III-V depletion mode semiconductor device
US11658236B2 (en) 2019-05-07 2023-05-23 Cambridge Gan Devices Limited III-V semiconductor device with integrated power transistor and start-up circuit
US11955488B2 (en) * 2019-05-07 2024-04-09 Cambridge Gan Devices Limited III-V semiconductor device with integrated power transistor and start-up circuit
US11302785B2 (en) 2019-06-18 2022-04-12 Texas Instruments Incorporated Method for testing a high voltage transistor with a field plate
US11545566B2 (en) 2019-12-26 2023-01-03 Raytheon Company Gallium nitride high electron mobility transistors (HEMTs) having reduced current collapse and power added efficiency enhancement
US11362190B2 (en) 2020-05-22 2022-06-14 Raytheon Company Depletion mode high electron mobility field effect transistor (HEMT) semiconductor device having beryllium doped Schottky contact layers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252429A (ja) * 1999-02-26 2000-09-14 Hitachi Ltd 静電気保護回路および半導体集積回路
CN101897029A (zh) * 2007-12-10 2010-11-24 特兰斯夫公司 绝缘栅e模式晶体管
CN102683405A (zh) * 2011-03-18 2012-09-19 富士通半导体股份有限公司 半导体器件、制造方法以及晶体管电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5313082A (en) 1993-02-16 1994-05-17 Power Integrations, Inc. High voltage MOS transistor with a low on-resistance
JP3249293B2 (ja) 1994-05-30 2002-01-21 富士通株式会社 半導体集積回路
JP3493956B2 (ja) 1997-06-04 2004-02-03 株式会社村田製作所 論理回路
US20010015437A1 (en) * 2000-01-25 2001-08-23 Hirotatsu Ishii GaN field-effect transistor, inverter device, and production processes therefor
US7202528B2 (en) * 2004-12-01 2007-04-10 Semisouth Laboratories, Inc. Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making
JP5299805B2 (ja) * 2005-08-29 2013-09-25 学校法人 名城大学 トランジスタ
WO2007109301A2 (en) * 2006-03-20 2007-09-27 International Rectifier Corporation Merged gate cascode transistor
US7501670B2 (en) 2007-03-20 2009-03-10 Velox Semiconductor Corporation Cascode circuit employing a depletion-mode, GaN-based FET
KR101631454B1 (ko) 2008-10-31 2016-06-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 논리회로
JP2011165749A (ja) * 2010-02-05 2011-08-25 Panasonic Corp 半導体装置
JP2012028705A (ja) * 2010-07-27 2012-02-09 Sumitomo Electric Ind Ltd 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252429A (ja) * 1999-02-26 2000-09-14 Hitachi Ltd 静電気保護回路および半導体集積回路
CN101897029A (zh) * 2007-12-10 2010-11-24 特兰斯夫公司 绝缘栅e模式晶体管
CN102683405A (zh) * 2011-03-18 2012-09-19 富士通半导体股份有限公司 半导体器件、制造方法以及晶体管电路

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