CN104335336A - 覆晶接合器以及覆晶接合方法 - Google Patents
覆晶接合器以及覆晶接合方法 Download PDFInfo
- Publication number
- CN104335336A CN104335336A CN201380027231.5A CN201380027231A CN104335336A CN 104335336 A CN104335336 A CN 104335336A CN 201380027231 A CN201380027231 A CN 201380027231A CN 104335336 A CN104335336 A CN 104335336A
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- semiconductor chip
- temperature
- joining tool
- chip bonding
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- 238000000034 method Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 199
- 238000001816 cooling Methods 0.000 claims abstract description 73
- 238000005304 joining Methods 0.000 claims description 147
- 238000010521 absorption reaction Methods 0.000 claims description 65
- 238000012546 transfer Methods 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 30
- 230000007246 mechanism Effects 0.000 claims description 23
- 239000011159 matrix material Substances 0.000 claims description 9
- 230000000694 effects Effects 0.000 claims description 7
- 230000008859 change Effects 0.000 claims description 5
- 239000011347 resin Substances 0.000 description 46
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- 238000001179 sorption measurement Methods 0.000 description 41
- 238000002844 melting Methods 0.000 description 20
- 230000008018 melting Effects 0.000 description 20
- 230000015572 biosynthetic process Effects 0.000 description 10
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- 238000012937 correction Methods 0.000 description 1
- 238000004512 die casting Methods 0.000 description 1
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Classifications
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- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
- B23K3/08—Auxiliary devices therefor
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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Abstract
本发明提供一种可缩短接合时间而又不降低接合质量的覆晶接合器。此覆晶接合器包括:吸附反转夹套(30),使半导体芯片(20)反转;以及接合工具(50),自吸附反转夹套(30)接收已由吸附反转夹套(30)反转的半导体芯片(20)并将此半导体芯片接合于电路基板(65);且吸附反转夹套(30)在内部具有使冷却空气流通来对吸附反转夹套(30)进行冷却的冷却流路。
Description
技术领域
本发明涉及一种覆晶接合器的构造、以及使用覆晶接合器的覆晶接合方法。
背景技术
作为将半导体芯片封装在电路基板的方法而广泛采用覆晶接合,即在半导体芯片形成称作凸块(bump)的突起电极,并将半导体芯片直接连接于电路基板。覆晶接合是对半导体芯片的电路面利用焊料等材料形成多个凸块(突起电极),并通过加热熔融将此凸块接合于电路基板上所形成的多个电极,由此将半导体芯片与电路基板接合,与现有的引线接合(wire bonding)连接方式相比,具有可减小封装面积,而且电气特性良好,不需要模铸密封等优点。
在覆晶接合中,为确保半导体芯片与电路基板的接合部的连接可靠性,而必须藉由底填充(under fill)等对半导体芯片与电路基板之间的空隙进行树脂密封,但若使用底填充则有液状树脂的填充耗费时间等问题,而且在近年来的半导体芯片与电路基板之间的间隙越来越窄的现状下,也有难以注入液状树脂的问题。因此,提出如下接合方法:预先在半导体芯片的表面贴附绝缘树脂膜(非导电膜(non-conductive film,NCF)),在将半导体芯片与电路基板接合的同时使树脂熔融、硬化,由此对半导体芯片与电路基板之间进行树脂密封。
此方法中,预先将绝缘树脂膜(NCF)贴附于半导体芯片的表面,将绝缘树脂膜(NCF)与半导体芯片一同吸附于保持构件而进行拾取(pick up)之后,使保持构件旋转而以绝缘树脂膜(NCF)的面成为下侧的方式使半导体芯片反转,且使接合工具接触于半导体芯片的贴附有绝缘树脂膜(NCF)的面的相反侧的面来使半导体芯片吸附于接合工具,并将半导体芯片自保持构件交付至接合工具。因此,在交付半导体芯片时,半导体芯片的贴附有绝缘树脂膜(NCF)的面成为接触于保持构件的上侧的面的状态,交付至接合工具的半导体芯片的绝缘树脂膜(NCF)的面成为下侧(电路基板侧)。其后,若藉由接合工具将半导体芯片按压于电路基板,并且使接合工具的温度上升至凸块的熔融温度(300℃左右)为止,则在凸块熔融的同时绝缘树脂膜(NCF)熔融并进入至半导体芯片与电路基板之间。然后,若使接合工具上升,则凸块与绝缘树脂膜(NCF)的温度降低而使得熔融的凸块的金属与熔融的树脂硬化,从而结束半导体芯片向电路基板的接合。
在接合结束时接合工具成为300℃左右的高温,因此若在此状态下自保持构件接收下一半导体芯片,则在高温的接合工具接触于半导体芯片时,贴附在半导体芯片表面(保持构件侧的面)的绝缘树脂膜(NCF)被加热、熔融而附着在保持构件表面。因此,必须在暂时将高温状态的接合工具冷却至绝缘树脂膜(NCF)的熔融温度以下(例如50℃左右)之后自保持构件接收下一半导体芯片,且在再次使接合工具的温度上升之后进行接合。然而,接合工具的冷却大多是使用常温(25~30℃左右)的空气来进行的,为将300℃左右的高温状态的接合工具冷却至50℃左右而会耗费时间,从而有整体的接合时间变长的问题。
由此,提出如下方法:在不使保持构件与接合工具接触的状态下,即在隔断自接合工具向保持构件传递热的状态下,藉由将半导体芯片吸引于接合工具的表面来将半导体芯片自保持构件交付至接合工具,且藉由不对接合工具进行冷却而持续进行接合来缩短接合时间(例如,参照专利文献1)。
现有技术文献
专利文献
专利文献1:日本专利特开2012-174861号公报
发明内容
发明解决的课题
此外,覆晶接合中,为一次接合多个电极而必须将半导体芯片与电路基板的相对位置准确地对准。然而,如专利文献1记载的现有技术那样,在与保持构件空开间隙的状态下使半导体芯片吸附于接合工具的情形时,半导体芯片在暂时浮游于空中之后吸附于接合工具的表面,因此有半导体芯片的位置、方向大幅偏移而接合质量降低的问题。
由此,本发明的目的在于提供一种可缩短接合时间而又不降低接合质量的覆晶接合器。
解决课题的技术手段
本发明的覆晶接合器的特征在于包括:反转机构,使半导体芯片反转;接合工具,自反转机构接收已由反转机构反转的半导体芯片并将上述半导体芯片接合于基板;以及冷却机构,对反转机构进行冷却。
本发明的覆晶接合器中亦较佳为:反转机构包括保持已反转的半导体芯片的保持构件,冷却机构在接合工具接收半导体芯片之前预先将保持构件的温度冷却至规定的温度为止。
本发明的覆晶接合器中亦较佳为,保持构件的热容大于接合工具的热容。
本发明的覆晶接合器中,保持构件较佳为在吸附并反转半导体芯片的状态下将其交付至接合工具的吸附反转夹套(collet),保持构件亦较佳为使半导体芯片在反转的状态下移动,且将半导体芯片在反转的状态下交付至接合工具的移送平台。
本发明的覆晶接合器中亦较佳为,冷却机构对保持构件的内表面或外表面进行冷却。
本发明的覆晶接合器中亦较佳为,冷却机构包括:基体部;以及冷却构件,包含接地板及散热构件,上述接地板具有保持构件的表面接地的接地面,上述散热构件安装在上述接地板;且冷却构件藉由仿照保持构件的表面的方向的方式而可以改变接地面的方向的支撑机构而支撑在基体部。
本发明的覆晶接合器中亦较佳为,冷却构件的热容大于保持构件的热容,散热构件较佳为安装在接地板的接地面的相反侧的面,散热构件为散热片(fin),且较佳为包括对散热片进行冷却的冷却风扇。
本发明的覆晶接合器中较佳为,支撑机构以绕沿接地面的第一轴、及沿接地面且与第一轴正交的第二轴这2个轴旋转自如的方式将接地板支撑于基体部,且较佳为上述覆晶接合器包括冷却喷嘴,上述冷却喷嘴设置在基体部,对表面接地于接地面的保持构件喷出冷却空气,接地板的接地面较佳为在保持构件的表面接地时,自保持构件向接地板产生热传导。
本发明的覆晶接合方法的特征在于,其包括准备覆晶接合器的步骤,上述覆晶接合器包括:反转机构,使半导体芯片反转;接合工具,自反转机构接收已由反转机构反转的半导体芯片并将上述半导体芯片接合于基板;以及冷却机构,对反转机构进行冷却;以及冷却步骤,在接合工具接收半导体芯片之前预先藉由冷却机构将保持构件的温度冷却至规定的温度。
发明的效果
本发明发挥可提供能缩短接合时间而又不降低接合质量的覆晶接合器的效果。
附图说明
[图1]表示本发明的实施方式的覆晶接合器的构成的立视图。
[图2]是图1所示的覆晶接合器的吸附反转夹套的剖面图。
[图3]是表示利用本发明的实施方式的覆晶接合器的接合步骤的流程图。
[图4]是表示利用本发明的覆晶接合器的接合步骤中的接合工具的温度与吸附反转夹套的温度变化的曲线图。
[图5]是表示利用现有技术的覆晶接合器的接合步骤中的接合工具的温度与吸附反转夹套的温度变化的曲线图。
[图6]是表示利用本发明的覆晶接合器的接合工具的半导体芯片接收温度相对于吸附反转夹套的冷却温度的关系的曲线图。
[图7]是表示利用本发明的覆晶接合器的吸附反转夹套、半导体芯片及接合工具的大小的立视图。
[图8]是表示本发明的另一实施方式的覆晶接合器的构成的立视图。
[图9]是表示图8所示的覆晶接合器的冷却平台的构成的立体图。
[图10]是图8所示的覆晶接合器的冷却平台的剖面图。
[图11]是图8所示的覆晶接合器的冷却平台的俯视图。
[图12]是表示利用本发明的另一实施方式的覆晶接合器的接合步骤的流程图。
[图13]是表示利用本发明的另一实施方式的覆晶接合器的接合步骤的流程图。
[图14]是表示利用本发明的另一实施方式的覆晶接合器的接合步骤的流程图。
[图15]是表示图8所示的覆晶接合器的另一冷却平台的构成的剖面图。
[图16]是表示图8所示的覆晶接合器的另一冷却平台的构成的俯视图。
[图17]是表示本发明的又一实施方式的覆晶接合器的构成的立视图。
[图18]是图17所示的覆晶接合器的移送平台的剖面图。
[图19]是表示利用本发明的又一实施方式的覆晶接合器的接合步骤的流程图。
[图20]是表示利用本发明的又一实施方式的覆晶接合器的接合步骤的流程图。
[图21]是表示本发明的又一实施方式的覆晶接合器的构成的立视图。
具体实施方式
以下,参照图式对本发明的实施方式进行说明。如图1所示那样,本实施方式的覆晶接合器101是在拾取表面22上贴附有绝缘树脂膜(NCF)21的半导体芯片20并使其反转之后,将此半导体芯片20封装(接合)在接合平台60上的电路基板65上。本实施方式的覆晶接合器101包括:拾取平台10,在上表面11保持半导体芯片20;吸附反转夹套30,作为反转机构,自拾取平台10的上表面11吸附拾取半导体芯片20,并使拾取的半导体芯片20反转;以及接合工具50,自吸附反转夹套30接收已反转的半导体芯片20,并将此半导体芯片20接合于吸附固定在接合平台60上的电路基板65。
吸附反转夹套30包括:夹套主体31,作为保持构件,具有吸附半导体芯片20的吸附面32;以及旋转移动轴33,安装有吸附面32的相反侧的夹套主体31的端部。旋转移动轴33藉由未图示的旋转移动机构而在上下左右方向移动、以及绕中心轴旋转。吸附反转夹套30构成为藉由旋转移动机构而使旋转移动轴33可在上下左右移动或旋转,藉此使夹套主体31在上下左右移动并且绕旋转移动轴33旋转。
如图2所示那样,旋转移动轴33设置有:圆筒状的冷却空气流路34,在上述旋转移动轴33的内部沿旋转移动轴33的轴方向伸展;以及冷却空气喷嘴35,自冷却空气流路34向旋转移动轴33的半径方向伸展,在夹套主体31设置有:第一冷却空气流路37,与冷却空气喷嘴35连通,自旋转移动轴33向夹套主体31的吸附面32伸展;以及第二冷却空气流路38,与第一冷却空气流路37连通,且在沿吸附面32的方向伸展。如图2所示那样,流入至旋转移动轴33内部的冷却空气流路34的冷却空气,自冷却空气喷嘴35通过第一冷却空气流路37、第二冷却空气流路38流出至夹套主体31外部,藉此对夹套主体31进行冷却。本实施方式中,对藉由冷却空气冷却夹套主体31的情况进行说明,但冷却媒体并不限定于空气,亦可使用水等液体。冷却空气流路34、冷却空气喷嘴35、第一冷却空气流路37、第二冷却空气流路38构成冷却机构。
如图1所示那样,接合工具50安装在接合头40,藉由接合头40而沿水平、垂直方向移动。又,接合工具50包括吸附半导体芯片20的前端的吸附面51(图1中的下侧面),在内部内置有未图示的脉冲加热器,此脉冲加热器可将半导体芯片20加热至可使形成在半导体芯片20的凸块熔融的温度(300℃~350℃)。
以下,参照图3、图4对藉由本实施方式的覆晶接合器101将半导体芯片20接合在电路基板65的步骤进行说明。再者,图4中为与其后不对吸附反转夹套30的夹套主体31进行冷却的现有的覆晶接合器的接合步骤进行对比,利用虚线a记载藉由现有的覆晶接合器进行覆晶接合时的接合工具50的温度TB的变化,且将其接合周期的时刻记载为时刻t11~时刻t16。现有技术的覆晶接合器与本实施方式的覆晶接合器101的对比说明,将于参照图5对现有技术的覆晶接合器的接合步骤进行说明之后进行。
如图3(a)所示那样,在拾取平台10的上表面11保持对晶圆进行切割而得的半导体芯片20。在半导体芯片20的接合面(图3中的上侧面)形成有未图示的凸块,并且贴附有绝缘树脂膜(NCF)21。首先,如图3(a)的箭头81所示那样,吸附反转夹套30下降至欲拾取的半导体芯片20的接合面。如参照图2所说明那样,吸附反转夹套30由流过旋转移动轴33的冷却空气流路34、冷却空气喷嘴35、第一冷却空气流路37、第二冷却空气流路38的冷却空气冷却,因此吸附反转夹套30的夹套主体31的温度TC,成为图4(b)所示的初始状态的温度TC1(例如30℃左右)。
如图3(b)所示那样,吸附反转夹套30向半导体芯片20下降,当夹套主体31前端的吸附面32接触于半导体芯片20的接合面上所贴附的绝缘树脂膜(NCF)21时,绝缘树脂膜(NCF)21吸附在夹套主体31的吸附面32。此时,夹套主体31的温度TC成为较绝缘树脂膜(NCF)21的熔融温度(60℃~70℃)低的温度TC1(例如30℃左右),因此即便绝缘树脂膜(NCF)21吸附在吸附面32,绝缘树脂膜(NCF)21亦会成为不熔融的状态。
如图3(c)所示那样,若使吸附反转夹套30如箭头82那样上升,则自拾取平台10的上表面11一同拾取绝缘树脂膜(NCF)21与半导体芯片20。
如图3(d)所示那样,藉由在拾取半导体芯片20之后,使吸附反转夹套30的旋转移动轴33沿图3(d)的箭头83的方向旋转180度,而使朝向下侧的夹套主体31的吸附面32朝上,以使半导体芯片20的表面22(贴附有绝缘树脂膜(NCF)21的接合面的相反侧的面)在图3(d)中成为上方的方式使半导体芯片20反转。
如图3(e)所示那样,在将吸附反转夹套30的吸附面32保持为上方来保持半导体芯片20的状态下,使吸附反转夹套30移动至向接合工具50交付半导体芯片20的交付位置为止。吸附反转夹套30移动至半导体芯片20的交付位置之后,接合头40在图4(b)所示的时刻t1使接合工具50的前端的吸附面51接触于半导体芯片20的表面22(贴附有绝缘树脂膜(NCF)21的接合面的相反侧的面)。然后,停止利用吸附反转夹套30吸引保持半导体芯片20,且开始利用接合工具50吸附半导体芯片20,藉此将半导体芯片20自吸附反转夹套30的吸附面32交付至接合工具50的吸附面51。
图4(b)所示的时刻t1下的接合工具50的温度TB如图4(a)的实线A所示那样成为温度TB2。温度TB2为较吸附反转夹套30的夹套主体31的初始温度TC1(30℃左右)高,例如100℃左右的温度。而且,若在时刻t1接合工具50的前端的吸附面51接触于半导体芯片20的表面22(贴附有绝缘树脂膜(NCF)21的接合面的相反侧的面),则热自高温的接合工具50经由半导体芯片20移动至吸附反转夹套30,从而夹套主体31的温度自初始温度即温度TC1(30℃左右)开始急速上升。在将半导体芯片20自吸附反转夹套30的吸附面32交付至接合工具50的吸附面51为止的极短的时间(例如0.1秒~0.2秒)的期间,夹套主体31的温度如图4(b)所示那样上升至温度TC2(50℃左右)。此温度TC2(50℃左右)为较绝缘树脂膜(NCF)21的熔融温度(60℃~70℃)低的温度,因此在将半导体芯片20自吸附反转夹套30的吸附面32交付至接合工具50的吸附面51的期间绝缘树脂膜(NCF)不熔融,从而不会在夹套主体31的吸附面32上熔融而附着树脂。
接合工具50在图4(a)所示的时刻t1自吸附反转夹套30接收到半导体芯片20之后,接合头40如图3(f)所示那样使接合工具50上升,如图3(g)所示那样,在图4(a)所示的时刻t101将半导体芯片20按压在吸附固定于接合平台60上的电路基板65上的规定位置。然后,接合工具50在自图4(a)的时刻t101至时刻t102的期间,藉由内置的脉冲加热器而使其温度上升至可将形成在半导体芯片20上的凸块熔融的温度(300℃~350℃)。其后,在自图4(a)所示的时刻t102至时刻t103的期间,接合头40藉由高温(300℃~350℃)状态的接合工具50而对半导体芯片20与绝缘树脂膜(NCF)21进行加热、按压,而使形成在半导体芯片20上的凸块以及绝缘树脂膜(NCF)21熔融。其后,接合头40停止接合工具50对半导体芯片20的吸附,并且使内置在接合工具50中的脉冲加热器停止,并使接合工具50上升。此时,本实施方式的覆晶接合器101中,藉由未图标的冷却装置对接合工具50进行冷却。如此一来,自图4(a)所示的时刻t103起接合工具50的温度TB开始降低,并在图4(b)所示的时刻t2成为初始温度即温度TB2(100℃左右)。
另一方面,吸附反转夹套30的夹套主体31如参照图2所说明那样,由流过旋转移动轴33的冷却空气流路34、冷却空气喷嘴35、第一冷却空气流路37、第二冷却空气流路38的冷却空气冷却,因此若在图4(b)所示的时刻t1将半导体芯片20交付至接合工具50,且如图3(f)所示那样接合工具50离开夹套主体31而不自接合工具50导入热,则如图4(b)的线D所示那样此夹套主体31的温度降低。而且,夹套主体31的温度TC在图4(b)所示的时刻t2降低至初始温度即温度TC1(30℃左右)。
以下,重复如下步骤而将多个半导体芯片20依序接合在电路基板65上,此步骤是藉由降低至初始温度TC1(30℃左右)的吸附反转夹套30拾取半导体芯片20并使其反转,而将半导体芯片20交付至初始温度为温度TB1(100℃左右)的接合工具50来进行接合。
其次,参照图5对藉由不对吸附反转夹套30的夹套主体31进行冷却的现有的覆晶接合器进行覆晶接合时的接合工具50与吸附反转夹套30的夹套主体31的温度TC的变化进行说明。
如图5所示那样,在不对吸附反转夹套30的夹套主体31进行冷却的现有的覆晶接合器的情形时,如图5(a)所示那样,在初始状态下,接合工具50被冷却至温度TB为较绝缘树脂膜(NCF)21的熔融温度(60℃~70℃)低的温度TB1(50℃左右)。另一方面,在初始状态下,吸附反转夹套30的夹套主体31的温度TC,如图5(b)所示那样成为与室温同程度的温度TC1(30℃左右)。而且,在图5所示的时间t11,如图3(e)所示那样,接合工具50接触于吸附反转夹套30的夹套主体31的吸附面32上所吸附的半导体芯片20,在自吸附反转夹套30接收半导体芯片20时,夹套主体31的温度TC藉由接合工具50的初始温度TB1(50℃左右)与夹套主体31的初始温度TC1(30℃左右)的温度差而略有上升。在不对夹套主体31进行冷却的现有的覆晶接合器中,使接合工具50的温度TB为较本实施方式的覆晶接合器101的情形时的温度TB2(100℃左右)低的温度TB1(50℃左右),来将半导体芯片20自吸附反转夹套30交付至接合工具50,因此此时的温度上升远小于参照图4(a)、图4(b)所说明的本实施方式的覆晶接合器101的情形。
现有技术的覆晶接合器中,在图5(b)所示的时间t111使接合工具50接地于电路基板65,在自时间t111至t112的期间使接合工具50的温度TB上升至可将形成在半导体芯片20上的凸块熔融的温度(300℃~350℃),其后,在自图5(a)所示的时刻t112至时刻t113的期间,藉由高温(300℃~350℃)状态的接合工具50对半导体芯片20与绝缘树脂膜(NCF)21进行加热、按压,而使形成在半导体芯片20上的凸块以及绝缘树脂膜(NCF)21熔融。其后,接合头40停止接合工具50对半导体芯片20的吸附,并且使内置在接合工具50中的脉冲加热器停止,且使接合工具50上升。此时现有技术的覆晶接合器亦藉由未图标的冷却装置对接合工具50进行冷却。如此一来,自图5(a)的时刻t113起接合工具50的温度TB开始降低,并在图5(b)所示的时刻t12成为初始温度即温度TB1(50℃左右)的温度。
另一方面,现有技术的覆晶接合器中,不对吸附反转夹套30的夹套主体31进行冷却,因此即便在图5(b)所示的时刻t11结束半导体芯片20自吸附反转夹套30向接合工具50的交付,夹套主体31的温度亦几乎不降低,维持较初始温度TC1(30℃左右)略高的温度。因此,如图5(b)所示的单点划线b所示那样,在时刻t12~t18每当自吸附反转夹套30向接合工具50交付半导体芯片20时,夹套主体31的温度均会稍许上升,最终成为温度TC3。温度TC3为与接合工具50接收半导体芯片20时的温度即温度TB1(50℃左右)相同的温度。
因此,不对夹套主体31进行冷却的现有技术的覆晶接合器中,接合工具50的半导体接收温度必须使接合工具50的温度自接合时的300℃~350℃降低至温度TB1(50℃左右)。但是,通常接合工具50的冷却是藉由喷出室温(25℃~30℃左右)的空气来进行的,因此在降低至温度TB1(50℃左右)的冷却时间与如本实施方式的覆晶接合器那样降低至温度TB2(100℃左右)的冷却时间之间呈现大差距。
其次,参照图4(a),对不冷却夹套主体31的现有技术的覆晶接合器与本实施方式的覆晶接合器101的接合步骤的差异进行说明。
如图4(a)的点线a所示那样,在现有技术的覆晶接合器中,使接合工具50的温度自TB3(300℃~350℃)降低至TB1(50℃左右)的时间(图4所示的时刻t103与时刻t12之间)、与本实施方式的覆晶接合器101中使接合工具50的温度自温度TB3(300℃~350℃)降低至TB2(100℃左右)的时间(图4所示的时刻t103与时刻t2之间)的时间差Δt为4秒~5秒左右。藉由现有技术的覆晶接合器拾取半导体芯片20至进行接合并完成接合工具50的冷却为止的周期时间(图4所示的时刻t11与t12之间)为14秒~15秒左右,因此在本实施方式的覆晶接合器101中,在已对夹套主体31进行冷却的情形时,可将覆晶接合的周期时间(图4所示的时刻t1与时刻t2之间)自14秒~15秒缩短至10秒左右而缩短至约2/3。又,本实施方式的覆晶接合器101中,在使接合工具50接触于吸附保持在吸附反转夹套30的吸附面32上的半导体芯片20之后,松开吸附反转夹套30对半导体芯片20的吸附保持而将半导体芯片20交付至接合工具50,因此可抑制如专利文献1记载的现有技术的覆晶接合器那样在交付半导体芯片20时半导体芯片20的位置大幅偏移,从而可维持接合质量。
即,在本实施方式的覆晶接合器101中,藉由对吸附反转夹套30的夹套主体31进行冷却,而可使接合工具50接收半导体芯片20的接收温度TB2较现有技术高,且可缩短接合后的接合工具50的冷却时间,因此可大幅缩短覆晶接合的周期时间。
如以上所说明那样,本实施方式的覆晶接合器101发挥可缩短接合时间而又不降低接合质量的效果。
下面,参照图6、图7,对接合工具50接收半导体芯片20的接收温度TB2(以图4(a)的线A所示的接合工具50的冷却后的温度TB2)相对于吸附反转夹套30的夹套主体31的冷却温度TC1(以图4(b)的线D所示的夹套主体31的冷却后的温度TC1)的关系更详细地进行说明。
如图4(b)的曲线D所示那样,夹套主体31的温度上升是因如图7(a)、图7(b)所示那样,热自温度TB2的高温的接合工具50向温度TC1的低温的夹套主体31移动而产生。图7(a)、图7(b)中,空心箭头表示热移动的方向,其宽度表示热移动量的大小。而且,若温度上升后的夹套主体31的温度TC2接近于绝缘树脂膜(NCF)21的熔融温度(60℃~70℃),则与夹套主体31的吸附面32接触的绝缘树脂膜(NCF)21产生软化、熔融,因熔融而使树脂附着在夹套主体31的吸附面32上。因此,温度上升后的夹套主体31的温度TC2,必须为绝缘树脂膜(NCF)21不产生软化、熔融的50℃左右的温度。另一方面,为缩短覆晶接合的周期时间,较好为而使交付半导体芯片20时的接合工具50的温度TB2尽可能高。
由此,夹套主体31的冷却温度TC1与接合工具50接收半导体芯片20的接收温度TB2,例如亦可藉由图6的曲线图来选定。图6的线e为如下的线:如图7(a)所记载那样,在交付的半导体芯片20的宽度大至D1,从而在交付半导体芯片20时自接合工具50移动至夹套主体31的热量大,且夹套主体31的温度TC易于上升的情形时,规定接合工具50接收半导体芯片20的接收温度TB2相对于使夹套主体31的温度TC2为50℃以下的夹套主体31的冷却温度TC1的关系,图6的线f为如下的线:如图7(b)所记载那样,在交付的半导体芯片20的宽度小至D2,从而在交付半导体芯片20时自接合工具50移动至夹套主体31的热量小,且夹套主体31的温度TC难以上升的情形时,规定接合工具50接收半导体芯片20的接收温度TB2相对于使夹套主体31的温度TC2为50℃以下的夹套主体31的冷却温度TC1的关系。
在未对夹套主体31进行冷却的情形时,如在现有技术的覆晶接合中所说明那样,接合工具50接收半导体芯片20的接收温度TB2为50℃(图6的点g)。此在半导体芯片20的宽度大的情形及小的情形均相同。
在对夹套主体31进行冷却的情形时,如图6的线e所示那样在半导体芯片20的宽度大的情形时,当夹套主体31的冷却温度TC1例如为30℃时,即便在将接合工具50接收半导体芯片20的接收温度TB2提高至100℃的情形时,夹套主体的温度上升亦成为50℃以下。进而,在藉由温度低的制冷剂对夹套主体31进行冷却,而使夹套主体31的温度降低至10℃左右的情形时,即便在将接合工具50接收半导体芯片20的接收温度TB2提高至100℃的情形时,夹套主体的温度上升亦成为50℃以下。
又,在对夹套主体31进行冷却的情形时,如图6的线f所示那样在半导体芯片20的宽度小的情形时,当夹套主体31的冷却温度TC1例如为30℃时,即便在将接合工具50接收半导体芯片20的接收温度TB2提高至150℃的情形时,夹套主体的温度上升亦成为50℃以下。进而,在藉由温度低的制冷剂对夹套主体31进行冷却,而使夹套主体31的温度降低至10℃左右的情形时,即便在将接合工具50接收半导体芯片20的接收温度TB2提高至250℃的情形时,夹套主体的温度上升亦成为50℃以下。
即,使夹套主体31的冷却温度TC1越低,则越可提高接合工具50接收半导体芯片20的接收温度TB2,从而可使接合的周期时间更短。又,若交付的半导体芯片20的大小变小,则即便夹套主体31的冷却温度TC1为相同的温度,由于在交付半导体芯片20时自接合工具50移动至夹套主体31的热量减少,因此可使接合工具50接收半导体芯片20的接收温度TB2更高,从而可使接合的周期时间更短。
在夹套主体31的热容大于接合工具50的热容的情形时,即便在自接合工具50移动至夹套主体31的热量相同的情形时,夹套主体31的温度上升亦变小,因此夹套主体31的热容相对于接合工具50的热容越大,则越可提高接合工具50接收半导体芯片20的接收温度TB2,从而可使接合的周期时间更短。
夹套主体31的冷却温度TC1、接合工具50接收半导体芯片20的接收温度TB2,亦可考虑上述特性并藉由例如试验等来决定。再者,图6是表示夹套主体31的冷却温度TC1、接合工具50接收半导体芯片20的接收温度TB2的关系的特性的概念图,此关系、特性亦存在图6所示的直线以外的情形。
下面,参照图8至图14对本发明的另一实施方式进行说明。对与参照图1至图7所说明的部分相同的部分附上相同的符号并省略其说明。
如图8所示那样,本实施方式的覆晶接合器102包括冷却平台110作为冷却机构,此冷却平台110是使吸附反转夹套30的吸附面32与其接触来对夹套主体31进行冷却。
如图9、图10所示那样,冷却平台110包括:作为基体部的框架112;以及冷却构件116,包含接地板114及作为散热构件的散热片115,此接地板114具有夹套主体31前端的吸附面32接地的接地面114a,此散热片115安装在接地板114的接地面114a的相反侧的面;接地板114藉由支撑机构200以可改变接地面114a的方向的方式安装在框架112上。又,在框架112的侧面安装有:冷却喷嘴119,经由支架(bracket)121来安装,且沿接地面114a的表面附近自吹出孔120喷出冷却空气;冷却空气供给管117、冷却空气供给管118,对冷却喷嘴119供给冷却空气。又,在冷却构件116的散热片115的下侧,配置有对散热片115喷出冷却空气的冷却风扇122。
如图10、图11所示那样,支撑机构200包括:四角环状的中间框架113,以绕通过接地板114的中心125且与沿接地面114a的X轴126正交的第二轴即Y轴127旋转自如的方式,藉由销123而安装在框架112的四方形开口的内侧;以及销124,安装在中间框架113的内侧,绕通过接地板114的中心125且沿接地面114a的第一轴即X轴126旋转自如地支撑接地板114。因此,接地板114相对于框架112,以绕通过中心125的X轴126以及Y轴127旋转自如、且可改变接地面114a相对于框架112的方向、或接地面114a相对于框架112的倾斜度的方式受到支撑。又,如图10所示那样,散热片115固定在接地板114的下侧面(接地面114a的相反侧的面),与接地板114一体地移动,因此包含接地板114与散热片115的冷却构件116,整体上绕通过接地板114的中心125的X轴126以及Y轴127旋转自如。
作为接地板114的表面的接地面114a,成为夹套主体31前端的吸附面32可密接的平面,包含接地板114与散热片115的冷却构件116的热容,以成为大于夹套主体31的热容的方式而构成。
参照图12至图14对利用包括以如上方式构成的冷却平台110的覆晶接合器102的覆晶接合的动作进行说明。对与参照图1至图7所说明的部分相同的部分附上相同的符号并省略说明。
如图12(a)所示那样,在初始状态下,吸附反转夹套30的吸附面32接触于冷却平台110的上表面而被冷却,例如成为30℃左右的常温。如图12(b)的箭头91所示那样,藉由未图示的旋转移动机构使旋转移动轴33向上下左右移动,而使吸附反转夹套30的夹套主体31移动至欲拾取的半导体芯片20的正上方,如图12(b)的箭头92所示那样,使吸附反转夹套30下降至要拾取的半导体芯片20上。如图12(c)所示那样,在吸附反转夹套30的夹套主体31的吸附面32接触于半导体芯片20的表面的绝缘树脂膜(NCF)21之后,吸附反转夹套30吸附绝缘树脂膜(NCF)21,如图12(d)的箭头93所示那样拾取绝缘树脂膜(NCF)21与半导体芯片20。然后,藉由未图示的旋转移动机构而如图12(e)的箭头94所示那样使夹套主体31绕旋转移动轴33旋转,而使拾取的半导体芯片20反转,且藉由未图示的旋转移动机构而使旋转移动轴33移动,如图13(f)所示那样,使夹套主体31移动至在与接合工具50之间进行半导体芯片20的交付的交付位置为止。如图13(f)的箭头95所示那样,接合头40使接合工具50的吸附面51接触于以反转状态吸附保持在夹套主体31的吸附面32的半导体芯片20的表面22(贴附有绝缘树脂膜(NCF)21的接合面的相反侧的面)来吸附半导体芯片20,自吸附反转夹套30的夹套主体31接收半导体芯片20。在交付半导体芯片20时,夹套主体31的温度TC如图4(b)的时刻t1所示那样自30℃左右的初始温度TC1上升至50℃左右的温度TC2。如图13(i)的箭头98所示那样,接合头40使接合工具50接地于固定在接合平台60上的电路基板65的规定位置。然后,藉由内置在接合工具50中的脉冲加热器对接合工具50加热而使半导体芯片20的凸块以及绝缘树脂膜(NCF)熔融,从而将半导体芯片20接合在电路基板65上。
如图4(b)所说明那样,交付半导体芯片20之后的夹套主体31的温度成为50℃左右的温度TC2。如图13(h)的箭头97所示那样,旋转移动机构以旋转移动轴33的吸附面32成为下侧的方式使旋转移动轴33旋转,并且使夹套主体31的中心移动至冷却平台110的中心。如图14(a)所示那样,冷却平台110的冷却风扇122旋转,如图中的箭头R所示那样,对散热片115输送冷却空气,因此接地板114、散热片115成为大致常温状态。
使夹套主体31如图14(b)所示的箭头P那样向下方(Z方向负侧)移动,而使夹套主体31的吸附面32接地于作为接地板114的表面的接地面114a。如参照图10、图11所说明那样,接地板114藉由支撑机构200以相对于框架112而绕通过接地板114的中心125的X轴126、Y轴127旋转自如的方式安装在框架112上,因此此接地面114a的倾斜度(接地面114a的方向)仿照夹套主体31的吸附面32的倾斜度(顶端面的方向)而绕X轴126、绕Y轴127自如旋转。由此,夹套主体31的吸附面32密接于接地面114a。接地板114与散热片115固定为一体,因此若夹套主体31的吸附面32密接于接地面114a,则夹套主体31的热如图14(b)的箭头S所示那样,向保持为常温的接地板114、散热片115流动。由于包含接地板114以及散热片115的冷却构件116的热容以成为大于夹套主体31的热容的方式而构成,因此夹套主体31的温度急速降低。又,在夹套主体31的吸附面32密接于接地板114的接地面114a时,自安装在框架112侧面的冷却喷嘴119的吹出孔120向沿接地面114a的方向(箭头Q的方向)喷出冷却空气,且此冷却空气接触于夹套主体31的顶端,从而亦自夹套主体31的外表面进行冷却。
若使夹套主体31对接地板114的接地面114a仅密接规定时间,则夹套主体31的温度降低至图4(b)所示的初始温度TC1。冷却平台110的冷却风扇122如图14(a)所示那样,在夹套主体31的吸附面32离开接地板114的接地面114a之后亦持续对散热片115输送冷却空气,因此由接地板114与散热片115构成的冷却构件116,在藉由接合工具50进行半导体芯片20的接合的期间被冷却至初始温度即温度TC1。
冷却结束后,再次如图12(b)所示那样,移动至下一要拾取的半导体芯片20上而进行下一半导体芯片20的拾取与接合。
本实施方式的覆晶接合器102,与参照图1至图7所说明的实施方式的覆晶接合器101相同,发挥可缩短接合时间而又不降低接合质量的效果。
参照图8至图14所说明的实施方式的覆晶接合器102中,说明了冷却平台110如图10、图11所示那样,藉由组合2个销123、124与中间框架113而成的支撑机构200而安装在框架112上,且接地板114相对于XY的各轴旋转自如,但若接地板114相对于XY的各轴旋转自如,则亦可为以下说明的构成。
参照图15、图16对另一构成的冷却平台110的构成进行说明。对与参照图9至图11所说明的实施方式相同的部分附上相同的符号并省略其说明。图15所示的冷却平台110将参照图9至图11所说明的冷却平台110的支撑机构200设为枢轴支撑机构210,此枢轴支撑机构210利用设置在框架112上的支撑销212来枢轴支撑设置在接地板114下表面的凹陷211。又,图16所示的冷却平台110将支撑机构200设为利用弹簧221支撑接地板114的四角的弹簧支撑机构220。又,亦可代替图15所示的冷却平台110的枢轴支撑机构210,而利用设置在框架112上的球面状的台座来支撑设置在接地板114下表面的球面状的凹陷。图15、图16所示的冷却平台110相对于XY各轴旋转自如,并且亦相对于Z轴旋转自如。又,散热片115以可散发接地板114的热的方式与接地板114成为一体即可,亦可如图15所示那样,配置在接地板114的侧面。进而,冷却构件116亦可不为散热片115,例如为在内部流动冷却水等藉由空气以外的制冷剂进行冷却的。
再者,参照图8至图16所说明的实施方式的覆晶接合器102中,说明了利用冷却平台110对吸附反转夹套30的夹套主体31进行冷却,但也可以与冷却平台110相同的构造设置使接合工具50前端的吸附面51密接来进行冷却的其他冷却平台,且与夹套主体31相同地对接合工具50进行冷却。
下面,参照图17、图18对本发明的另一实施方式进行说明。对与参照图1至图7所说明的实施方式相同的部分附上相同的符号并省略说明。如图17所示那样,本实施方式的覆晶接合器103中,代替将已由吸附反转夹套30反转的半导体芯片20直接交付至接合工具50,而是利用安装在移送头70的夹套71来接收藉由吸附反转夹套30反转的半导体芯片20,并将此半导体芯片20载置在移送平台75的表面76,移送平台75将半导体芯片20一面保持于反转状态,一面搬送至向接合工具50交付半导体芯片20的交付位置。然后,接合工具50自移送平台75的表面76接收反转状态的半导体芯片20,并将此半导体芯片20接合于吸附固定在接合平台60上的电路基板65上。本实施方式的覆晶接合器103中,在接合工具50与移送平台75之间进行半导体芯片20的交付,因此在交付半导体芯片20时与图4(b)所示的夹套主体31相同地,移送平台75的温度自温度TC1上升至温度TC2。再者,安装在移送头70的夹套71在常温下使用,因此本实施方式的覆晶接合器103中,吸附反转夹套30为常温,温度不上升。
因此,本实施方式中,吸附反转夹套30、移送头70、夹套71、以及移送平台75构成反转机构,移送平台75为保持反转的半导体芯片20的保持构件。
如图18所示那样,移送平台75包括:空气流入路77,自此移送平台75的下表面(保持半导体芯片20的表面76的相反侧的面)向表面76伸展;以及水平冷却流路78,连通于空气流入路77且在沿表面76的方向伸展。如图18所示那样,流入至空气流入路77的冷却空气,通过水平冷却流路78自移送平台75的侧面流出至外部,藉此对移送平台75进行冷却。本实施方式中,说明了藉由冷却空气对移送平台75进行冷却,但冷却媒体并不限定于空气,亦可使用水等液体。空气流入路77、水平冷却流路78构成冷却机构。
如参照图1所说明那样,本实施方式的覆晶接合器103中,亦为接合工具50安装在接合头40,且藉由接合头40而沿水平、垂直方向移动。又,接合工具50包括吸附半导体芯片20的前端的吸附面51(图1中的下侧面),且在内部内置有未图示的脉冲加热器,此脉冲加热器将半导体芯片20加热至可熔融形成在半导体芯片20上的凸块的温度(300℃~350℃)。
以下,参照图19、图20对藉由本实施方式的覆晶接合器103将半导体芯片20接合在电路基板65的步骤进行说明。对与参照图1至图7所说明的实施方式相同的步骤、构件附上相同的符号并省略说明。
如图19(a)至图19(d)所示那样,藉由吸附反转夹套30吸附拾取半导体芯片20并使之反转。其后如图19(e)的箭头84所示那样,使安装在移送头70的夹套71的吸附面72接触于半导体芯片20的表面22,而自吸附反转夹套30的夹套主体31接收半导体芯片20,如图19(f)的箭头87所示那样,藉由移送头70而使夹套71移动至移送平台75上,将吸附于夹套71的半导体芯片20交付至移送平台75的表面76。如图20(g)所示那样,结束半导体芯片20向移送平台75的交付之后,移送头70使夹套71上升。移送平台在将反转状态的半导体芯片20保持于表面76上的状态下,如图20(g)的空心箭头88所示那样,移动至半导体芯片20向接合工具50交付的交付位置为止。如图20(h)所示那样,移送平台75到达规定的交付位置之后,接合工具50自移送平台75的表面76接收半导体芯片20,并将半导体芯片20接合于吸附保持在接合平台60的表面61上的电路基板65上。
在将半导体芯片20交付至接合工具50时,移送平台75的温度与图4(b)的时刻t1所示的夹套主体31的温度相同地自初始的30℃左右的温度TC1上升至50℃左右的温度TC2。其后,移送平台75由流过空气流入路77、水平冷却流路78的冷却空气冷却,其温度与图4(b)的时刻t2所示的夹套主体31的温度相同地恢复至初始的温度TC1。
本实施方式的覆晶接合器103中,对在与接合工具50之间进行半导体芯片20的交付的移送平台75进行冷却,藉此使接合工具50接收半导体芯片20的接收温度TB2较现有技术高,且可缩短接合后的接合工具50的冷却时间,因此可将覆晶接合的周期时间大幅缩短。
再者,移送平台75的冷却温度与接合工具50接收半导体芯片20的接收温度TB2的关系,与参照图6、图7所说明的夹套主体31的冷却温度TC1与接合工具50接收半导体芯片20的接收温度TB2的关系相同地,使移送平台75的冷却温度越低,则越可提高接合工具50接收半导体芯片20的接收温度TB2,从而可使接合的周期时间更短。又,若交付的半导体芯片20的大小变小,则即便移送平台75的冷却温度为相同的温度,在交付半导体芯片20时自接合工具50移动至移送平台75的热量亦变少,因此可使接合工具50接收半导体芯片20的接收温度TB2更高,从而可使接合的周期时间更短。又,在移送平台75的热容大于接合工具50的热容的情形时,即便在自接合工具50移动至移送平台75的热量相同的情形时,移送平台75的温度上升亦变小,因此移送平台75的热容相对于接合工具50的热容越大,则越可提高接合工具50接收半导体芯片20的接收温度TB2,从而可使接合的周期时间更短。
参照图21对本发明的又一实施方式的覆晶接合器104进行说明。首先,对与参照图17至图20所说明的实施方式相同的部分附上相同的符号并省略说明。本实施方式的覆晶接合器104构成为:首先在参照图17至图20所说明的覆晶接合器103上配置对移动平台75进行冷却的冷却平台150,使移动平台75在上下方向移动并使其表面76密接于冷却平台150的接地板154,藉此对移动平台75进行冷却。冷却平台150为将参照图8至图14所说明的实施方式的冷却平台110上下反转的构成。本实施方式的效果与参照图17至图20所说明的实施方式相同。再者,本实施方式中,说明了使移动平台75在上下方向移动且密接于冷却平台150的接地板154,但反之亦可使冷却平台150在上下方向移动且使接地板154密接于移动平台75的表面76。
本发明并不限定于以上说明的实施形态,而是包含不脱离权利要求所规定的本发明的技术范围或本质的所有变更及修正。
符号说明:
10:拾取平台
11:上表面
20:半导体芯片
21:绝缘树脂膜(NCF)
22:表面
30:吸附反转夹套
31:夹套主体
32、51、72:吸附面
33:旋转移动轴
34:冷却空气流路
35:冷却空气喷嘴
37:第一冷却空气流路
38:第二冷却空气流路
40:接合头
50:接合工具
60:接合平台
61、76:表面
65:电路基板
70:移送头
71:夹套
75:移送平台
77:空气流入路
78:水平冷却流路
101、102、103、104:覆晶接合器
110、150:冷却平台
112:框架
113:中间框架
114、154:接地板
114a:接地面
115:散热片
116:冷却构件
117、118:冷却空气供给管
119:冷却喷嘴
120:孔
121:支架
122:冷却风扇
123、124:销
125:中心
126:X轴
127:Y轴
200:支撑机构
210:枢轴支撑机构
212:支撑销
221:弹簧
220:弹簧支撑机构
Claims (16)
1.一种覆晶接合器,其包括:
反转机构,使半导体芯片反转;
接合工具,自上述反转机构接收已由上述反转机构反转的上述半导体芯片并将上述半导体芯片接合于基板;以及
冷却机构,对上述反转机构进行冷却。
2.根据权利要求1所述的覆晶接合器,其中上述反转机构包括保持经反转的上述半导体芯片的保持构件,
上述冷却机构在上述接合工具接收上述半导体芯片之前预先将上述保持构件的温度冷却至规定的温度。
3.根据权利要求2所述的覆晶接合器,其中上述保持构件的热容大于上述接合工具的热容。
4.根据权利要求2所述的覆晶接合器,其中上述保持构件为将上述半导体芯片在吸附并反转的状态下交付至上述接合工具的吸附反转夹套。
5.根据权利要求3所述的覆晶接合器,其中上述保持构件为将上述半导体芯片在吸附并反转的状态下交付至上述接合工具的吸附反转夹套。
6.根据权利要求2所述的覆晶接合器,其中上述保持构件为使上述半导体芯片在反转的状态下移动,且将上述半导体芯片在反转的状态下交付至上述接合工具的移送平台。
7.根据权利要求3所述的覆晶接合器,其中上述保持构件为使上述半导体芯片在反转的状态下移动,且将上述半导体芯片在反转的状态下交付至上述接合工具的移送平台。
8.根据权利要求2至7中任一项所述的覆晶接合器,其中上述冷却机构对上述保持构件的内表面或外表面进行冷却。
9.根据权利要求2至7中任一项所述的覆晶接合器,其中上述冷却机构包括:
基体部;以及
冷却构件,包含接地板及散热构件,上述接地板具有上述保持构件的表面接地的接地面,上述散热构件安装在上述接地板;且
上述冷却构件藉由仿照上述保持构件的表面的方向的方式而可以改变上述接地面的方向的支撑机构而支撑在上述基体部。
10.根据权利要求9所述的覆晶接合器,其中上述冷却构件的热容大于上述保持构件的热容。
11.根据权利要求9所述的覆晶接合器,其中上述散热构件安装在上述接地板的接地面的相反侧的面。
12.根据权利要求9所述的覆晶接合器,其中上述散热构件为散热片,且
包括对上述散热片进行冷却的冷却风扇。
13.根据权利要求9所述的覆晶接合器,其中上述支撑机构以绕沿上述接地面的第一轴、及沿上述接地面且与上述第一轴正交的第二轴这2个轴旋转自如的方式将上述接地板支撑于上述基体部。
14.根据权利要求9所述的覆晶接合器,其包括冷却喷嘴,设置在上述基体部,且对表面接地于上述接地面的上述保持构件喷出冷却空气。
15.根据权利要求9所述的覆晶接合器,其中上述接地板的上述接地面在上述保持构件的上述表面接地时,自上述保持构件向上述接地板产生热传导。
16.一种覆晶接合方法,其包括:
准备覆晶接合器的步骤,上述覆晶接合器包括:反转机构,使半导体芯片反转;接合工具,自上述反转机构接收已由上述反转机构反转的上述半导体芯片并将上述半导体芯片接合于基板;以及冷却机构,对上述反转机构进行冷却;以及
冷却步骤,在上述接合工具接收上述半导体芯片之前预先藉由上述冷却机构将上述保持构件的温度冷却至规定的温度。
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Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI576196B (zh) * | 2012-12-05 | 2017-04-01 | Shinkawa Kk | The cooling method of the joining tool cooling device and the joining tool |
US9093549B2 (en) * | 2013-07-02 | 2015-07-28 | Kulicke And Soffa Industries, Inc. | Bond heads for thermocompression bonders, thermocompression bonders, and methods of operating the same |
DE102015106298B4 (de) * | 2015-04-24 | 2017-01-26 | Semikron Elektronik Gmbh & Co. Kg | Vorrichtung, Verfahren und Anlage zur inhomogenen Abkühlung eines flächigen Gegenstandes |
US9929121B2 (en) | 2015-08-31 | 2018-03-27 | Kulicke And Soffa Industries, Inc. | Bonding machines for bonding semiconductor elements, methods of operating bonding machines, and techniques for improving UPH on such bonding machines |
KR101834644B1 (ko) * | 2016-06-30 | 2018-03-05 | 세메스 주식회사 | 다이 본딩 장치 |
JP6705727B2 (ja) * | 2016-09-26 | 2020-06-03 | ファスフォードテクノロジ株式会社 | フリップチップボンダおよび半導体装置の製造方法 |
JP7018338B2 (ja) * | 2018-03-19 | 2022-02-10 | ファスフォードテクノロジ株式会社 | ダイボンディング装置および半導体装置の製造方法 |
KR20210004324A (ko) | 2019-07-04 | 2021-01-13 | 삼성전자주식회사 | 마이크로 led 디스플레이 모듈 및 이를 제조하는 방법 |
KR102221704B1 (ko) * | 2019-09-03 | 2021-03-02 | 세메스 주식회사 | 진공 피커 및 이를 포함하는 다이 본딩 장치 |
US11289360B2 (en) | 2019-12-16 | 2022-03-29 | Micron Technology, Inc. | Methods and apparatus for protection of dielectric films during microelectronic component processing |
KR20230067922A (ko) | 2021-11-10 | 2023-05-17 | 주식회사 쌤토스 | 마이크로 ic 플립형 실장 장치 |
TW202335115A (zh) * | 2022-01-27 | 2023-09-01 | 日商東京威力科創股份有限公司 | 基板處理裝置及基板處理方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1111820A (zh) * | 1994-05-06 | 1995-11-15 | 松下电器产业株式会社 | 集成电路元件组装方法及其装置 |
JPH10275833A (ja) * | 1997-03-31 | 1998-10-13 | Sumitomo Osaka Cement Co Ltd | パルスヒーター及び半導体チップ実装ボードの製法 |
JP2001168146A (ja) * | 1999-12-09 | 2001-06-22 | Sony Corp | 部品装着装置及び部品装着方法 |
US20040206800A1 (en) * | 2003-04-15 | 2004-10-21 | Kazuhisa Arai | Flip chip bonder |
US20050098610A1 (en) * | 2001-06-27 | 2005-05-12 | Shunji Onobori | Apparatus and method for mounting electronic components |
JP2012174861A (ja) * | 2011-02-21 | 2012-09-10 | Sekisui Chem Co Ltd | フリップチップ実装方法 |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05291354A (ja) | 1992-04-10 | 1993-11-05 | Nippon Steel Corp | ボンディング装置 |
JPH0997819A (ja) * | 1995-09-29 | 1997-04-08 | Matsushita Electric Ind Co Ltd | 電子部品ボンディング装置 |
JP3382436B2 (ja) | 1995-10-27 | 2003-03-04 | 松下電器産業株式会社 | 電子部品搭載装置 |
US5923086A (en) * | 1997-05-14 | 1999-07-13 | Intel Corporation | Apparatus for cooling a semiconductor die |
JP3399367B2 (ja) * | 1998-06-26 | 2003-04-21 | 松下電器産業株式会社 | ワークの熱圧着装置 |
JP3635930B2 (ja) | 1998-07-06 | 2005-04-06 | 松下電器産業株式会社 | 光通信ユニットの実装方法 |
JP2002158257A (ja) * | 2000-11-16 | 2002-05-31 | Mitsubishi Electric Corp | フリップチップボンディング方法 |
JP2002367931A (ja) * | 2001-06-07 | 2002-12-20 | Lintec Corp | ダイボンディングシート貼着装置およびダイボンディングシートの貼着方法 |
TW559963B (en) * | 2001-06-08 | 2003-11-01 | Shibaura Mechatronics Corp | Pressuring apparatus of electronic device and its method |
JP3671051B2 (ja) * | 2002-12-03 | 2005-07-13 | 芝浦メカトロニクス株式会社 | 電子部品のボンディング装置およびボンディング方法 |
WO2005008726A2 (en) * | 2003-07-09 | 2005-01-27 | Newport Corporation | Flip chip device assembly machine |
JP4516354B2 (ja) * | 2004-05-17 | 2010-08-04 | パナソニック株式会社 | 部品供給方法 |
JP4761026B2 (ja) | 2005-06-03 | 2011-08-31 | ソニー株式会社 | 素子転写装置、素子の転写方法および表示装置の製造方法 |
JP2009289959A (ja) * | 2008-05-29 | 2009-12-10 | Elpida Memory Inc | ボンディング装置およびボンディング方法 |
JP5167071B2 (ja) | 2008-11-04 | 2013-03-21 | アルファーデザイン株式会社 | フリップチップボンダ装置の作業台板の水平化調整方法及びプログラム |
JP5167072B2 (ja) | 2008-11-04 | 2013-03-21 | アルファーデザイン株式会社 | フリップチップボンダ装置 |
JP5281550B2 (ja) * | 2008-12-08 | 2013-09-04 | パナソニック株式会社 | ボンディングツール、電子部品装着装置、および電子部品装着方法 |
JP5296722B2 (ja) * | 2009-03-02 | 2013-09-25 | パナソニック株式会社 | ボンディングツール、電子部品装着装置、および電子部品装着方法 |
JP5835722B2 (ja) * | 2009-12-10 | 2015-12-24 | オルボテック エルティ ソラー,エルエルシー | 自動順位付け多方向直列型処理装置 |
US8231044B2 (en) * | 2010-10-01 | 2012-07-31 | Orthodyne Electronics Corporation | Solar substrate ribbon bonding system |
US8196798B2 (en) * | 2010-10-08 | 2012-06-12 | Kulicke And Soffa Industries, Inc. | Solar substrate ribbon bonding system |
TWI564106B (zh) * | 2011-03-28 | 2017-01-01 | 山田尖端科技股份有限公司 | 接合裝置以及接合方法 |
CN107768285B (zh) * | 2011-06-03 | 2021-06-22 | 豪锐恩科技私人有限公司 | 用于半导体芯片的拾取和转移及结合的方法和系统 |
WO2014038439A1 (ja) * | 2012-09-04 | 2014-03-13 | シャープ株式会社 | 液晶表示装置の製造方法 |
CH707378A1 (de) * | 2012-12-21 | 2014-06-30 | Besi Switzerland Ag | Thermokompressionsverfahren und Vorrichtung für die Montage von Halbleiterchips auf einem Substrat. |
JP6182082B2 (ja) * | 2013-03-15 | 2017-08-16 | 日本碍子株式会社 | 緻密質複合材料、その製法及び半導体製造装置用部材 |
JP6182084B2 (ja) * | 2013-03-25 | 2017-08-16 | 日本碍子株式会社 | 緻密質複合材料、その製法、接合体及び半導体製造装置用部材 |
US9093549B2 (en) * | 2013-07-02 | 2015-07-28 | Kulicke And Soffa Industries, Inc. | Bond heads for thermocompression bonders, thermocompression bonders, and methods of operating the same |
US9484241B2 (en) * | 2013-07-29 | 2016-11-01 | Asm Technology Singapore Pte Ltd | Device for holding multiple semiconductor devices during thermocompression bonding and method of bonding |
KR101543864B1 (ko) * | 2013-11-13 | 2015-08-11 | 세메스 주식회사 | 본딩 헤드 및 이를 포함하는 다이 본딩 장치 |
KR102168070B1 (ko) * | 2013-11-29 | 2020-10-21 | 삼성전자주식회사 | 반도체 제조 장치 및 방법 |
US9548284B2 (en) * | 2013-12-18 | 2017-01-17 | Intel Corporation | Reduced expansion thermal compression bonding process bond head |
US9282650B2 (en) * | 2013-12-18 | 2016-03-08 | Intel Corporation | Thermal compression bonding process cooling manifold |
-
2013
- 2013-08-14 TW TW102129072A patent/TWI490956B/zh active
- 2013-09-20 WO PCT/JP2013/075478 patent/WO2014141514A1/ja active Application Filing
- 2013-09-20 CN CN201380027231.5A patent/CN104335336B/zh active Active
- 2013-09-20 KR KR1020147033242A patent/KR101623368B1/ko active IP Right Grant
- 2013-09-20 JP JP2014545028A patent/JP5675008B1/ja active Active
- 2013-09-20 SG SG11201507246VA patent/SG11201507246VA/en unknown
-
2015
- 2015-09-08 US US14/847,295 patent/US9536856B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1111820A (zh) * | 1994-05-06 | 1995-11-15 | 松下电器产业株式会社 | 集成电路元件组装方法及其装置 |
JPH10275833A (ja) * | 1997-03-31 | 1998-10-13 | Sumitomo Osaka Cement Co Ltd | パルスヒーター及び半導体チップ実装ボードの製法 |
JP2001168146A (ja) * | 1999-12-09 | 2001-06-22 | Sony Corp | 部品装着装置及び部品装着方法 |
US20050098610A1 (en) * | 2001-06-27 | 2005-05-12 | Shunji Onobori | Apparatus and method for mounting electronic components |
US20040206800A1 (en) * | 2003-04-15 | 2004-10-21 | Kazuhisa Arai | Flip chip bonder |
JP2012174861A (ja) * | 2011-02-21 | 2012-09-10 | Sekisui Chem Co Ltd | フリップチップ実装方法 |
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