TWI538136B - 半導體封裝件及其製造方法 - Google Patents

半導體封裝件及其製造方法 Download PDF

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Publication number
TWI538136B
TWI538136B TW103117572A TW103117572A TWI538136B TW I538136 B TWI538136 B TW I538136B TW 103117572 A TW103117572 A TW 103117572A TW 103117572 A TW103117572 A TW 103117572A TW I538136 B TWI538136 B TW I538136B
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Taiwan
Prior art keywords
solder bump
solder
contact pad
semiconductor package
bump
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TW103117572A
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English (en)
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TW201521170A (zh
Inventor
林修任
呂文雄
陳正庭
郭炫廷
陳威宇
鄭明達
劉重希
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台灣積體電路製造股份有限公司
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Publication of TW201521170A publication Critical patent/TW201521170A/zh
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Description

半導體封裝件及其製造方法
本揭露係關於一種半導體封裝結構。
半導體裝置的效能藉由縮減裝置尺寸而大幅提升。同時，半導體裝置的發展使得元件密度與元件複雜度均顯著提升。在一晶圓級晶片尺寸封裝件(wafer level chip scale package；WLCSP)技術中，半導體晶片係在晶圓上製作完成後直接在晶圓層級上進行封裝，接著自該晶圓切單各半導體晶片。因此，晶片封裝件的尺寸幾乎等同於原始半導體晶片之尺寸。WLCSP已廣泛應用於行動電話，如類比連接、無線連接、CMOS影像感測器及其他應用上。尤其，WLCSP漸漸用於封裝尺寸大於5 x 5mm2的無線基頻或射頻收發器(wireless baseband or RF transceiver)。用於一覆晶接合(flip-chip bonding)之關鍵元件為走線層(redistribution layer；RDL)、凸塊下冶金(under bump metallurgy；UBM)、及凸塊(如銲錫凸塊或金屬柱)。在上述元件中，銲錫凸塊(solder bump)係用以對裝置進行存取之結構，亦稱作輸入/輸出(I/O)結構。
上述需求與發展已催生出新的半導體裝置封裝方法，據此發展出如球柵陣列(ball grid array；BGA)裝置及柱柵陣列(Column Grid Array；CGA)裝置等結構。一BGA包含黏附於位在一積體電路封 裝件底部上之引腳(pins)之一銲錫凸塊陣列(array of bumps of solder)，用於將該積體電路封裝件電性連接至一印刷電路板(PCB)。該積體電路封裝件可接著被放置於該印刷電路板上，該印刷電路板具有多個銅導電墊片，該等銅導電墊片位在與該積體電路封裝件上的銲錫凸塊陣列相吻合的一圖案中。該等銲錫凸塊可被加熱至熔化。當該銲錫冷卻且固化時，該經硬化的銲錫以機械性的方式將該積體電路封裝件附接至該印刷電路板。
習知的BGA具有40、50及60密耳(mil)之間隙。由於裝置的微型化趨勢，裝置上所具有的互連(interconnect)之效能及裝置的成本已成為封裝件發展上的重要考量因素。
本揭露之一實施例提供一種半導體封裝件，其包括：一接點墊片；一裝置，其位於該接點墊片外部且包括對應於該接點墊片之一導電接點墊片；一銲錫凸塊，其利用該導電接點墊片連接該接點墊片，其中該銲錫凸塊包括：一高度，其係自該銲錫凸塊的一頂部至該接點墊片；及一寬度，其係該銲錫凸塊在一垂直於該高度的方向上之一最寬尺寸；及其中該銲錫凸塊在接近該接點墊片處之一接面部位包括一沙漏形狀。
本揭露之另一實施例提供一種半導體封裝件，其包括：一球柵陣列(BGA)，其包括複數個接點墊片，其中該複數個接點墊片之各者均在一銲錫凸塊的一端與該銲錫凸塊連接，其中該BGA中的一最細微間距(pitch)小於大約0.2毫米；及一電路板，其包括複數個導電接點墊片，其中該複數個導電接點墊片之各者均在該銲錫凸塊的另一端與該BGA電性連接；其中該銲錫凸塊包括：一高度，其係自該銲錫凸塊的一頂部至該接點墊片；及一寬度，其係該銲錫凸塊在一垂直於該高度的方向上之一最寬尺寸；及其中該銲錫凸塊在接近該接點墊片 處之一接面部位包括一沙漏形狀。
本揭露之又一實施例提供一種製造一半導體封裝件的方法，其包括：在一接點墊片上形成一銲錫膠層；在該銲錫膠層上設置一銲錫凸塊；在該銲錫凸塊與該接點墊片之間形成一第一電性連接；密封該銲錫膠層與該銲錫凸塊之一下側部位，其中該銲錫凸塊之該下側部位接近該接點墊片；及在該銲錫凸塊與一外部裝置之間形成一第二電性連接。
θ‧‧‧角度
A‧‧‧點
B‧‧‧點
C‧‧‧點
r+‧‧‧正半徑
r-‧‧‧負半徑
C1‧‧‧等濃度切面輪廓
C2‧‧‧等濃度切面輪廓
C3‧‧‧等濃度切面輪廓
C4‧‧‧等濃度切面輪廓
H‧‧‧高度
H'‧‧‧頂部
K‧‧‧點
Tm‧‧‧厚度
Ts‧‧‧厚度
W'‧‧‧寬度
W1‧‧‧寬度
W2‧‧‧寬度
100‧‧‧載體
100A‧‧‧半導體封裝件
100B‧‧‧半導體封裝件
100C‧‧‧半導體封裝件
100D‧‧‧半導體封裝件
100E‧‧‧半導體封裝件
101‧‧‧接點墊片
102‧‧‧接面部位
103‧‧‧銲錫凸塊
105‧‧‧鑄模化合物
107‧‧‧填充層
200‧‧‧外部裝置
201‧‧‧導電接點墊片
202‧‧‧頂部接面部位
301‧‧‧銲錫膠層
303‧‧‧電性連接
305‧‧‧電性連接
500‧‧‧部分剖面
本揭露所提出之態樣可藉由參閱實施方式及附加圖式被清楚地理解。必須強調的是，依據工業上的標準實務，各圖式中之特徵並非以正確尺寸繪示。實際上，為了清楚表達及論述，各特徵的尺寸可任意增加或減少。
圖1係本揭露之某些實施例所載半導體封裝件之一部份之剖面圖；圖2係本揭露之某些實施例所載半導體封裝件之一部份之剖面圖；圖3係本揭露之某些實施例所載半導體封裝件之一部份之剖面圖；圖4係本揭露之某些實施例所載半導體封裝件之一部份之剖面圖，顯示該半導體封裝件中一元件之一濃度切面輪廓(concentration contour)；圖5係本揭露之某些實施例所載半導體封裝件之一球柵陣列之剖面圖；圖6係本揭露之某些實施例所載半導體封裝件之一部份之剖面圖；及圖7A至7E係顯示製造本揭露之某些實施例所載半導體 封裝件之操作之剖面圖。
本說明書所載實施例應配合附加圖式閱讀，該等附加圖式被認為是整體說明書的一部分。在本揭露之說明書中，關於方向或定向之任何參考符號僅為方便描述且並非意圖限定本揭露之範疇。相對性用語(如"下側(lower)"、"上側(upper)"、"水平(horizontal)"、"垂直(vertical)"、"在...之上(above)"、"在...之下(below)"、"上(up)"、"下(down)"、"頂部(top)"及"底部(bottom)")及相關衍生用語(例如，"水平地(horizontally)"、"向下地(downwardly)"及向上地(upwardly)"等)應理解為本揭露所述實施例或圖式之定向。這些相對性用語僅為方便描述，並非要求相關實施例所述裝置在特定定向下建構或操作。除非有特別說明，否則如"經附接的(attached)"、"經黏附(affixed)"、"經連接的(connected)"及"經互連的(interconnected)等用語係描述某結構透過中間結構而被直接或間接固定至或附接至另一結構之關係以及可移動的或剛性的附接關係。此外，參照較佳實施例描述本揭露之特徵與優點。此等較佳實施例描述可單獨存在之非限定特徵組合或與其他特徵組合之結合。因此，可明確了解到，本揭露內容不應被限定於此等較佳實施例。本揭露之範疇為所附申請專利範圍所涵蓋。
在附加圖式中，類似的參考編號係用以指定各圖式中相似或類似的元件，且顯示及描述本揭露之說明實施例。該等附加圖式無須依實際比例繪示，且在某些範例中，為了便於說明，該等圖式可以誇大及/或簡化的方式繪示。基於本揭露以下所載之說明實施例，所屬技術領域中具有通常知識者將理解到本揭露的各種可能應用與變化。
某些小尺寸的WLP裝置被整合在一個具有更多I/O墊片的大尺寸WLCSP裝置中，以確保封裝件組件的面積。由於該矽晶粒 (矽晶粒)與印刷電路板間熱膨脹係數的差異，故會在最遠的銲錫接頭(solder joint)上產生更多個熱應力(thermal stress)。此外，WLCSP裝置的銲錫凸塊間距(solder bump pitch)也趨於減少，且由於銲錫接頭面積越來越小，使得熱可靠度(thermal reliability)係一重要的考量因素。綜合考量上述所有因素，需要較大的銲錫凸塊直徑以達到較佳的可靠度。然而，在一細微間距WLCSP中採用較大的銲錫凸塊會導致鄰近銲錫凸塊之間的橋接問題(Bridge problem)。橋接問題會產生短路連接，進而降低球裝設良率(ball mount yield)。
銅球或銅核心銲錫球(copper core solder ball)係解決含錫銲錫球(Sn-containing solder ball)所遭遇問題之解決方案。然而，高成本及不理想的可靠度性質阻礙了此種技術的發展。塑膠核心銲錫球(藉由多層金屬塗層覆蓋一塑膠核心(plastic core))係用於解決上述問題的另一解決方案。尺寸可控制且可吸收應力的彈性塑膠核心提供了較佳的隔離可控制性(stand-off controllability)及較高的可靠度。然而，塑膠核心銲錫球的成本限制了此技術在實際量產上的應用。
本揭露提供了一種使用含錫銲錫球之半導體封裝件結構，該半導體封裝件結構在一細微間距WLCSP中表現出較佳的隔離可控制性、在銲錫接頭的良好電遷移阻抗(electromigration resistance)、較高的球裝設良率以及較低的製造成本。在某些實施例中，利用本揭露說明書所述之方法所製造的半導體封裝件結構顯示一銲錫凸塊在接近一支撐該銲錫凸塊的接點墊片(contact pad)處具有一接面部位(junction portion)，且該接面部位呈現一沙漏形狀(hourglass shape)。在該接面部位所呈現之沙漏形狀維持該銲錫凸塊具有較高的高度對寬度之比值，且達到相對較佳的偏離可控制性。在某些實施例中，相對較佳的隔離可控制性能夠降低大體積銲錫凸塊發生橋接問題的風險。
本揭露提供了一種製造一包含本揭露所載銲錫凸塊結構之半導體封裝件的方法。在沉積一銲錫凸塊之前，在一接點墊片上形成一銲錫膠層(solder paste layer)。該銲錫凸塊結構經歷兩次溫度處理(temperature treatments)。第一溫度處理僅容許該銲錫膠層被液化，且在該銲錫凸塊與該接點墊片之間形成一電性連接。第二溫度處理容許該銲錫凸塊與該銲錫膠層兩者均被液化，且在該銲錫凸塊與一外部半導體裝置之間形成一電性連接。
在描述與主張本揭露之內容時，下列術語必須根據以下所提及的定義被使用。
如本揭露說明書中所使用，「助銲劑(flux)」一詞意指輔助銲錫製程之。物質。在某些實施例中，該助銲劑含有還原劑(reducing agent)，如炭(charcoal)。在某些實施例中，該助銲劑含有腐蝕性材料(corrosive material)。在某些實施例中，該助銲劑降低被熔化的銲錫之表面張力，且使得該被熔化的銲錫更容易流動及濕潤一工件(work piece)。在某些實施例中，該助銲劑係以松香為基礎的(rosin-based)。在某些實施例中，該助銲劑的構成成分包含松香、溶劑、觸變劑thixotropic agent)(下陷防止劑(sagging preventing agent))、活化劑(activator)及添加劑。該松香可為天然松香或合成松香(如聚合松香、不勻化松香(disproportionated rosin)及氫化松香(hydrogenated rosin))。上述松香中任何一者或其中多者之組合皆可被使用。該助銲劑中所使用的溶劑通常是一種卡必醇系(carbitol system)或乙二醇系(glycol system)的醇。上述醇類中任何一者或其中多者之組合皆可被使用。(amide wax)或蓖麻蠟(castor wax)可用以作為觸變劑。作為活化劑的其他有機酸可與如胺鹽(amine salt)之活化劑共同使用作為活化劑。殘餘物改性劑(residue modifiers)(如典型的塑化劑(plasticizers)及填充劑(fillers))可用以作為添加劑。
在本揭露中，「銲錫膠(solder paste)」意指在一助銲劑媒介材料中的均勻且穩定懸浮的銲錫顆粒(solder particle)。在某些實施例中，該銲錫膠(通常亦稱為銲錫膏(solder cream)或焊接膠(soldering paste))係藉由混合(或揉合)銲錫合金粉末與一助銲劑而獲得。在習知技術中，錫鉛系統(tin-lead system)已常用以作為銲錫合金，但最近幾年才因考量鉛的危險性而轉變成為不含鉛的無鉛銲錫(lead-free solders)。在某些實施例中，無鉛銲錫合金粉末包含錫(Sn)、銀(Ag)、鉍(Bi)及銦(In)，顆粒尺寸自大約20微米至大約38微米。
如本揭露說明書中所使用，「氣相沉積(vapor deposition)」一詞意指利用欲沉積之材料之氣相(vapor phase)或該材料之一前驅物(precursor)在一基板上沉積材料之製程。汽相沉積製程包含(但不限定於)任何如化學汽相沉積(CVD)及物理汽相沉積(PVD)之製程。汽相沉積方法的範例包括熱燈絲CVD(hot filament CVD)、射頻CVD、雷射CVD(LCVD)、適形鑽石塗層製程(conformal diamond coating processes)、金屬有機CVD(MOCVD)、濺鍍(sputtering)、熱蒸鍍PVD(thermal evaporation PVD)、離子化金屬PVD(IMPVD)、電子束PVD(EBPVD)、反應性PVD(reactive PVD)、原子層沉積(ALD)、電漿輔助CVD(PECVD)、高密度電漿CVD(HDPCVD)、低壓CVD(LPCVD)及類似技術。
如本揭露說明書中所使用，「鑄模化合物(molding compound)」一詞意指由複合材料所形成的化合物。一鑄模化合物可包含環氧樹脂(epoxy resins)、酚類固化劑(phenolic hardeners)、氧化矽(silicas)、催化劑(catalysts)、顏料(pigments)、脫模劑(mold release agents)或類似材料。形成鑄模化合物的材料具有高導熱性(thermal conductivity)、低吸濕率(low moisture absorption rate)、在電路板安裝 溫度下較高的抗彎強度(flexural strength)或上述各者之組合。
如本揭露說明書中所使用，「電性互連(electrical interconnects)」一詞意指經繞線在積體電路結構中且位於該(等)晶粒上方或周圍的導電線路或薄膜。在某些實施例中，該等電性互連係走線層(RDL)。該等RDL係用於扇入(fan-in)或扇出(fan-out)製程。在某些實施例中，該等電性互連係由導電材料(如金、銀、銅、鎳、鎢、鋁及/或上述各者之合金)所形成。
如本揭露說明書中所使用，「接點墊片」係放置於一晶粒之頂部表面上。該接點墊片的頂部表面可容納一銲錫凸塊或銲錫膠，並作為一終端以將該晶粒連接至一外部電路，或者電性連接至一RDL。該接點墊片之底部表面連接至一互連(如RDL)或連接至該晶粒中的一主動區域(active area)。在某些實施例中，該接點墊片係一凸塊下金屬化(under bump metallization；UBM)。在某些實施例中，該UBM係由導電材料(如金、銀、銅、鎳、鎢、鋁及/或上述各者之合金)所形成。
如本揭露說明書中所使用，「圖案化(patterning)」或「經圖案化」係用以描述在一表面上形成一預定圖案之操作。該圖案化操作包含多個步驟及製程，且依據實施例之特徵而變化。在某些實施例中，一圖案化操作對一現有薄膜或層進行圖案化。該圖案化操作包含在該現有薄膜或層上形成一遮罩(mask)及利用一蝕刻或其他移除製程來移除該薄膜或層之未被遮蔽的部份(unmasked portion)。該遮罩為一光阻(photo resist)或一硬遮罩。在某些實施例中，一圖案化操作直接在一表面上形成一經圖案化層。該圖案化操作包含在該表面上形成一光敏薄膜(photosensitive film)、進行一光微影製程(photolithography process)及一顯影製程(developing process)。剩餘的光敏薄膜可被移除或被保留且被整合在該封裝件中。
本揭露之實施例可對於先前所述技術課題與需求提供解決方案。圖1係半導體封裝件100A的一部份之剖面圖。圖1所示之銲錫凸塊結構包含一載體100、一接點墊片101及置於該接點墊片101上的一銲錫凸塊103。在某些實施例中，該載體100包含一矽晶圓、矽晶粒、一絕緣體上半導體(SOI)基板、任何包括半導體材料之架構或一印刷電路板。如電晶體、電容器、電阻器、二極體、光電二極體(photo-diodes)、保險絲(fuses)等經互連以實現一或多種功能的半導體裝置係形成於該載體100的表面。在某些實施例中，該銲錫凸塊103的高度為H，其中H係自該銲錫凸塊103的頂部H'沿一垂直線測量至於該接點墊片101的高度。該銲錫凸塊103亦具有寬度W1，其中W1係該銲錫凸塊103在一垂直於該高度H的方向上的一最寬尺寸(widest dimension)。在特定實施例中，該銲錫凸塊103的高度H與寬度W1係藉由剖面掃描式電子顯微技術(cross sectional scanning electron microscope；SEM)在大約300倍至大約600倍的放大倍率下測量得到。
該銲錫凸塊103的接面部位102係指在該銲錫凸塊103的底部與該接點墊片101之一頂部表面接觸的一頸狀結構(neck structure)。在某些實施例中，根據本揭露所載方法製造的銲錫凸塊103的接面部位102具有一沙漏形狀。該接面部位102具有一最狹窄部份，且當該寬度測量自該最窄部份往該銲錫凸塊103的頂部H'移動以及往該接點墊片101移動時，該接面部位102的其他部份之寬度會增加。
參照圖2，圖2係本揭露之某些實施例所載半導體封裝件100B的一部份之剖面圖。為了簡化起見，圖2中元件與圖1中元件共用相同元件符號者在此不重覆赘述。該半導體封裝件100B包含一鑄模化合物105，該鑄模化合物105包圍該接面部位102及該銲錫凸塊103之下側部位。必須說明的是，該銲錫凸塊103的下側部位意指接近該 載體100上之該接點墊片101的部位。在某些實施例中，具有沙漏形狀的接面部位102接近該接點墊片101。然而，在其他實施例中，具有沙漏形狀的接面部位102係形成為接近該接點墊片101的底部且同時接近一頂部接點墊片201(此組態並未顯示於圖2中)。
在某些實施例中，該鑄模化合物105之厚度Tm為該銲錫凸塊103高度的大約0.45倍至大約0.6倍。在某些實施例中，該半導體封裝件100B包含一填充層(underfill layer)107，該填充層包圍該銲錫凸塊103的上側部位。必須說明的是，該銲錫凸塊103的上側部位意指該銲錫凸塊103接近一導電接點墊片201之部位，且該導電接點墊片201係連接至一外部裝置200。在某些實施例中，該外部裝置200包含一矽晶圓、一矽晶粒、一絕緣體上半導體(SOI)基板、任何包括半導體材料之架構或一印刷電路板。如電晶體、電容器、電阻器、二極體、光電二極體(photo-diodes)、保險絲(fuses)等經互連以實現一或多種功能的半導體裝置係形成於該外部裝置200的表面。圖2所示之半導體封裝件包含該鑄模化合物105及該填充層107兩者。該鑄模化合物105包圍該底部接點墊片101、該接面部位102及該銲錫凸塊103之下側部位；同時，該填充層107包圍該頂部導電接點墊片201與該銲錫凸塊103的上側部位。
在某些實施例中，該銲錫凸塊103可包含由錫(Sn)、銀(Ag)、銅(Cu)、鉛(Pb)、鉍(Bi)、銻(Sb)、銦(In)、鍺(Ge)、鎳(Ni)及上述材料之任意組合所構成之合金。在特定實施例中，該銲錫凸塊103包含適當化學計量之錫、銀及銅。在銲錫凸塊中使用鉛(lead)已受到高度關注，且基於環保及維護人體健康之考量已不欲在銲錫凸塊中使用鉛。因此，目前產業界已嘗試避免在銲錫凸塊中使用鉛。此類無鉛的銲錫凸塊通常包含錫、銅及銀(通常為重量百分比95.5%之錫、重量百分比4%之銀、重量百分比0.5%之銅)。重量百分比大約1.0%至4.5% 之鉍(Bismuth)亦可與錫、銻(antimony)及銀一起使用。
在某些實施例中，該銲錫凸塊103的接面部位102包含含有錫之合金(SnX)，該SnX合金具有一低於攝氏165度之合金熔點。舉例而言，位於該銲錫凸塊103的接面部位102之合金包含二元含錫合金(binary Sn-containing(SnX)alloy)，如SnBix、SnSbx、SnPbx、SnGex、SnAlx、SnGax、SnInx、SnTlx、BiInSn及上述材料之任意組合。在其他實施例中，位於該銲錫凸塊103的接面部位102之合金包含上述元素之三元(ternary)或甚至四元合金(quaternary alloys)。然而，該等含錫(SnX)合金並不限定於本段落所提及之元素，熔化溫度低於一銲錫凸塊之熔化溫度(通常是在大約攝氏220度至大約攝氏250度)的任何含錫(SnX)合金皆可被使用於該銲錫凸塊103之接面部位102。
如圖2所示的某些實施例中，該銲錫凸塊103的寬度W1大於該接點墊片101的一寬度W2。對於一微細間距WLCSP而言，鄰近的多個接點墊片之間的分隔縮短，同樣地相鄰的多個銲錫凸塊之間的間距也縮減。倘若偏離可控制性較佳的銲錫凸塊103的寬度W1遠大於該下層接點墊片(underlying contact pad)101的寬度，則限制鄰近的接點墊片之間的分隔受到限制，以避免在多個銲錫凸塊之間發生橋接瑕疵(bridge defects)。在某些實施例中，該接點墊片101的寬度W2大約為550微米，而該銲錫凸塊103的寬度W1大約為288微米。在這些實施例中，一具有較佳偏離可控制性的銲錫凸塊103在金屬球剪力測試(ball shear test)中展現出440gf的剪力(shear force)且符合250gf的目標金屬球剪力規格(target ball shear specification)。
參照圖2及圖3，圖3係本揭露之某些實施例所載半導體封裝件100C之一部份之剖面圖。為了簡化起見，與圖2中元件共用相同元件符號者在此不重覆赘述。在圖3中，顯示該底部接面部位102與該頂部接面部位202均分別具有一沙漏形狀。在此情況下，該鑄模化 合物105包圍該底部接點墊片101、該底部接面部位102及該銲錫凸塊103之下側部位；同時，該填充層107包圍該頂部導電接點墊片201、該頂部接面部位202及該銲錫凸塊103的上側部位。在某些實施例中，該銲錫凸塊102的上側與下側部位係由不同材料所密封。然而，一接面部位無論位於較接近該接點墊片101的一端或者位於較接近該導電墊片201的一端皆涵蓋在本揭露所考慮的範疇內。
在圖3中，該銲錫凸塊103具有一高度H與一寬度W1。在某些實施例中，該銲錫凸塊103的高度對寬度比(H/W1)介於大約0.85至大約1.15。應留意到，本揭露中之銲錫凸塊103的高度對寬度比(H/W1)接近1，此比值代表一銲錫凸塊在裝設於一接點墊片上之前的高度對寬度比(H/W1)。如圖3所示，該銲錫凸塊103的高度係自該底部接點墊片101測量至該頂部導電接點墊片201之長度。在某些實施例中，該銲錫凸塊103的高度H大約為290微米，而此銲錫凸塊103的寬度大約為280微米。因此，所獲得的高度對寬度比(H/W1)為1.04。在其他實施例中，該銲錫凸塊103的高度H大約為244微米，而此銲錫凸塊103的寬度大約為288微米。因此，所獲得的高度對寬度比(H/W1)為0.85。
參照圖4，圖4係本揭露之某些實施例所載半導體封裝件100D之一部份之剖面圖。該含錫合金(SnX)中的X成分在該銲錫凸塊103的接面部位102呈現出因擴散或對流(convection)造成之一濃度分布(concentration distribution)。該含錫合金(SnX)中的X成分已於先前描述過，故為了簡化起見，將不再重覆贅述。圖4所示者為該銲錫凸塊103中X成分的濃度分布的其中一種情況，顯示四個等濃度切面輪廓(equi-concentration contour)C1、C2、C3及C4。在某些實施例中，該X成分濃度由高至低的順序為：C1>C2>C3>C4，亦即該X成分濃度自該接面部位102往該銲錫凸塊103的頂部H'遞減。在其他實施例 中，該些等濃度切面輪廓之拓墣結構(topologies)無須如圖4所示。然而，該X成分濃度具有一濃度梯度(concentration gradient)，該濃度梯度自一較低濃度區域(接近該銲錫凸塊103的頂部及/或周邊)指向一較高濃度區域(接近該銲錫凸塊103之接面部位102)。在某些實施例中，有X成分分布在該銲錫凸塊103中的情況相較於在該銲錫凸塊103中沒有X成分的情況而言能夠提供更好的電遷移(electromigration)及強大的熱循環(thermal cycle)特性。
圖5顯示一半導體封裝件100E具有BGA的一部份。為了簡化起見，該接點墊片101上僅設置有一個銲錫凸塊103。在某些實施例中，該BGA中各接點墊片101均設置有一個銲錫凸塊。應留意到，該BGA中各銲錫凸塊均包含先前參照圖1所討論的結構。兩個鄰近的接點墊片101的各別中心(respective centers)之間的分隔係一間距P，且在某些實施例中，該最細微間距P小於0.2毫米。所屬技術領域中具有通常知識者應理解到多個不同尺寸之間距同時出現在該BGA中且皆涵蓋在本揭露所考慮的範疇內。該BGA上進一步裝設有具數個導電接點墊片之電路板(未顯示)。各導電接點墊片均對應至該BGA上的一接點墊片101。該導電接點墊片透過一銲錫凸塊103連接該接點墊片101。
圖6係圖5中所示之BGA 100E之一部分500之放大剖面圖。在圖6中，該銲錫凸塊103的剖面包含一零曲率點(a point where a curvature thereof is zero)。曲率的正半徑(positive radius)r+於該銲錫凸塊103的周邊上之點A被發現，同時曲率的負半徑(negative radius)r-於該銲錫凸塊103的周邊上之點B被發現。在本揭露中，該銲錫凸塊103內部的曲率半徑具有一正號(positive sign)，而該銲錫凸塊103外部的曲率半徑具有一負號(negative sign)。因為該銲錫凸塊103的周邊切面輪廓係連續的且無突兀的轉折點，故可在點A(正曲率)與點B(負曲 率)之間發現一零曲率點C。在本揭露之某些實施例中，圖1至圖4所示之接面部位102呈現一沙漏形狀，因此可在該接點部位102內發現一零曲率點(zero curvature)。亦如圖6所示，可在該銲錫凸塊103的接面部位發現一最窄寬度W'。此處所提及的接面部位可視為先前在圖1至圖4描述的接面部位102。在一相同的水平線上，該最窄寬度W'對應於該接面部位之一切面輪廓之一點K。在某些實施例中，在該接點墊片101與該點K之間形成的一角度θ係一銳角。在其他實施例中，在該接點墊片101與該點L之間形成的角度θ小於90度。
圖7A至7E顯示一製造半導體封裝件的方法中之操作。為了簡化起見，與圖1及圖2中元件共用相同元件符號者在此不重覆赘述。在圖7A中，一銲錫膠層301形成在一接點墊片101上。銲錫膠層係在一助銲劑媒介材料中的均勻且穩定懸浮的銲錫顆粒，且在某些實施例中，該銲錫膠層係藉由如絲網或模板印刷(screen or stencil printing)或點膠(dispensing)之方法而施加。在某些實施例中，銲錫膠之製備包含在以松香為基礎的助銲劑媒介中混合下列銲錫顆粒之任何一者。舉例而言，該等銲錫顆粒包含(但不限定於)SnBix、SnSbx、SnPbx、SnGex、SnAlx、SnGax、SnInx、SnTlx及上述材料之任意組合。然而，該等銲錫顆粒並不限定於本段落所提供的元素，熔化溫度低於接著施加於其上之一銲錫球的任何含錫(Sn-containing)銲錫顆粒皆可應用在本揭露中。
在圖7B中，一銲錫凸塊103藉由落球(ball-dropping)或模板點膠(stencil dispensing)而設置在該銲錫膠層301上。在某些實施例中，該銲錫凸塊103的寬度W1與該銲錫膠層301的厚度Ts的比例(W1/Ts)被控制在大約2至大約5。在比例(W1/Ts)低於2的情況下，最終產出的銲錫凸塊之接面部位不會具有一沙漏形狀。如第7B圖所示，該接點墊片101之寬度W2被控制為小於該銲錫凸塊103之寬度W1。
在圖7C中，該銲錫凸塊103與該接點墊片101之間的一第一電性連接303係藉由液化該銲錫膠層301所形成。由於該銲錫膠層301經轉變為熔融狀態(molten state)，故重力使得該銲錫凸塊103陷入該銲錫膠層301中且與該接點墊片101物理連接。在某些實施例中，形成該第一電性連接303之操作包含藉由一紅外線燈、熱風槍(hot air pencil)、經加熱的傳送帶或者(更常見地)藉由使該銲錫膠層通過一經嚴密控制的加熱爐而將該銲錫膠層301加熱至一第一溫度。請注意，該第一溫度被控制為低於該銲錫凸塊103的熔化溫度且高於該銲錫膠層301的熔化溫度。在某些實施例中，該第一溫度低於大約攝氏170度，例如大約為攝氏165度。因為一SnBix銲錫膠層的熔點為大約攝氏140度且一Sn-Ag-Cu(SAC)銲錫球的熔點為大約攝氏217度，故大約攝氏165度之第一溫度使得該SnBix銲錫膠層液化，但該SAC銲錫球並未液化。
參照圖7D，該銲錫凸塊103的一下側部位為一液體鑄模化合物105所密封。為了簡化起見，關於該銲錫凸塊103的下側部位之論述請參照圖2相關內容，在此不再贅述。在某些實施例中，在密封該銲錫凸塊103之後進行一切割(die saw)操作。含有所欲I/O引腳(亦即，銲錫凸塊)之晶粒經切單且接合至一外部裝置(未繪示於圖中)。
參照圖7E，該銲錫凸塊103與一外部裝置200之間的一第二電性連接305係藉由液化該銲錫膠層301與該銲錫凸塊103兩者所形成。在某些實施例中，形成該第二電性連接305之操作包含藉由一紅外線燈、熱風槍(hot air pencil)、經加熱的傳送帶或者(更常見地)藉由使該銲錫膠層通過一經嚴密控制的加熱爐而將該銲錫凸塊103及該銲錫膠層301加熱至一第二溫度。請注意，該第二溫度被控制為高於該銲錫凸塊103的熔化溫度與該銲錫膠層301的熔化溫度。在某些實施例中，該第二溫度高於該第一溫度大約攝氏50度。因為一Sn-Ag- Cu(SAC)銲錫球的熔點為大約攝氏217度，故介於大約攝氏240度至大約攝氏260度之第二溫度使得該SnBix銲錫膠層液化及該SAC銲錫球兩者皆液化，在該銲錫凸塊103與該外部裝置200之一導電接點墊片201之間形成一第二電性連接305。
如圖7E所示，根據本揭露之某些實施例，形成有包圍該銲錫凸塊103的一上側部位的一填充層107。為了簡化起見，關於該銲錫凸塊103的上側部位之論述請參照圖2相關內容，在此不再贅述。
本揭露的某些實施例提供一種半導體封裝件，其中包含一接點墊片、一位於該接點墊片外部之裝置及位於該接點墊片上之一銲錫凸塊。該裝置具有對應於該接點墊片之一導電接點墊片。該銲錫凸塊連接該接點墊片與該導電接點墊片。該銲錫凸塊具有一高度及一寬度，該高度為自該銲錫凸塊的一頂部至該接點墊片，該寬度為該銲錫凸塊在一垂直於該高度的方向上之一最寬尺寸。該銲錫凸塊在接近該接點墊片處之一接面部位具有一沙漏形狀。
在本揭露之某些實施例中，該半導體封裝件進一步包括一包圍該接面部位與該銲錫凸塊之一下側部位的鑄模化合物。該鑄模化合物的厚度為該銲錫凸塊高度的大約0.4倍至大約0.6倍，且該銲錫凸塊之下側部位接近該接點墊片。
在本揭露之某些實施例中，該半導體封裝件進一步包括一包圍該銲錫凸塊的一上側部位之填充層。該銲錫凸塊的上側部位接近該銲錫凸塊的頂部。
在本揭露之某些實施例中，在該半導體封裝件中，該銲錫凸塊的高度對寬度之比值為大約0.85至大約1.15。
在本揭露之某些實施例中，該銲錫凸塊之該接面部位包括SnX合金，該SnX合金具有一低於攝氏165度之合金熔化溫度(alloy melting temperature)。
在本揭露之某些實施例中，該SnX合金中之該X材料包括鉍(Bi)、銻(Sb)、鉛(Pb)、鍺(Ge)、鋁(Al)、鎵(Ga)、銦(In)、鉈(Tl)及上述材料之任意組合。
在本揭露之某些實施例中，X材料的濃度自該銲錫凸塊的接面部位向該銲錫凸塊的頂部遞減。
在本揭露之某些實施例中，該銲錫凸塊的寬度大於該接點墊片的寬度。
在本揭露之某些實施例中，該銲錫凸塊包括錫(Sn)、銀(Ag)、銅(Cu)、鉛(Pb)、鎳(Ni)、鍺(Ge)、鉍(Bi)及上述材料之任意組合。
在某些實施例中，一半導體封裝件包括一包含複數個接點墊片之球柵陣列(BGA)，其中各該複數個接點墊片在一銲錫凸塊的一端與該銲錫凸塊連接。該BGA中的一最細微間距(pitch)小於大約0.2毫米。該半導體封裝件包括一包含複數個導電接點墊片之電路板，其中該複數個導電接點墊片之各者均在該銲錫凸塊的另一端與該BGA電性連接。該銲錫凸塊具有一高度(H)與一寬度(W1)，該高度(H)係自該銲錫凸塊的一頂部至該接點墊片，該寬度(W1)係該銲錫凸塊在一垂直於該高度的方向上之一最寬尺寸。該銲錫凸塊在接近該接點墊片處之一接面部位具有一沙漏形狀。
本揭露之某些實施例提供一種包括一球柵陣列(BGA)之半導體封裝件，該球柵陣列(BGA)中各銲錫凸塊均具有一包含一接點墊片及位於該接點墊片上之一銲錫凸塊的結構。該銲錫凸塊包括一高度及一寬度，該高度係自該銲錫凸塊的一頂部至該接點墊片，該寬度係該銲錫凸塊在一垂直於該高度的方向上之一最寬尺寸。該銲錫凸塊在接近該接點墊片處之一接面部位包括一沙漏形狀。該BGA中的一最細微間距(pitch)小於0.2毫米。
在本揭露之某些實施例中，該球柵陣列(BGA)中各銲錫凸塊均具有一零曲率點(zero curvature)。
本揭露之某些實施例提供一種製造半導體封裝件的方法。該方法包括：在一接點墊片上形成一銲錫膠層、在該銲錫膠層上設置一銲錫凸塊、在該銲錫凸塊與該接點墊片之間形成一第一電性連接、密封該銲錫膠層與該銲錫凸塊之一下側部位，其中該銲錫凸塊之該下側部位接近該接點墊片、及在該銲錫凸塊與一外部裝置之間形成一第二電性連接。
在本揭露之某些實施例中，該製造一半導體封裝件的方法進一步包括形成一包圍該銲錫凸塊的一上側部位之填充層。該銲錫凸塊的該上側部位接近該外部裝置。
在本揭露之某些實施例中，在製造該半導體封裝件的方法中，在該銲錫凸塊與該接點墊片之間形成該第一電性連接之操作包括加熱該銲錫膠層至一第一溫度。
在本揭露之某些實施例中，該銲錫膠之一熔點低於該第一溫度，且該第一溫度低於該銲錫凸塊之一熔點。
在本揭露之某些實施例中，該第一溫度低於攝氏170度。
在本揭露之某些實施例中，在製造該半導體封裝件的方法中，在該銲錫凸塊與該外部裝置之間形成該第二電性連接之操作包括加熱該銲錫膠層與該銲錫凸塊至一第二溫度。
在本揭露之某些實施例中，該銲錫膠之一熔點低於該銲錫凸塊之一熔點，且該銲錫凸塊之該熔點低於該第二溫度。
在本揭露之某些實施例中，該第二溫度高於該第一溫度達至少攝氏50度。
在本揭露之某些實施例中，在製造該半導體封裝件的方 法中，在該接點墊片上形成該銲錫膠層之操作包括形成一厚度T之銲錫膠，且在製造該半導體封裝件的方法中，在該銲錫膠層上設置該銲錫凸塊之操作包括將該銲錫凸塊設置成具有一寬度W。該寬度W係該銲錫凸塊在一水平方向上的最寬尺寸，且該寬度W對該厚度T之比值(W/T)為大約2至大約5。
雖然本揭露之內容及其優點已經詳細描述於前述說明書內容中，但應瞭解到在不違背本揭露之申請專利範圍所載技術之精神與範疇的情況下，本揭露之內容可為各種不同的變化、取代及置換。舉例而言，上述許多製程步驟可以不同的方法實現且可為其他製程步驟或其他製程步驟之組合所取代。
此外，本揭露之範疇不限定於本說明書所述製程、機器、製造、物質組成、手段、方法及步驟之特定實施例。所屬技術領域中具有通常知識者將可基於本揭露之內容輕易理解到可利用現有或稍後將被開發出來能夠達到與本揭露之對應實施例相同功能或結果的製程、機器、製造、物質組成、手段、方法或步驟。因此，本案申請專利範圍意欲涵蓋上述製程、機器、製造、物質組成、手段、方法或步驟之範疇。
θ‧‧‧角度
A‧‧‧點
B‧‧‧點
C‧‧‧點
r+‧‧‧正半徑
r-‧‧‧負半徑
W'‧‧‧寬度
K‧‧‧點
100‧‧‧載體
101‧‧‧接點墊片
103‧‧‧銲錫凸塊
500‧‧‧部分剖面

Claims (10)

  1. 一種半導體封裝件，其包括：一接點墊片；一裝置，其位於該接點墊片外部且包括對應於該接點墊片之一導電接點墊片；一銲錫凸塊，其利用該導電接點墊片連接該接點墊片，其中該銲錫凸塊包括：一高度，其係自該銲錫凸塊的一頂部至該接點墊片；及一寬度，其係該銲錫凸塊在一垂直於該高度的方向上之一最寬尺寸；及其中該銲錫凸塊在接近該接點墊片處之一接面部位包括一沙漏形狀；一鑄模化合物，包圍(surrounding)該接面部位以及該銲錫凸塊之一下側部位，但並未密封該銲錫凸塊之一上側部位；及一填充層，包圍該銲錫凸塊之該上側部位。
  2. 如請求項第1項之半導體封裝件，其中該鑄模化合物之一厚度為該銲錫凸塊高度的大約0.4倍至大約0.6倍，且其中該銲錫凸塊的該下側部位接近該接點墊片。
  3. 如請求項第1項之半導體封裝件，其中該銲錫凸塊之該接面部位包括SnX合金，該SnX合金包括一低於攝氏165度之合金熔化溫度。
  4. 如請求項第3項之半導體封裝件，其中該X材料的濃度自該銲錫凸塊的該接面部位向該銲錫凸塊的該頂部遞減。
  5. 一種半導體封裝件，其包括：一球柵陣列(BGA)，其包括複數個接點墊片，其中該複數個接 點墊片之各者均在一銲錫凸塊的一端與該銲錫凸塊連接，其中該BGA中的一最細微間距(pitch)小於大約0.2毫米；及一電路板，其包括複數個導電接點墊片，其中該複數個導電接點墊片之各者均在該銲錫凸塊的另一端與該BGA電性連接；其中該銲錫凸塊包括：一高度，其係自該銲錫凸塊的一頂部至該接點墊片；及一寬度，其係該銲錫凸塊在一垂直於該高度的方向上之一最寬尺寸；及其中該銲錫凸塊在接近該接點墊片處之一接面部位包括一沙漏形狀，且各銲錫凸塊均具有一零曲率點。
  6. 一種製造一半導體封裝件的方法，其包括：在一接點墊片上形成一銲錫膠層；在該銲錫膠層上設置一銲錫凸塊；在該銲錫凸塊與該接點墊片之間形成一第一電性連接；以一鑄模化合物密封該銲錫膠層與該銲錫凸塊之一下側部位，該鑄模化合物並未密封該銲錫凸塊之一上側部位；在該銲錫凸塊與一外部裝置之間形成一第二電性連接；以及形成一填充層包圍該銲錫凸塊之該上側部位；其中該銲錫凸塊之該下側部位接近該接點墊片。
  7. 如請求項第6項之製造一半導體封裝件的方法，其中該在該銲錫凸塊與該接點墊片之間形成該第一電性連接之操作包括加熱該銲錫膠層至一第一溫度。
  8. 如請求項第7項之製造一半導體封裝件的方法，其中該銲錫膠層之一熔點係低於該第一溫度，且其中該第一溫度係低於該銲錫凸塊之一熔點。
  9. 如請求項第7項之製造一半導體封裝件的方法，其中該在該銲錫凸塊與該外部裝置之間形成該第二電性連接之操作包括加熱該銲 錫膠層與該銲錫凸塊至一第二溫度。
  10. 如請求項第9項之製造一半導體封裝件的方法，其中該第二溫度高於該第一溫度達至少攝氏50度。
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CN104659002B (zh) 2018-12-14
TW201521170A (zh) 2015-06-01
US9355927B2 (en) 2016-05-31
KR20150060559A (ko) 2015-06-03
KR101685769B1 (ko) 2016-12-12
CN104659002A (zh) 2015-05-27
US20150145130A1 (en) 2015-05-28
US9935044B2 (en) 2018-04-03

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