CN104168004A - 电子元件及其制造方法 - Google Patents

电子元件及其制造方法 Download PDF

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CN104168004A
CN104168004A CN201410188208.0A CN201410188208A CN104168004A CN 104168004 A CN104168004 A CN 104168004A CN 201410188208 A CN201410188208 A CN 201410188208A CN 104168004 A CN104168004 A CN 104168004A
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pad
projection
substrate
electronic component
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CN104168004B (zh
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山内基
川内治
福田靖
石桥良庸
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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Abstract

电子元件及其制造方法。一种电子元件包括：基板，其由陶瓷形成，并包括位于该基板的上表面上的一个或更多个焊盘；元件，其利用接合至所述一个或更多个焊盘的一个或更多个凸块而倒装地安装在所述基板的所述上表面上；以及附加膜，其位于所述基板的下表面上，并在一个或更多个焊盘/凸块对中的每一对中与焊盘和凸块中的较小一方的至少一部分交叠，所述一个或更多个焊盘/凸块对由彼此接合的所述一个或更多个焊盘和所述一个或更多个凸块构成。

Description

电子元件及其制造方法
技术领域
本发明的特定方面涉及电子元件及其制造方法。
背景技术
诸如移动电话的通信装置采用：诸如表面声波(SAW)器件的声波器件，其用作滤波器或双工器；芯片元件，其包括电感器和电容器；以及电子元件，其包括诸如功率放大器(PA)和开关的半导体器件。为了减小电子元件的尺寸和高度，SAW器件和半导体器件通常被倒装地安装在基板上。日本特开2003-60334号公报公开了一种发明，其中LC滤波器和芯片元件被安装在基板上。日本特开2010-10165号公报公开了一种电子元件模块，其配备有传感器元件和半导体元件，并用于测量轮胎的压力。
当诸如SAW器件或半导体器件的元件被倒装地安装时，施加热以连接凸块，并且还对元件施加压力。应力也由于压力而被施加至基板，并且基板可能被损坏。
发明内容
根据本发明的一方面，提供了一种电子元件，该电子元件包括：基板，其由陶瓷形成，并包括位于其上表面上的一个或更多个焊盘；元件，其利用接合至所述一个或更多个焊盘的一个或更多个凸块而倒装地安装在所述基板的所述上表面上；以及附加膜，其位于所述基板的下表面上，并在一个或更多个焊盘/凸块对中的每一对中与焊盘和凸块中的较小一方的至少一部分交叠，所述一个或更多个焊盘/凸块对由彼此接合的所述一个或更多个焊盘和所述一个或更多个凸块构成。
根据本发明的另一方面，提供了一种制造电子元件的方法，该方法包括以下步骤：在由陶瓷形成的基板的下表面上形成附加膜；以及在形成所述附加膜之后，通过将一个或更多个凸块接合至位于所述基板的上表面上的一个或更多个焊盘来倒装地安装元件，使得所述附加膜在一个或更多个焊盘/凸块对中的每一对中与焊盘和凸块中的较小一方的至少一部分交叠，所述一个或更多个焊盘/凸块对由彼此接合的所述一个或更多个焊盘和所述一个或更多个凸块构成。
附图说明
图1A是示出根据第一实施方式的电子元件的截面图，图1B是示出电子元件的顶视图，图1C是示出电子元件的底视图；
图2A是示出SAW器件的下表面的图，图2B是SAW器件的放大截面图；
图3A是示出制造电子元件的方法的截面图，图3B是SAW器件的放大截面图；
图4A是示出根据第一比较例的电子元件的截面图，图4B是示出电子元件的底视图，图4C是示出制造电子元件的方法的截面图；
图5A是示出根据第二比较例的电子元件的截面图，图5B是示出电子元件的底视图，图5C是示出制造电子元件的方法的截面图；
图6A是示出根据第三比较例的电子元件的截面图，图6B是示出电子元件的底视图，图6C是示出制造电子元件的方法的截面图；
图7是示出仿真的概要的立体图；
图8A是示出模型A的截面图，图8B是示出模型A中的应力分布的底视图；
图9A是示出模型B的截面图，图9B是示出模型B中的应力分布的底视图；
图10A是示出模型C的截面图，图10B是示出模型C中的应力分布的底视图；
图11A是示出模型D的截面图，图11B是示出模型D中的应力分布的底视图；
图12A是示出模型E的截面图，图12B是示出模型E中的应力分布的底视图；
图13A是示出根据第二实施方式的电子元件的截面图，图13B是SAW器件的放大截面图；
图14A是示出制造电子元件的方法的截面图，图14B是SAW器件的放大截面图；
图15A是示出模型F的截面图，图15B是示出模型F中的应力分布的底视图，并示出了SAW器件被移位到右方的情况；
图16A是示出模型G的截面图，图16B是示出模型G中的应力分布的底视图，并示出了SAW器件被移位到右方的情况；
图17是根据第三实施方式的电子元件的SAW器件的放大截面图；
图18A是示出第四实施方式中的SAW器件的下表面的图，图18B是示出SAW器件的截面图；以及
图19A是示出实验中的受压位置的平面图，图19B是示出最大应力的图。
具体实施方式
现在将参照附图描述实施方式。
第一实施方式
图1A是示出根据第一实施方式的电子元件100的截面图，并且示出了沿着图1B中的线A-A截取的截面。图1B是示出电子元件100的顶视图。图1C是示出电子元件100的底视图。
如图1A和图1B所示，电子元件100包括基板10、半导体器件20、SAW器件22和芯片元件30。焊盘12位于基板10的上表面上，并且焊盘14、16和18位于下表面上。在基板10的上表面上，倒装地安装有半导体器件20和SAW器件22，并且还安装有芯片元件30。半导体器件20和SAW器件22在芯片元件30通过焊料32电连接至焊盘12的同时通过凸块24电连接至焊盘12。凸块24的直径R1小于焊盘12的宽度W1。如图1A和图1C所示，焊盘14位于半导体器件20下方，并且各个焊盘16位于对应的SAW器件22下方。焊盘18沿着基板10的边缘布置以包围焊盘14和16。焊盘18电连接至半导体器件20、SAW器件22和芯片元件30，并用于在电子元件100与外部基板之间输入和输出信号。例如，SAW器件22是包括接收滤波器和发送滤波器的SAW滤波器或双工器。半导体器件20用作功率放大器或开关。芯片元件30包括诸如电感器和电容器的无源元件，并且匹配未示出的天线与半导体器件20和SAW器件22之间的阻抗。
图2A是示出SAW器件22的下表面的图。如图2A所示，凸块24位于SAW器件22的下表面上。由SAW器件22的凸块24包围的区域被称作区域23，并且由图2A中的虚线指示。图2B是SAW器件22的放大截面图。如图2B所示，焊盘16的宽度W2等于区域23的宽度。SAW器件22的宽度W3大于宽度W2。尽管未示出，但是凸块24也位于半导体器件20的下表面上。焊盘14的宽度等于由半导体器件20中的凸块24包围的区域的宽度。
基板10由诸如陶瓷的绝缘材料形成。凸块24由主要由例如锡银(Sn-Ag)构成的焊料形成。焊盘12、14、16和18包括例如铜(Cu)、银(Ag)、钨(W)和钼(Mo)，并且它们的表面由具有焊料的高润湿性的金(Au)形成。
图3A是示出制造电子元件100的方法的截面图。如图3A所示，半导体器件20和SAW器件22由工具25吸取，并被布置在基板10上。在工具25在半导体器件20和SAW器件22上带来如箭头B指示的向下的压力(朝向基板10的压力)的同时，施加热。热压缩熔融焊料，并且凸块24接合至焊盘12。图3B是SAW器件22的放大截面图。如图3B所示，SAW器件22被设置在基板10上，使得整个区域23与焊盘16交叠，然后被倒装地安装。
在第一实施方式中，焊盘14和16减小了在倒装安装期间施加至基板10的应力。因此，防止了基板10被损坏。如图2B和图3B所示，优选地，焊盘16的宽度W2等于或大于区域23的宽度。焊盘16与整个区域23交叠，即，所有凸块24接合至SAW器件22。这样使得能够有效地降低施加至SAW器件22下方的基板10的应力。在具有焊盘16的情况下，优选地，焊盘14的宽度等于或大于由半导体器件20中的凸块24包围的区域(未示出)的宽度。不需要增厚基板10以防止损坏，进而可减小电子元件100的高度。
提供了对应于半导体器件20的焊盘14，并且提供了对应于SAW器件22的焊盘16。因此，当元件被倒装地安装时施加至基板10的应力减小，并且防止了基板10被损坏。而且，抑制了由于焊盘14和16与基板10之间的热膨胀系数的差异导致的基板10的翘曲。对基板10的翘曲的抑制改进了凸块24与焊盘12之间的连接的可靠性。例如，如第二比较例所述，提供与SAW器件22交叠的大的焊盘增大了基板10的翘曲。翘曲降低了凸块24与焊盘12之间的连接的可靠性。
焊盘14和16可用作用于输入和输出信号的端子或接地端子，或者可以是不具有电功能的虚设焊盘。作为焊盘14和16的替代，可提供由树脂形成的绝缘层。也就是说，在基板10的下表面上设置由金属或绝缘材料制成的附加膜可防止基板10被损坏。
现在将描述比较例。图4A是示出根据第一比较例的电子元件100R的截面图。图4B是示出电子元件100R的底视图。如图4A和图4B所示，焊盘14和16未布置在基板10的下表面上。图4C是示出制造电子元件100R的方法的截面图。半导体器件20和SAW器件22被倒装地安装在基板10上。如箭头B所指示，从工具25施加向下的压力。焊盘14和16没有位于与半导体器件20和SAW器件22交叠的位置中。因此，施加至基板10的应力大于第一实施方式中的情况。如图4C中的叉形标记所指示，压力在基板10中导致裂纹或者使基板10破裂，进而损坏基板10。
图5A是示出根据第二比较例的电子元件200R的截面图。图5B是示出电子元件200R的底视图。如图5A和图5B所示，单个焊盘17位于基板10的下表面上。焊盘17与半导体器件20以及邻近半导体器件20布置的两个SAW器件22交叠。在与其它两个SAW器件22交叠的位置处，焊盘不位于基板10的下表面上。图5C是示出制造电子元件200R的方法的截面图。如箭头B所指示，从工具25施加向下的压力。在布置了焊盘17的部分中，基板10几乎没有损坏。然而，在未布置焊盘17的部分中，施加至基板10的应力较高。因此，基板10被损坏，如图5C中的叉形标记所指示。另外，焊盘17较大，并且因此温度改变使得基板10由于基板10与焊盘17之间的热膨胀系数的差异而导致翘曲。翘曲降低了凸块24与焊盘12之间的连接的可靠性。
图6A是示出根据第三比较例的电子元件300R的截面图。图6B是示出电子元件300R的底视图。如图6A和图6B所示，两个焊盘17位于基板10的下表面上。各个焊盘17与两个SAW器件22交叠。在与半导体器件20交叠的位置处，焊盘未布置在基板10的下表面上。图6C是示出制造电子元件300R的方法的截面图。如图6C中的叉形标记所指示，半导体器件20下方的基板10被损坏。另外，焊盘17较大，进而温度改变容易引起基板10翘曲。随着基板10变薄，在第一比较例至第三比较例中，基板10更容易被损坏。此外，基板10翘曲(由于安装在上表面上的元件与形成在下表面上的焊盘之间的热膨胀系数的差异导致)的效果增加。因此，在第一比较例至第三比较例中，难以使基板10变薄，因此电子元件的高度减小。尤其是，由陶瓷形成的基板10是易碎的并且容易损坏。
现在将描述施加至基板10的应力的仿真。当未设置焊盘12和凸块24并且基板10被设置为直接接触SAW器件22时，计算施加至基板10的应力。将五个模型的应力进行比较。
图7是示出仿真的概要的立体图。如图7所示，基板10位于基座27上。SAW器件22位于基板10的上表面的中心，并且通过工具25向下施压。工具25和基座27由钢制成，并且压力为40N。位于基板10的下表面上的焊盘18由虚线示出。焊盘18的尺寸为0.5×0.5×0.02mm3。基板10是厚度为30μm的高温共烧陶瓷(HTCC)。
仿真使用了五个模型。表1示出了仿真中使用的SAW器件22和焊盘16的尺寸、SAW器件22和焊盘16是否彼此交叠以及应力的最大值的计算结果。
[表1]
如表1所示，模型A中未设置焊盘16。在模型B、C和E中，设置尺寸与SAW器件22的尺寸相同的焊盘16。模型D中的焊盘16比SAW器件22小。参照截面图和底视图，现在将描述各个模型的详细结构和应力。
图8A是示出模型A的截面图。图8B是示出模型A中的应力分布的底视图。图8B中的阴影指示的区域29是应力为5.0×107Pa或更大的区域。如图8A所示，未布置焊盘16，因此焊盘16与SAW器件22彼此不交叠，如表1所示。如图8B所示，区域29形成在基板10的中心处，并且靠近焊盘18中的一些。如表1所示，应力的最大值为4.1×108Pa。
图9A是示出模型B的截面图。图9B是示出模型B中的应力分布的底视图。如图9A所示，焊盘16从SAW器件22朝向图9A的左方偏离0.32mm。因此，如表1所示，焊盘16不与整个SAW器件22交叠而与其一部分交叠。在图9B中的焊盘16的右侧，SAW器件22不与焊盘16交叠并且应力较高。如表1所示，应力的最大值为8.6×107Pa。
图10A是示出模型C的截面图。图10B是示出模型C中的应力分布的底视图。如图10A和表1所示，焊盘16不与SAW器件22交叠。如图10B所示，区域29形成在基板10的中心。另外，区域29看上去靠近焊盘18中的一些。如表1所示，应力的最大值为3.7×108Pa。
图11A是示出模型D的截面图。图11B是示出模型D中的应力分布的底视图。如图11A所示，焊盘16比SAW器件22小，因此与SAW器件22的一部分交叠而不与整个SAW器件22交叠，如表1所示。如图11B所示，形成包括焊盘16的区域29。如表1所示，应力的最大值为5.7×107Pa。
图12A是示出模型E的截面图。图12B是示出模型E中的应力分布的底视图。如图12A和表1所示，焊盘16与整个SAW器件22交叠。如图12B所示，不形成区域29。如表1所示，应力的最大值为2.8×107Pa。
上述仿真揭示了可通过将焊盘直接设置在工具25所施压的部分之下来减小应力。当凸块24用于倒装安装时，可通过使焊盘16与由凸块24包围的区域23交叠来减小应力，如第一实施方式中所述。
第二实施方式
第二实施方式描述了焊盘14和16被放大的情况。图13A是示出根据第二实施方式的电子元件200的截面图。图13B是SAW器件22的放大截面图。
如图13A所示，第二实施方式中的焊盘14和16的宽度大于第一实施方式中的焊盘的宽度。如图13B所示，焊盘16比区域23宽，并且其宽度W3等于例如SAW器件22的宽度。焊盘14的宽度等于例如半导体器件20的宽度。凸块24由Au形成。
图14A是示出制造电子元件200的方法的截面图。如图14A所示，利用工具25将超声波施加至半导体器件20和SAW器件22，以使它们沿着箭头C所指示的横向振动。在使半导体器件20和SAW器件22振动的同时，施加箭头B所指示的向下的压力(朝向基板10的压力)，并且还施加热。该工艺将凸块24接合至焊盘12(二者均由Au制成)。半导体器件20和SAW器件22通过超声波沿着横向移位的量是例如几微米。图14B是SAW器件22的放大截面图。图14B中的点划线指示SAW器件22通过超声波移位至左侧。此时由SAW器件22的凸块24包围的区域被称作区域23a。虚线指示通过超声波被移位到右方的SAW器件22。此时由SAW器件22的凸块24包围的区域被称作区域23b。焊盘16的宽度较宽，进而即使SAW器件22移位，焊盘16也与区域23a和23b交叠。因此，利用超声波，在倒装安装中施加至基板10的应力减小。
为了减小应力，焊盘16的宽度大于区域23的宽度，并且焊盘14的宽度大于由半导体器件20的凸块24包围的区域的宽度就足够了。然而，随着焊盘14和16变大，基板10的翘曲增大。例如，为了抑制翘曲，焊盘16的宽度被形成为等于或小于SAW器件22的宽度，并且焊盘14的宽度被形成为等于或小于半导体器件20的宽度。焊盘14和16的宽度可根据基板10以及焊盘14和16的热膨胀系数而改变，并且焊盘16的宽度可被形成为等于或大于SAW器件22的宽度，并且焊盘14的宽度可等于或大于半导体器件20的宽度。
现在将描述仿真。在图7所示的结构中，SAW器件22受压并通过超声波沿着横向振动。使用了具有不同尺寸的焊盘16的两个模型。表2示出了仿真中使用的SAW器件22和焊盘16的尺寸、SAW器件22与焊盘16是否彼此交叠以及应力的最大值的计算结果。
[表2]
如表2所示，模型F中的焊盘16的尺寸与SAW器件22相同。模型G中的焊盘16在左侧和右侧比模型F中的焊盘16大50μm，即，总共大100μm。
图15A是示出模型F的截面图。图15B是示出模型F中的应力分布的底视图，并且示出了SAW器件22被移位到右方的情况。根据图8B，应力为5.0×107Pa或更大的区域被称作区域29，并由图15B中的阴影指示。如图15A所示，焊盘16与SAW器件22交叠。然而，当SAW器件22振动时，SAW器件22的一部分从焊盘16沿着水平方向移位。因此，如表2所示，焊盘16与SAW器件22的一部分交叠但不与整个SAW器件22交叠。随着SAW器件22从焊盘16的右边缘突出，施加至基板10的应力在焊盘16的右侧增大。结果，区域29形成在焊盘16的右侧，如图15B所示。如表2所示，应力的最大值为5.2×107Pa。
图16A是示出模型G的截面图。图16B是示出模型G中的应力分布的底视图，并示出了SAW器件22被移位到右方的情况。焊盘16的宽度宽，因此即使SAW器件22振动，焊盘16也与SAW器件22交叠，如表2所示。因此，未形成区域29，如图16B所示。如表2所示，应力的最大值为4.2×107Pa。上述仿真揭示了即使半导体器件20和SAW器件22振动也可通过将焊盘14和16的宽度制备得较宽来减小应力。尽管未示出，但是焊盘14和16在垂直于振动方向的方向(即，深度方向)上可被制备得较大。应力在深度方向上可减小。
第三实施方式
图17是根据第三实施方式的电子元件300的SAW器件22的放大截面图。尽管未示出，但是电子元件300包括半导体器件20，如电子元件100和200那样。如图17所示，焊盘12的宽度W1小于凸块24的直径R1。因此，由焊盘12包围的区域23c的宽度W4小于由凸块24包围的区域23的宽度W2。焊盘16的宽度W4等于例如区域23c的宽度。焊盘16与区域23c之间的交叠使得能够减小应力。尽管未示出，但是焊盘14与由半导体器件20的焊盘12包围的区域交叠就足够了。凸块24由主要由Sn-Ag构成的焊料形成，并且在不利用超声波的情况下被倒装地安装。
即使如第一实施方式和第三实施方式所述，凸块24由焊料形成，半导体器件20和SAW器件22也可通过经由超声波振动而被倒装地安装，如第二实施方式所述。可通过将焊盘14和16的宽度制备得较宽来减小应力。如第一实施方式至第三实施方式所述，在所有焊盘12/凸块24对中，焊盘14和16与焊盘12和凸块24中的较小一方交叠就足够了。例如，当SAW器件22通过单个凸块24接合至单个焊盘12时，焊盘16与焊盘12和凸块24中的较小一方交叠就足够了。
第四实施方式
第四实施方式描述了焊盘16与焊盘12和凸块24的至少一部分交叠的情况。图18A是示出第四实施方式的SAW器件22的下表面的图。图18A中的虚线指示位于基板10的下表面上的焊盘16。图18B是示出SAW器件22的截面图。如图18A和图18B所示，焊盘16比区域23小，并且与单个凸块24的一部分或整个单个凸块24交叠。
即使焊盘16与凸块24的至少一部分交叠，可减小应力。按压基板10中的多个位置，并且测量在所述位置产生的最大应力。图19A是示出实验中的受压位置的平面图。以10N的力按压图19A中示出的P1-P10。P1～P4不与焊盘16交叠。P5～P7中的每一个的一部分与焊盘16交叠。P8～P10中的每一个的整个与焊盘16交叠。
图19B是表示最大应力的图。水平轴表示受压位置，并且竖直轴表示最大应力。如图19B所示，P1～P4处的最大应力是1.4×108Pa～1.8×108Pa。由于受压位置更靠近焊盘16，所以应力减小。P5～P7处的最大应力为5.6×108Pa～6.6×108Pa，并小于P1-P4处的最大应力。当受压位置的一部分与焊盘16交叠时，最大应力减小至当受压位置不与焊盘16交叠时产生的最大应力的一半或一半以上。P8～P10处的最大应力为2.1×108Pa～2.9×108Pa，并且小于P5～P7处的最大应力。当整个受压位置与焊盘16交叠时，最大应力减小至当受压位置不与焊盘16交叠时产生的最大应力的十分之一。
如实验所揭示的，为了减小应力，凸块24的至少一部分与焊盘16交叠就足够了，如图18A和图18B所示。为了极大地减小应力，整个凸块24与焊盘16交叠，如图2A和图2B所示。当焊盘12的宽度W1小于凸块24的直径R1时，如图17所示，焊盘12的至少一部分与焊盘16交叠就足够了。如上所述，焊盘16在焊盘12/凸块24对中的每一对中与焊盘12和凸块24中的至少较小一方交叠就足够了，焊盘12/凸块24对中的焊盘12和凸块24彼此接合。在图2A和图18A的示例中，单个焊盘16与凸块24交叠。焊盘16可被设置为对应于各个凸块24。
要被倒装安装的元件可以是一个。要被倒装安装的元件不限于半导体器件20或SAW器件22。例如，诸如边界声波器件和薄膜体声波谐振器(FBAR)的声波器件可被倒装地安装。第一实施方式至第四实施方式可应用于包括倒装地安装在基板10上的至少一个元件在内的电子元件。
虽然已经详细描述了本发明的实施方式，但是应该理解，在不脱离本发明的精神和范围的情况下，可进行各种改变、替换和修改。

Claims (10)

1.一种电子元件，该电子元件包括：
基板，其由陶瓷形成，并包括位于该基板的上表面上的一个或更多个焊盘；
元件，其利用接合至所述一个或更多个焊盘的一个或更多个凸块而倒装地安装在所述基板的所述上表面上；以及
附加膜，其位于所述基板的下表面上，并在一个或更多个焊盘/凸块对中的每一对中与焊盘和凸块中的较小一方的至少一部分交叠，所述一个或更多个焊盘/凸块对由彼此接合的所述一个或更多个焊盘和所述一个或更多个凸块构成。
2.根据权利要求1所述的电子元件，其中，
所述凸块接合至所述焊盘，并且
单个附加膜与所述焊盘和所述凸块中的较小一方的至少一部分交叠。
3.根据权利要求1或2所述的电子元件，其中，
所述元件被倒装地安装在所述基板的所述上表面上，并且
所述附加膜被设置为与所述元件对应。
4.根据权利要求1或2所述的电子元件，其中，
所述附加膜比所述元件小。
5.根据权利要求1或2所述的电子元件，其中，
所述附加膜由金属形成。
6.根据权利要求1或2所述的电子元件，其中，
所述附加膜在所述一个或更多个焊盘/凸块对中的每一对中与所述焊盘和所述凸块中的较小一方的整个交叠。
7.一种制造电子元件的方法，该方法包括以下步骤：
在由陶瓷形成的基板的下表面上形成附加膜；以及
在形成所述附加膜之后，通过将一个或更多个凸块接合至位于所述基板的上表面上的一个或更多个焊盘来倒装地安装元件，使得所述附加膜在一个或更多个焊盘/凸块对中的每一对中与焊盘和凸块中的较小一方的至少一部分交叠，所述一个或更多个焊盘/凸块对由彼此接合的所述一个或更多个焊盘和所述一个或更多个凸块构成。
8.根据权利要求7所述的方法，其中，
所述附加膜的形成包括形成多个所述附加膜；并且
所述元件的倒装安装包括倒装地安装所述元件以与所述附加膜对应。
9.根据权利要求7或8所述的方法，其中，
所述元件的倒装安装包括利用超声波沿着所述基板的所述上表面的延伸方向振动所述元件来倒装地安装所述元件。
10.根据权利要求7或8所述的方法，其中，
所述附加膜在所述一个或更多个焊盘/凸块对中的每一对中与所述焊盘和所述凸块中的较小一方的整个交叠。
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