CN104054171B - 用于基板接合的平坦化基板表面 - Google Patents

用于基板接合的平坦化基板表面 Download PDF

Info

Publication number
CN104054171B
CN104054171B CN201280053476.0A CN201280053476A CN104054171B CN 104054171 B CN104054171 B CN 104054171B CN 201280053476 A CN201280053476 A CN 201280053476A CN 104054171 B CN104054171 B CN 104054171B
Authority
CN
China
Prior art keywords
layer
insulator layer
substrate
conductive features
top surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201280053476.0A
Other languages
English (en)
Other versions
CN104054171A (zh
Inventor
E·C·库尼
J·S·杜恩
D·W·马丁
C·F·马桑特
B-A·雷尼
师利仁
E·J·斯普罗吉斯
曾康怡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN104054171A publication Critical patent/CN104054171A/zh
Application granted granted Critical
Publication of CN104054171B publication Critical patent/CN104054171B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4825—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05187—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05687—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80054—Composition of the atmosphere
    • H01L2224/80075—Composition of the atmosphere being inert
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/804—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/80486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/80487—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80905—Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
    • H01L2224/80907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

公开了用于接合基板表面的方法、接合基板组件和用于接合基板组件的设计结构。通过使用器件基板(10)的第一表面(15)形成产品芯片(25)的器件结构(18、19、20、21)。在产品芯片上形成用于器件结构的互连结构的布线层(26)。布线层被平整化。临时操作晶片(52)被可去除地接合到平整化后的布线层。响应可去除地将临时操作晶片接合到平整化后的第一布线层，器件基板的与第一表面相对的第二表面(54)被接合到最终操作基板(56)。然后从组件去除临时操作晶片。

Description

用于基板接合的平坦化基板表面
技术领域
本发明涉及半导体器件制造，特别是涉及用于接合基板表面的方法、接合基板组件和用于接合基板组件的设计结构。
背景技术
蓝宝石上硅(SOS)是一般适于需求的器件应用的绝缘体上硅(SOI)半导体制造技术中的一种。SOS基板包含蓝宝石的绝缘块体晶片和绝缘块体基板上的硅的高质量器件层。蓝宝石基板事实上消除了在块体硅技术中出现的寄生漏电容。形成SOS基板的常规方法是在高温下将薄硅层沉积于块体蓝宝石晶片上，并可包含非晶表面层的外延再生长。通常在加热蓝宝石基板上通过硅烷气体(SiH4)的分解来沉积硅。利用器件层制造器件结构。
需要改进的扩展接合基板制造技术的能力的用于接合基板表面的方法、接合基板组件和用于接合基板组件的设计结构。
发明内容
根据本发明的一个实施例，提出了一种涉及具有第一表面和与第一表面相对的第二表面的器件基板的基板接合方法。该方法包括利用器件基板的第一表面形成至少一个产品芯片的器件结构；形成用于至少一个产品芯片的器件结构的互连结构的布线层；并将布线层平整化。响应于将布线层平整化，将临时操作晶片可去除地接合到布线层。响应于将临时操作晶片可去除地接合到布线层，将器件基板的第二表面接合到最终操作基板。
根据本发明的另一实施例，提出了一种接合基板组件，包括包含第一表面和与第一表面相对的第二表面的器件基板。该设计结构进一步包含接合到器件基板的第二表面的最终操作基板和具有在器件结构的第一表面上的器件结构的至少一个产品芯片。该设计结构进一步包含用于器件结构的互连结构。互连结构包含具有顶面的层间电介质层、突出于顶面之上第一导电特征、以及突出于顶面之上第二导电特征。第二导电特征通过间隙与第一导电特征横向地分开。并且，第一导电特征和第二导电特征具有相对于顶面测量的高度。至少一个绝缘体层填充间隙并具有相对于顶面测量的厚度，该厚度大于第一导电特征和第二导电特征的高度。
根据本发明的另一实施例，提出了一种可被用于集成电路的设计、制造或仿真的机器读取的设计结构，该设计结构包括包含第一表面和与第一表面相对的第二表面的器件基板。该设计结构进一步包括接合到器件基板的第二表面的最终操作基板以及具有在器件结构的第一表面上的器件结构的至少一个产品芯片。该设计结构进一步包括用于器件结构的互连结构，所述互连结构包含具有顶面的层间电介质层、突出于顶面之上的第一导电特征、以及突出于顶面之上的第二导电特征，第二导电特征通过间隙与第一导电特征横向地分开，并且，第一导电特征和第二导电特征具有相对于顶面测量的高度。至少一个绝缘体层填充间隙并具有相对于顶面测量的厚度，该厚度大于第一导电特征和第二导电特征的高度。该设计结构包含网单。该设计结构还可作为用于交换集成电路的布局数据的数据格式驻留于存储介质上。该设计结构可驻留于可编程门阵列中。
附图说明
包含于本说明书中并构成其一部分的附图示出本发明的各种实施例，并与以上给出的本发明的一般描述和以下给出的实施例的详细描述一起用于解释本发明的实施例。
图1～7是用于形成根据本发明的实施例的接合基板组件的基板接合处理的连续阶段的剖视图。
图1A是图1的基板的放大图。
图8是图4所示的晶片接合处理的阶段中的器件基板上的相邻的裸片的剖视图。
图9是根据本发明的替代性实施例的基板接合处理中的阶段的与图2类似的剖视图。
图10根据本发明的替代性实施例的基板接合处理中的阶段的与图3类似的剖视图。
图11根据本发明的替代性实施例的基板接合处理中的初始阶段的与图5类似的剖视图。
图12是用于半导体设计、制造和/或测试中的设计处理的流程图。
具体实施方式
一般地，本发明的实施例涉及晶片或基板的接合，特别是涉及改善基板的接合完整性。器件基板的一个表面包含具有有源器件结构以及可加入无源器件结构的后端(BEOL)结构的裸片。可通过将器件基板的表面平整化来提供改进的接合完整性，该表面可以是BEOL互连结构的布线层的露出表面，该露出表面与器件基板的在接合处理中与其它基板关联的表面相对。换句话说，平整化的表面不是参与接合处理的接触表面，而是在开始以可去除的方式与诸如玻璃基板的临时操作基板耦合的相对表面。临时操作基板在将器件的接触表面与最终操作基板结合的接合处理中提供机械支持，并在晶片接合之后被去除。得到的接合基板组件可在例如高性能射频集成电路中获得使用。
参照图1，并且，根据本发明的实施例，绝缘体上半导体(SOI)基板的代表形式的器件基板10包含块体基板12、器件层14和将器件层14与块体基板12分开的埋入绝缘体层16。器件层14包含半导体材料，诸如单晶硅或主要包含硅的其它单晶材料。块体基板12也可由诸如单晶硅的半导体材料构成。埋入绝缘体层16可包含电绝缘材料，特别是可以是包含二氧化硅(例如，SiO2)的埋入氧化物层。埋入绝缘体层16使块体基板12与明显比块体基板12薄的器件层14电隔离。器件层14沿连续的平面界面与埋入绝缘体层16的顶面直接接触。可通过本领域技术人员熟悉的诸如晶片接合技术或注氧隔离(SIMOX)技术的任何适当的常规技术来制造器件基板10。器件层14和埋入绝缘体层16的厚度可作为制造处理的设计参数被选择。
块体基板12、器件层14和埋入绝缘体层16各自分别沿横向延伸到器件基板10的外周缘17，在图1A中能最清楚地看到这一点。器件层14具有通过器件层14的厚度与埋入绝缘体层16分开的表面15。块体基板12具有通过块体基板12的厚度与埋入绝缘体层16分开的表面13。器件基板10的彼此相对的表面13、15沿横向延伸到器件基板10的外周缘17并分别构成器件基板10的前后表面。外周缘17从表面13延伸到表面15。由此，表面13、15通过块体基板12、器件层14和埋入绝缘体层16的合成厚度t彼此分开。器件层14和/或埋入绝缘体层16可几乎延伸到外周缘17，但终止于外周缘17附近处(例如，1mm～5mm)。
在前端(FEOL)处理中，利用器件层14的表面15上的各区域来制造器件结构18、19、20和21，作为产品芯片25的集成电路的有源电路。通过跨器件基板10的表面15使用所描述的处理流程来并行地制造产品芯片25(图1A)。通过本领域技术人员熟悉的FEOL技术形成产品芯片25上的器件结构18～21，并且，各产品芯片25可包含分布于跨器件层14的不同位置处的多个器件结构类型。集成电路的有源电路可包含诸如场效应晶体管、双极结晶体管、结场效应晶体管等的器件。
在代表性的实施例中，器件结构18～21是通过本领域技术人员熟悉的互补金属氧化物半导体(CMOS)工艺制造的场效应晶体管。器件结构18～21中的每一个包含栅电极、位于栅电极与器件层14之间的栅电介质层、和器件层14的半导体材料中的源区/漏区。构成栅电极的导体可包含例如金属、硅化物、多结晶硅(多晶硅)或通过CVD工艺等沉积的任何其它适当的材料。栅电介质层可包含任何适当的电介质或绝缘材料，包含但不限于二氧化硅、氧氮化硅、诸如氧化铪或氧氮化铪的高k电介质材料或这些电介质材料的分层组合。可通过使用在45nm、32nm、22nm和其它先进技术节点中使用的先栅极方法或后栅极(替换金属栅极)方法形成器件结构18-21。可通过用离子注入、掺杂剂扩散或它们的组合来掺杂器件层14的半导体材料，来形成源区/漏区。器件结构18-21可包含诸如晕圈(halo)区域、轻度掺杂漏极(LDD)区域等的其它部分。例如，通过标准块体CMOS工艺特有的常规的图案化、蚀刻、电介质填充和平整化处理，在器件层14中形成为器件结构18-21提供电隔离的浅沟槽隔离区域。
随后进行标准后端(BEOL)处理以制造连接有源器件结构18-21的互连结构，以在产品芯片25中的每一个上形成希望的集成电路。互连结构可包含与器件结构18-21耦合的布线层，并且可包含支持用于信号、时钟、电力等的导电路径的多达8个以上的布线层。在代表性的实施例中，互连结构是具有布线层22、24、26的多级互连结构。诸如二极管、电阻器、电容器、变容二极管和电感器的无源电路元件可集成到互连结构中。
布线层22包含配置于层间电介质层28中的互连线和导体填充通孔形式的多个导电特征30。导电特征30与器件结构18-21耦合并且通过层间电介质层28被电绝缘。布线层24包含作为导电特征配置于层间电介质层32中的导体填充通孔38。导体填充通孔38通过层间电介质层32被电绝缘。导电特征30之间以及导体填充通孔38之间的间隙分别被层间电介质层28、32的电介质材料填充。
本领域技术人员可以理解，可通过镶嵌工艺特有的沉积、抛光、光刻和蚀刻技术形成布线层22、24。特别地，层间电介质层28被沉积，并且，通过使用已知的光刻和蚀刻技术在层间电介质层28中限定通孔开口和/或沟槽的图案。得到的通孔开口和/或沟槽与衬套(即，钽和氮化钽的双层)对齐。导体(例如，铜)的厚层沉积于层间电介质层28上以溢出通孔和/或沟槽。通过诸如化学机械抛光(CMP)处理，导体层被平整化，从而将导体去除直至层间电介质层28的顶面的水平以保持导电特征30。通过使用层间电介质层28重复该处理以形成布线层24的导体填充通孔38。特别地，在镶嵌工艺中，可在形成布线层24的导体填充通孔38时将层间电介质层32的顶面31平整化。在本发明中，也可使用诸如消减铝图案化的其它的金属化方法，以构建一个或更多个布线层22、24。
用于布线层22、24的导体的候选导电材料包含但不限于铜(Cu)、铝(Al)或这些金属的合金。可通过化学气相沉积(CVD)或诸如电镀或无电镀的电化学工艺来沉积这些类型的金属。层间电介质层28、32可包含任何适当的有机或无机电介质材料，诸如SiO2、富氢碳氧化硅(SiCOH)、氟硅酸盐玻璃(FSG)或可通过诸如低压化学气相沉积(LPCVD)或等离子体增强化学气相沉积(PECVD)的CVD来沉积的其它类型的低k电介质材料。
作为可选地在布线层24中出现的代表性的无源电路元件，示出MIM电容器27。MIM电容器27包含板电极和作为电绝缘体设置在各相邻的板电极对之间的板间电介质层。但是，可从互连结构中省略MIM电容器27。
作为特定互连结构中的顶部布线层的布线层26包含分别接触层间电介质层32的顶面31的布线34和接合焊盘36。接合焊盘36通过导体填充通孔38与布线层22中的导电特征30并与MIM电容器27电耦合且机械耦合。导体填充通孔38可包含通过CVD沉积的一个或更多个难熔金属，比如钨(W)。
布线34和接合焊盘36可以是通过使用消减蚀刻处理用铝冶金法制造的导电特征。在代表性的实施例中，布线34和接合焊盘36直接接触层间电介质层32的顶面31。但是，诸如Ti/TiN双层的衬套层可作为扩散壁垒位于层间电介质层32与布线34之间以及层间电介质层32与接合焊盘36之间。
布线34可被用作用于跨各产品芯片25传送信号和电力的线。接合焊盘36可以是与正电源电压(VDD)或接地电压(VSS)耦合的电力分配焊盘、用于向或从产品芯片25上的有源电路(例如，器件结构18-21)传送信号的I/O焊盘、或与产品芯片25的有源电路电隔离的伪焊盘。在分割为裸片之后，可通过大量的不同技术中的任一种(例如通过压缩焊接或者C4(控制塌陷芯片连接，Controlled Collapse Chip Connection))使用接合焊盘36和其它类似的接合焊盘将产品芯片25与诸如电路板的其他结构物理耦合和电耦合。
布线34和接合焊盘36各自突出于层间电介质层32的顶面31之上，并包含以高度h与顶面31间隔开的各顶面35a～d。布线34和接合焊盘36的高度h可以为0.5μm或更高的量级，并且可高达4～5μm或者可以甚至更高。接合焊盘36的顶面35b的表面积可比布线34中的一些或全部的各顶面35a、35c、35d的表面积大。在布线34和接合焊盘36与层间电介质层32的顶面31之间存在未填充且开放的间隙37a～c。间隙37a～c具有等于布线34和接合焊盘36的高度h的高度。顶面31的各表面区域通过可具有各种宽度并且不限于具有相同宽度的间隙37a～c被露出。
参考图2，其中用类似的附图标记表示与图1类似的特征，并且在随后的制造阶段中，在层间电介质层32的顶面31的露出表面区域上以及在布线34和接合焊盘36的顶面35a～d上，形成绝缘体层40。用于绝缘体40的候选电介质材料可包含但不限于硅的氧化物(例如，SiO2)、FSG、氮化硅(Si3N4)或氧氮化硅。在一个实施例中，绝缘体层40包含利用包括硅烷(SiH4)、氧气(O2)和氩气(Ar)的处理气体的混合物通过高密度等离子体化学气相沉积(HDPCVD)处理沉积的二氧化硅。由于向形成绝缘体层的沉积处理增加溅射部分，因此，HDPCVD处理可被控制以有效地促进沉积中的间隙填充。特别地，绝缘体层40的电介质材料可以以包含最少的缝隙或空隙的状态填充布线34和接合焊盘36之间的间隙37a～c，并且，在一个实施例可以没有空隙。
绝缘体层40具有可沿层间电介质层32的顶面31的法向测量的层厚t1。在代表性的实施例中，层厚t1约等于布线34和接合焊盘36的高度h。但是，绝缘体层40的层厚t1可小于高度h或大于高度h。绝缘体层40的填充间隙37a～c的部分用于减小间隙深度。布线34和接合焊盘36的分布特征在绝缘体层40中被再现，使得绝缘体层40的顶面39不共面，其中峰覆盖布线34和接合焊盘36，而谷覆盖间隙37a～c。峰与谷之间的高度差约等于布线34和接合焊盘36的高度h。在正视图中，在从峰到谷的各过渡处出现台阶。
绝缘体层42保形地沉积于绝缘体层40的顶面39上。用于绝缘体层42的候选电介质材料可包含但不限于诸如SiO2的硅的氧化物或通过例如PECVD处理保形沉积的FSG。绝缘体层42在垂直和水平表面上可以是高度保形的(即，具有大致相同的厚度，例如，处于平均厚度的±2％～±5％内)。在一个实施例中，绝缘体层40和42可包含相同的电介质材料。
绝缘体层42具有可沿层间电介质层32的顶面31的法向测量的层厚t2。绝缘体层42可比绝缘体层40薄，并且，在代表性的实施例中，绝缘体层42的层厚t2可小于绝缘体层40的层厚t1的50％。增加绝缘体层42会增加电介质材料的附加厚度，特别是增加绝缘体层40的占据间隙37a～c的部分上的电介质材料的附加的覆盖层。
来自布线34和接合焊盘36的绝缘体层40中的分布特征在绝缘体层42中被再现。作为结果，绝缘体层42的顶面41与覆盖布线34和接合焊盘36的峰和覆盖间隙37a～c的谷不共面。峰谷距离约等于布线34和接合焊盘36的高度h。特别地，在正视图中，在布线34和接合焊盘36上的绝缘体层40、42的升高部分与间隙37a～c上的绝缘体层40、42的降低部分之间存在高度差Δ形式的台阶高度。
在替代性实施例中，可从处理流程省略绝缘体层42的沉积。省略绝缘体层42且仅存在绝缘体层40可能适于布线34和接合焊盘36之间的间隔足够大的情况。绝缘体层40、42还可覆盖设置在外周缘17内的所有器件基板10，特别是可覆盖所有的产品芯片25。包含绝缘体层40、42的电介质材料可具有大于诸如聚酰胺的聚合物材料的硬度和/或刚度。可结合绝缘体层40、42施加附加层，并且附加层可具有与绝缘体层40、42之一或两者相比类似或不同的成分。绝缘体层40、42之一或两者可被分为单独沉积但累积提供总目标层厚的子层。
参考图3，其中用类似的附图标记表示与图2类似的特征，并且在随后的制造阶段中，施加诸如化学机械抛光(CMP)的抛光处理，以使绝缘体层40、42平整化，以提供具有没有或者缺少源自布线34和接合焊盘36的明显分布特征的平坦化顶面46的复合绝缘体层44。绝缘体层40的残留部分接触布线34和接合焊盘36的顶面区域。绝缘体层40的残留部分接触间隙37a～c中的层间电介质层32的顶面31的表面区域，并且，绝缘体层42的残留部分接触绝缘体层40的这些残留部分。
作为抛光的结果，绝缘体层44包含具有横向和/或堆叠布置的绝缘体层40、42的复合体，并可具有小于绝缘体层42的厚度t2的厚度t3。虽然绝缘体层40、42的断面被示为绝缘体层44的分段的断面，但本领域技术人员可以理解，绝缘体层40、42的断面可不具有很好地限定的边界，并可包含电介质材料的连续邻接断面。为了提高结束CMP处理时的顶面46的平整性，绝缘体层42提供电介质材料的附加的覆盖层。
绝缘体层40、42的表面分布特征通过CMP处理被平坦化和平滑化以形成绝缘体层44的平整化的顶面46。为了执行CMP处理，器件基板10被加载到CMP系统中，使得最高点突出于与抛光盘直接接触的绝缘体层42的顶面41之上。器件基板10被压在抛光盘上，并且，料浆被分配到抛光盘上。料浆可包含具有碱性pH值的载体流体和悬浮于载体流体中的摩擦材料(例如，细分的硅石)。器件基板10和抛光盘相对于彼此旋转和/或振荡以结合施加的压力产生机械力。在绝缘体层40、42之间捕获的料浆首先去除绝缘体层40、42的高点，并在完全去除绝缘体层42的位置上去除绝缘体层40。CMP处理中的材料去除将在亚微米级上抛光基板表面的蚀刻效果和研磨相结合。CMP处理持续给定的抛光时间，或者直到出现检测到的结束点。优选地，抛光处理部分地去除绝缘体层42但不去除绝缘体层42的整个厚度，使得布线34和接合焊盘36被复合绝缘体层44的厚度t3覆盖。在CMP处理之后，可从顶面46清除残留的料浆。可通过使用本领域技术人员已知的用于抛光绝缘体层40、42的电介质材料(例如，二氧化硅)的标准抛光盘和料浆用商业CMP工具进行CMP处理。
这里使用的平整化是平坦化和平滑化绝缘体层40、42以提供绝缘体层44的缺少底层器件结构18-21的大部分或全部分布特征的平滑和平坦顶面46的处理(例如，CMP处理)。通过在绝缘体层40、42中沉积附加的电介质材料并然后反向抛光电介质材料以去除来自布线34和接合焊盘36的分布特征，实现平整化。
高度差Δ(图2)可通过平整化明显减小，并可被减小以提供绝缘体层44的所有区域的平整性。但是，可仍对绝缘体层44的覆盖器件结构18-21的区域和绝缘体层44的覆盖间隙37a～c的区域保持台阶高度差，同时仍考虑顶面46的平整化。台阶高度差源自绝缘体层44覆盖器件结构18-21的图案化区域和绝缘体层44覆盖间隙37a～c的非图案化区域的抛光率差。在一个实施例中，台阶高度差可处于布线34和接合焊盘36的原高度的10％或更小的量级。例如，如果布线34和接合焊盘36的高度为4μm，那么台阶高度差可以为0.4μm或更小。
分布特征可跨整个器件基板10减小，使得平坦化和平滑化的绝缘体层44在外周缘17内沿周围覆盖整个表面区域，特别是与所有的产品芯片25对应的表面区域。
参考图4，其中用类似的附图标记表示与图3类似的特征，并且在随后的制造阶段中，在与接合焊盘36的表面区域的一部分对应的绝缘体层44中限定开口48。可通过光刻法和蚀刻处理在绝缘体层44中限定开口48。光刻处理可能需要在绝缘体层44的顶面46上施加诸如感光聚酰亚胺(PSPI)的感光聚合物、软固化、通过光掩模将抗蚀剂曝光为有效地在开口48的预期位置上在抗蚀剂中限定潜在窗口的放射图案、显影以形成窗口和硬固化。可通过在溶剂中溶解聚合物以形成前体、跨顶面46通过旋转涂敷处理将前体展开为涂层、以及然后使涂层变干以去除溶剂并部分地酰亚胺化和交联聚合物，来制备感光聚合物。
通过依赖于作为蚀刻掩模的图案化抗蚀剂的、诸如反应离子蚀刻(RIE)的各向异性干蚀刻，来实现在感光聚合物中的窗口内形成开口48的蚀刻处理。可通过不同的蚀刻化学品在单个蚀刻步骤或多个蚀刻步骤中进行蚀刻处理，如果包含氧化物的话，则包含用于绝缘体层44的标准氧化物RIE处理。可在形成开口48之后从顶面46去除感光聚合物。绝缘体层44可保留于布线34上，使得布线34保持被电介质材料覆盖。感光聚酰亚胺可通过诸如氧等离子体暴露的灰化或诸如HF溶液的化学溶液来剥离。
在替代性实施例中，接合焊盘36的开口可在处理流程中推迟直到涉及最终操作基板的转移动作之后。
参考图5，其中用类似的附图标记表示与图4类似的特征，并且在随后的制造阶段中，粘接剂层50被施加到绝缘体层44的顶面46上，并且，临时操作基板52通过粘接剂层50与绝缘体层44粘性接合。临时操作基板52足够厚，以用于在随后的处理步骤中减薄块体基板12之后的机械操作。临时操作基板52可包含玻璃且粘接剂层可包含聚合物粘接剂。粘接剂层50的粘接强度被选择为使得可从顶面46去除临时操作基板52。作为粘接剂接合的替代，也可使用其它的技术以临时附接临时操作基板52。
参考图6，其中用类似的附图标记表示与图5类似的特征，并且在随后的制造阶段中，通过研磨、蚀刻和/或CMP完全去除块体基板12，以露出埋入绝缘体层16的表面54。埋入绝缘体层16可通过CMP或其它的抛光处理或蚀刻处理被部分去除，使得埋入绝缘体层16在前进到下一制造阶段之前被减薄。但是，埋入绝缘体层16在结束本制造阶段时不被完全去除，使得表面54处于相对于埋入绝缘体层16的初始厚度的中间位置上。
参考图7，其中用类似的附图标记表示与图6类似的特征，并且在随后的制造阶段中，器件基板10的器件层14、器件结构18-21、BEOL互连结构的布线层22、24以及布线34和接合焊盘36作为从临时操作基板52到最终操作基板56的转移层被原样转移以形成组件。特别地，通过去除块体基板12露出的埋入绝缘体层16的表面54与最终操作基板56的表面58接触，并且，这些表面54、58被接合在一起。在各种实施例中，最终操作基板56可包含蓝宝石、诸如砷化镓(GaAs)的III-V族半导体材料、玻璃、氧化硅晶片、蓝宝石上的氧化物层等。如果最终操作基板56包含蓝宝石基板且器件层14包含硅，那么接触表面54、58之间的接合可形成蓝宝石上硅(SOS)基板。最终操作基板56具有通过最终操作基板56的厚度与表面58分开的另一表面59。
接触表面54、58可通过将接触表面54、58暴露于能够增加它们的相互接合能力的条件的接合处理被接合在一起。平坦、平滑且清洁的表面54、58可在不存在中间层或外力的情况下通过直接接合被结合。当表面54、58进入接触关系时，基于诸如范德瓦尔兹力的物理力出现弱的接合。晶片对然后在足够的温度下和足够的持续期内经受低温热处理或退火以使物理力转变成化学接合。例如，代表性的接合处理可包含在小于或等于400℃的温度下以足以促进接触表面之间的表面间接合的持续期进行的热退火。热退火的温度足够低，使得温度敏感的器件结构18-21和可能的其它结构不会明显地受到不利影响。通过诸如等离子体激活或化学激活的预处理，可降低热退火的温度。可选地，器件基板10和最终操作基板56可在热退火中被夹在一起以提供压紧。还一般在包含诸如N2的非氧化气体的受控气氛中执行可在存在或不存在外力的情况下执行的热退火。
通过粘接剂层50调整的器件基板10与临时操作基板52的接合强度比器件基板10与最终操作基板56的接合强度弱。作为结果，可通过沿粘接剂层50与绝缘体层44的顶面56之间的相对较弱的界面的优先分层来释放和去除临时操作基板52。最终结果是，最终操作基板56与埋入绝缘体层16的电介质材料结合。可通过例如灰化处理从粘接剂层50去除残留粘接剂。
在通过使用器件层14制造产品芯片25(图1A)之后，并且，在示出的实施例中，在制造互连结构的布线层22、24之后，出现最终操作基板56与器件基板10的接合。由此，在代表性的实施例中，在完成FEOL处理和BEOL处理之后，出现层转移。
布线34和接合焊盘36的平整化在绝缘体层44上提供了与临时操作基板52接合并与块体基板12的表面13和埋入绝缘体层16的表面54相对的、平坦化且平滑的顶面46。电介质材料对间隙37a～c的填充以及对布线34和接合焊盘36产生的表面分布特征的减少改善了在接触表面54、58之间出现的晶片接合的完整性和质量。晶片接合完整性的改善不依赖于诸如MIM电容器27的无源元件的有无。通过对与器件基板10的埋入绝缘体层16的(与最终操作基板56的表面58的接合处理所涉及的)表面54相对的顶面46进行平整化来获得接合完整性的改善。平整化的顶面46可在物理上与器件基板10的埋入绝缘体层16的(与最终操作基板56的表面58的接合处理所涉及的)表面54区分，但是是与表面54相对的表面。在向最终操作基板56转移转移层之前，平整化的顶面46以可去除的方式与临时操作基板52耦合。
绝缘体层44的顶面46通过块体基板12、埋入绝缘体层16、器件层14和互连结构的布线层22、24的厚度与块体基板12的表面13分开。在先于晶片接合而去除块体基板12之后，绝缘体层44的顶面46与块体基板12的表面13相对，并且通过埋入绝缘体层16、器件层14和互连结构的布线层22、24的厚度与埋入绝缘体层16的表面54分开。
参考图8，其中用类似的附图标记表示与图4类似的特征，产品芯片60、62是产品芯片25(图1A)的代表，并且，产品芯片60、62中的每一个包含图4所示的平整化结构的复制版本。切口通道64被设置在各相邻的一对产品芯片60、62之间。切口通道64具有与产品芯片60的边界65和与产品芯片62的边界67。分别与切口通道64类似的其它的切口通道被设置在相邻的一对产品芯片25之间。在将各个产品芯片25分割成相应的多个裸片的过程中，切口通道被用作切割道。
具体而言，并且，继续参照图8，切口通道64作为产品芯片60、62之间的无效空间被保留，使得可在不损伤产品芯片60、62的情况下分割产品芯片60、62。可以使用切割锯或激光装置以沿各切口通道64切割或划切器件基板10和最终操作基板56，并由此在物理上将产品芯片60、62分成离散的裸片。
可通过与形成布线34和接合焊盘36相同的处理步骤在切口通道64中形成测试焊盘66。测试焊盘66可与内置于切口通道64中的测试集成电路结构耦合。与接合焊盘36类似并在平整化之前，测试焊盘66突出于层间电介质层32的顶面31之上。测试焊盘66的顶面69可以以与层间电介质层32的顶面31之上的接合焊盘36相同的高度h突出于层间电介质层32的顶面31之上。
绝缘体层40、42也沉积于切口通道64中并填充与测试焊盘66相邻的开放空间并覆盖测试焊盘66。当绝缘体层40、42通过CMP处理被平坦化和平滑化以形成复合绝缘体层44时，绝缘体层44(图7)的顶面46还跨切口通道64横向延伸。可在与边界65、67相邻的位置上在绝缘体层44中形成划线通道。由此，绝缘体层40、42的沉积和随后的CMP处理可跨包含产品裸片之间的切口通道的器件基板10的直径提供全局的平整化。
参考附图9，用类似的附图标记表示与图2类似的特征，并且根据替代性的实施例，反掩模层70可在绝缘体层42的顶面41上形成并且通过常规的光刻处理被图案化。反掩模层70可包含通过旋转涂敷处理施加并然后在软烘焙处理中被加热以去除过量的溶剂并促进部分凝固的放射敏感抗蚀剂。在光刻处理中，抗蚀剂通过使用光掩模被曝光以进行放射成像，在曝光之后被烘焙，并被显影以限定用作反掩模层70的抗蚀剂材料的残留区域。
在图案化之后，反掩模层70包含延伸到绝缘体层42的深度的孔径或开口72。开口72用作基本上与绝缘体层40、42的覆盖接合焊盘36的部分的位置一致的窗口。开口72可在尺寸上比接合焊盘36的表面积稍小，以确保随后的蚀刻处理将在接合焊盘36上停止。反掩模层70覆盖并保护绝缘体层40、42的残留。
使用诸如RIE处理的蚀刻处理以在通过反掩模层70中的开口72露出的表面区域上至少部分地去除绝缘体层40、42的电介质材料。在代表性的实施例中，绝缘体层40、42的整个厚度被去除。作为替代方案，去除的厚度可小于绝缘体层40、42的整个厚度，使得电介质材料的减薄区域覆盖接合焊盘36。在反掩模层70被去除之后，可利用清洁处理以去除残留的掩模材料。
使用反掩模层70可通过在本地减小相对较高特征的高度来改善CMP处理的表面均匀性。例如，接合焊盘36和绝缘体层40、42的特征高度可以为接合焊盘36的高度h的至少两倍。作为数值例，接合焊盘36可具有4μm高度，绝缘体层40可具有4μm高度，绝缘体层42可具有1μm高度，这提供9μm的特征高度。在通过使用反掩模层70蚀刻之后，必须在接合焊盘36上被去除的电介质材料的体积被减少，这降低了用于实现图3的结构的CMP处理的要求。
处理在上述的图3的制造阶段中继续以生成图7～8所示的接合结构。
参考图10，用类似的附图标记表示与图3类似的特征，并且根据替代性实施例，可在复合绝缘体层44的平坦化的顶面46上形成层80，并且，在代表性的实施例中，该层80处于与顶面46的直接接触关系中。层80应是保形的，使得在施加层80之后保持顶面46的平整性。
层80可包含蚀刻选择性与下层的绝缘体层44的电介质材料不同、且在成分上与被组合为形成绝缘体层44的绝缘体层40、42的电介质材料中的至少一种不同的电介质材料。在一个实施例中，层80可包含通过使用CVD或其它的适当的沉积处理沉积的氮化硅(Si3N4)，并且，绝缘体层40、42可包含二氧化硅。当接合焊盘36开放(图4)时，可通过针对绝缘体层44、80的不同材料选择不同的蚀刻化学品，在多个蚀刻步骤中进行蚀刻处理。
处理在上述的图4的制造阶段中继续，以生成与图7和图8类似并在最终的结构中添加层80的接合结构。
参考图11，其中用类似的附图标记表示与图1和图5类似的特征，并且，根据替代性实施例，可在形成布线层24的导体填充通孔38和层间电介质层32之后中断BEOL处理。层间电介质层32的顶面31和导体填充通孔38的顶面39通过与上述的平整化处理类似的CMP处理(图4)被平整化，以形成绝缘体层44的顶面46。在具有多个布线层的互连结构中，可在制造任何任意的布线层之后中断BEOL处理以执行晶片接合处理。
临时操作基板52通过粘接剂层50与以上在图5的上下文中描述的层间电介质层32的顶面31粘接接合，并且，处理如图6和图7所述的那样继续。在埋入绝缘体层16的表面54与最终操作基板56的表面58接合且临时操作基板52和粘接剂层50被去除之后，可如以上在图1的上下文中描述的那样形成布线层24。
通过平整化与器件基板10的埋入绝缘体层16的(与最终操作基板56的表面58的接合处理所涉及的)表面54相对的层间电介质层32的顶面31来获得接合完整性的改善。平整化的顶面31可与器件基板10的埋入绝缘体层16的(与最终操作基板56的表面58的接合处理所涉及的)表面54区分，但是是与表面54相对的表面。在向最终操作基板56转移之前，平整化的顶面31以可去除的方式与临时操作基板52耦合。
图12表示例如用于半导体IC逻辑设计、仿真、测试、布局和制造中的示例性设计流程100的框图。设计流程100包含用于处理设计结构或器件以生成以上描述的并在图5～7和图9～11中表示的设计结构和/或器件的、在逻辑上或在功能上相当的表示的处理、机器和/或机构。由设计流程100处理和/或生成的设计结构可在机器可读传送或存储介质上被编码以包括当在数据处理系统上被执行或被处理时生成硬件部件、电路、器件或系统的逻辑、结构、机械或其它功能等效表示的数据和/或指令。机器包含但不限于用于诸如设计、制造或仿真电路、部件、器件或系统的IC设计处理中的任何机器。例如，机器可包含：光刻机、用于生成掩模的机器和/或设备(例如，e束书写器)、用于仿真设计结构的计算机或设备、用于制造或测试过程中的任何装置或用于将设计结构的在功能上相当的表示编程到任何介质中的任何机器(例如，用于将可编程门阵列编程的机器)。
设计流程100可根据被设计的表示类型而改变。例如，用于构建专用IC(ASIC)的设计流程100可与用于设计标准部件的设计流程100或用于将设计实例化为可编程阵列(例如为可编程门阵列(PGA)或由Inc.或Inc.提供的现场可编程门阵列)的设计流程100不同。
图12示出包含优选通过设计处理104处理的输入设计结构102的多个这种设计结构。设计结构102可以是通过设计处理104生成和处理以生成硬件装置的在逻辑上相当的功能表示的逻辑仿真设计结构。设计结构102可以进一步地或者替代性地包含当通过设计处理104被处理时生成硬件器件的物理结构的功能表示的数据和/或程序指令。不管是否代表功能和/或结构设计特征，都可通过使用诸如通过核开发人员/设计人员实现的电子计算机辅助设计(ECAD)来生成设计结构102。当在机器可读数据的传送、门阵列或存储介质上被编码时，设计结构102可通过设计处理104内的一个或更多个硬件和/或软件模块被访问和处理以仿真或者在功能上表示诸如图5～7和图9～11所示的那些的电子部件、电路、电子或逻辑模块、装置、器件或系统。因而，设计结构102可包含文件或其它数据结构，包括人和/或机器可读源代码、编译结构和当通过设计或仿真数据处理系统被处理时在功能上仿真或代表电路或硬件逻辑设计的其它层级的计算机可执行代码结构。这种数据结构可包含与诸如Verilog和VHDL的低级HDL设计语言和/或诸如C或C++的高级设计语言相符合并且/或者兼容的硬件描述语言(HDL)设计实体或其它数据结构。
设计处理104优选使用和加入用于综合、翻译或处理图5～7和图9～11所示的部件、电路、器件或逻辑结构的设计/仿真功能等同物的硬件和/或软件模块，以生成可包含诸如设计结构102的设计结构的网单106。网单106可包含例如表示描述与集成电路设计中的其它元件和电路的连接的布线、离散部件、逻辑门、控制电路、I/O器件、模型等的列表的编译后或处理后的数据结构。可通过使用迭代处理来综合网单106，在该迭代处理中，网单106根据用于器件的设计规范和参数被重新综合一次或更多次。与这里描述的其它设计结构类型一样，网单106可被记录于机器可读数据存储介质上或者被编程到可编程门阵列中。介质可以是诸如磁或光盘驱动器、可编程门阵列、压缩快擦写或其它快擦写存储器的非易失性存储介质。另外，或者在替代方案中，介质可以是数据分组可通过因特网或其它适当联网手段在其上传送和中间存储的系统或高速缓存存储器、缓冲器空间或者电学或光学传导器件和材料。
设计处理104可包含用于处理包含网单106的各种输入数据结构类型的硬件和软件模块。对于给定的制造技术(例如，不同的技术节点32nm、45nm、84nm等)，这种数据结构类型可驻留于例如库元件108内，并包含一组的共用元件、电路和器件，包括模型、布局和符号表示。数据结构类型还可包含设计规范110、表征数据112、验证数据114、设计规则116以及可包含输入测试图案、输出测试结果和其它测试信息的测试数据文件118。设计处理104还可包含例如诸如应力分析、热分析、机械事件仿真、和用于诸如铸造、成型和裸片加压形成等操作的处理仿真的标准机械设计处理。机械设计领域技术人员可以想到在不背离本发明的范围和精神的情况下的用于设计处理104中的可能的机械设计工具和应用的范围。设计处理104还可包含用于执行诸如定时分析、验证、设计规则检查、位置和路线操作等的标准电路设计处理的模块。
设计处理104使用并加入诸如HDL编译器和仿真模型构建工具的逻辑和物理设计工具以与示出的支持数据结构中的一些或全部一起并连同任何附加的机械设计或数据(如果适用的话)来处理设计结构102，以生成第二设计结构120。设计结构120以用于交换机械装置和结构的数据的数据格式(例如，存储于IGES、DXF、Parasolid XT、JT、DRG中的信息或用于存储或呈现这种机械设计结构的任何其它适当的格式)驻留于存储介质或可编程门阵列上。与设计结构102类似，设计结构120优选包含驻留于传送或数据存储介质上并且当通过ECAD系统被处理时生成图5～7和图9～11所示的本发明的一个或多个实施例的逻辑上或者功能上的等同形式的一个或更多个文件、数据结构或其它计算机编码数据或指令。在一个实施例中，设计结构120可包含在功能上仿真图5～7和图9～11所示的器件的编译后的可执行HDL仿真模型。
设计结构120还可使用用于交换集成电路的布局数据的数据格式和/或符号数据格式(例如，以GDSII(GDS2)、GL1、OASIS、映射文件或用于存储这种设计数据结构的任何其它适当的格式来存储的信息)。设计结构120可包含诸如例如符号数据、映射文件、测试数据文件、设计内容文件、制造数据、布局参数、布线、金属层级、通孔、形状、用于通过制造线路由的数据和制造商或其它设计人员/开发人员制造以上描述并在图5～7和图9～11中显示的器件或结构所需要的任何其它数据的信息。设计结构120然后可前进到阶段122，例如，在阶段122中，设计结构120前进到流片，被发布到制造、被发布到掩模室，被发送到另一设计室，被送回顾客等。
上述的方法被用于集成电路芯片的制造。可由制造商以原始晶片形式(即，具有多个未封装芯片的单个晶片)作为裸片，或者以封装形式分发得到的集成电路芯片。在后一种情况下，芯片被安装于单芯片封装(诸如塑料载体，具有固定于母板或其它高级载体上的引线)或多芯片封装(诸如具有表面互连和埋入互连中的任一者或两者的陶瓷载体)中。在任何情况下，芯片然后作为(a)诸如母板的中间产品或(b)最终产品的一部分与其它的芯片、离散电路元件和/或其它信号处理器件集成。最终产品可以是包含集成电路芯片的任何产品，涵盖从玩具和其它低端应用到具有显示器、键盘或其它输入装置和中央处理器的先进计算机产品。
这里，为了建立基准框架，作为例子而不是限制来参照诸如“垂直”、“水平”等的术语。这里使用的术语“水平”被定义为与半导体基板的常规面平行的面，与其实际的三维空间取向无关。术语“垂直”指的是与刚刚限定的水平垂直的方向。术语“横向”指的是水平面内的维度。
应当理解，当元件被描述为与另一元件“连接”或“耦合”时，它可直接与另一元件连接或耦合，或者可存在一个或更多个居间的元件。相反，当元件被描述为与另一元件“直接连接”或“直接耦合”时，不存在居间的元件。当元件被描述为与另一元件“间接连接”或“间接耦合”时，存在至少一个居间的元件。
虽然通过各种实施例的描述示出了本发明并且相当详细地描述了这些实施例，但申请人不是要将所附的权利要求限于或以任何形式局限于这种细节。对于本领域技术人员来说，其它的优点和修改将是十分明显的。因此，本发明在其更宽的方面上不限于显示和描述的特定的细节、代表性的装置和方法以及说明性的例子。

Claims (20)

1.一种涉及具有第一表面和与第一表面相对的第二表面的器件基板的基板接合方法，该方法包括：
利用器件基板的第一表面形成至少一个产品芯片的器件结构；
形成用于所述至少一个产品芯片的器件结构的互连结构的第一布线层；
将第一布线层平整化；
响应于将第一布线层平整化，将临时操作晶片可去除地接合到第一布线层；和
响应于将临时操作晶片可去除地接合到第一布线层，将器件基板的第二表面接合到最终操作基板，
其中，互连结构包含具有顶面的层间电介质层，第一布线层包含突出于层间电介质层的顶面之上的第一导电特征和第二导电特征，并且，第一导电特征和第二导电特征通过间隙被分开，并且
将第一布线层平整化还包括：用包含第一电介质材料的第一绝缘体层填充第一导电特征和第二导电特征之间的间隙，
所述方法还包括：
在第一绝缘体层上沉积包含第二电介质材料的第二绝缘体层，
其中，第一绝缘体层和第二绝缘体层各自包含第一导电特征上的第一部分和间隙上的第二部分，第一部分以第一高度突出于层间电介质层的顶面之上，并且，第二部分以第二高度突出于层间电介质层的顶面之上，
所述方法还包括：
抛光第一绝缘体层和第二绝缘体层以减小第一高度与第二高度之间的差值，
并且所述方法还包括：
在抛光第一绝缘体层和第二绝缘体层之前，在第二绝缘体层上沉积反掩模层；
在反掩模层中形成与第一导电特征上的第一和第二绝缘体层的第一部分对准的开口；和
通过蚀刻处理至少部分地去除通过所述开口露出的第二绝缘体层的第一部分。
2.根据权利要求1的方法，其中，在抛光之后，第一绝缘体层的第一电介质材料覆盖第一导电特征的顶面和第二导电特征的顶面，并且，第二绝缘体层的第二电介质材料覆盖至少部分填充间隙的第一绝缘体层的第一电介质材料。
3.根据权利要求1的方法，还包括：
在抛光第一绝缘体层和第二绝缘体层之后，在第一绝缘体层和第二绝缘体层的抛光后的表面上沉积包含第三电介质材料的第三绝缘体层，
其中，第三电介质材料在成分上与第一电介质材料和第二电介质材料中的至少一个不同。
4.根据权利要求1的方法，其中，通过蚀刻处理至少部分地去除通过所述开口露出的第一绝缘体层的第一部分。
5.根据权利要求1的方法，其中，通过所述开口露出的第一绝缘体层完全被去除。
6.根据权利要求1的方法，其中，填充间隙的第一电介质材料没有空隙，并且，用包含第一电介质材料的第一绝缘体层填充第一导电特征和第二导电特征之间的间隙包括：
通过高密度等离子体化学气相沉积(HDPCVD)处理来沉积二氧化硅作为第一电介质材料。
7.根据权利要求1的方法，其中，利用器件基板的第一表面来形成第一产品芯片和第二产品芯片的器件结构，第一产品芯片通过切口通道与第二产品芯片分开，并且，当互连结构的第一布线层被平整化时，切口通道被平整化。
8.根据权利要求1的方法，其中，当形成第一布线层时，第一布线层被平整化。
9.根据权利要求8的方法，还包括：
响应于将器件基板的第二表面接合到最终操作基板，在第一布线层上形成互连结构的第二布线层。
10.根据权利要求1的方法，其中，器件基板包含块体基板、器件层、和分开器件层与块体基板的埋入绝缘体层，并且所述方法还包括：
从器件基板去除块体基板以露出埋入绝缘体层，并由此限定埋入绝缘体层上的第二表面，该第二表面随后被接合到最终操作基板。
11.根据权利要求10的方法，还包括：
响应于将器件基板的第二表面接合到最终操作基板，从平整化后的第一布线层去除临时操作晶片。
12.一种接合基板组件，包括：
包含第一表面和与第一表面相对的第二表面的器件基板；
接合到器件基板的第二表面的最终操作基板；
具有在器件基板的第一表面上的器件结构的至少一个产品芯片；
用于器件结构的互连结构，所述互连结构包含第一布线层和在第一布线层与所述器件基板的第一表面之间的第二布线层，所述互连结构的第二布线层包含具有顶面的层间电介质层，所述第一布线层包含突出于顶面之上的第一导电特征以及突出于顶面之上的第二导电特征，第二导电特征通过间隙与第一导电特征分开，并且，第一导电特征和第二导电特征均具有相对于顶面测量的高度；和
在所述层间电介质层的顶面上的填充间隙的至少一个绝缘体层，所述至少一个绝缘体层具有平坦化顶面和相对于顶面测量的厚度，该厚度大于第一导电特征和第二导电特征的高度，
其中，所述互连结构的第一布线层是顶部布线层，并且所述互连结构的第一导电特征是接合焊盘。
13.根据权利要求12的接合基板组件，其中，第一电介质材料和第二电介质材料包含二氧化硅。
14.根据权利要求12的接合基板组件，其中，所述至少一个绝缘体层包含没有空隙的电介质材料。
15.根据权利要求12的接合基板组件，还包括：
可去除地接合到所述至少一个绝缘体层的临时操作晶片。
16.根据权利要求12的接合基板组件，还包括：
包含在成分上与所述至少一个绝缘体层的电介质材料不同的电介质材料的层，该层直接接触所述至少一个绝缘体层的顶面并具有均匀厚度。
17.根据权利要求12的接合基板组件，其中，第一导电特征和第二导电特征中的至少一个被设置在所述至少一个绝缘体层的一部分与层间电介质层的顶面之间。
18.根据权利要求12的接合基板组件，其中，器件基板包含各自沿横向向器件基板的周边延伸的器件层和埋入绝缘体层，并且，器件基板的第二表面是包含埋入绝缘体层的表面。
19.根据权利要求12的接合基板组件，其中，最终操作基板包含蓝宝石，并且，器件基板的第二表面是绝缘体层。
20.根据权利要求12的接合基板组件，其中，所述至少一个绝缘体层包括包含第一电介质材料的第一绝缘体层和包含第二电介质材料的第二绝缘体层，第一绝缘体层填充间隙，并且，第一导电特征和第二导电特征中的至少一个被设置在第一电介质材料的一部分与层间电介质层的顶面之间。
CN201280053476.0A 2011-10-31 2012-08-03 用于基板接合的平坦化基板表面 Active CN104054171B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/285,443 2011-10-31
US13/285,443 US8778737B2 (en) 2011-10-31 2011-10-31 Flattened substrate surface for substrate bonding
PCT/US2012/049414 WO2013066455A2 (en) 2011-10-31 2012-08-03 Flattened substrate surface for substrate bonding

Publications (2)

Publication Number Publication Date
CN104054171A CN104054171A (zh) 2014-09-17
CN104054171B true CN104054171B (zh) 2017-11-07

Family

ID=48171554

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280053476.0A Active CN104054171B (zh) 2011-10-31 2012-08-03 用于基板接合的平坦化基板表面

Country Status (5)

Country Link
US (2) US8778737B2 (zh)
CN (1) CN104054171B (zh)
DE (1) DE112012004106B4 (zh)
GB (1) GB2509683B (zh)
WO (1) WO2013066455A2 (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130193489A1 (en) * 2012-01-30 2013-08-01 Globalfoundries Inc. Integrated circuits including copper local interconnects and methods for the manufacture thereof
US8907488B2 (en) * 2012-12-28 2014-12-09 Broadcom Corporation Microbump and sacrificial pad pattern
US9263511B2 (en) * 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9691686B2 (en) 2014-05-28 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor device
US10043769B2 (en) 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US9679772B2 (en) 2015-10-15 2017-06-13 International Business Machines Corporation Method for handling thin brittle films
US10050102B2 (en) * 2016-01-15 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
DE102017127920A1 (de) 2017-01-26 2018-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Erhöhte Durchkontaktierung für Anschlüsse auf unterschiedlichen Ebenen
US10297494B2 (en) 2017-01-26 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Raised via for terminal connections on different planes
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US10535636B2 (en) * 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US10515874B2 (en) 2017-11-30 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10622302B2 (en) 2018-02-14 2020-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Via for semiconductor device connection and methods of forming the same
DE102018126130B4 (de) 2018-06-08 2023-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und -verfahren
US11158775B2 (en) 2018-06-08 2021-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10992100B2 (en) 2018-07-06 2021-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US20200194459A1 (en) * 2018-12-18 2020-06-18 Vanguard International Semiconductor Corporation Semiconductor devices and methods for fabricating the same
US11308257B1 (en) 2020-12-15 2022-04-19 International Business Machines Corporation Stacked via rivets in chip hotspots
FR3126542A1 (fr) * 2021-08-27 2023-03-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de fabrication d'un circuit électronique pour auto-assemblage à un autre circuit électronique

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1387237A (zh) * 2001-05-22 2002-12-25 华邦电子股份有限公司 薄膜沉积与平坦化工艺
US6864585B2 (en) * 2000-03-22 2005-03-08 Ziptronix, Inc. Three dimensional device integration method and integrated device
CN101431058A (zh) * 2007-11-09 2009-05-13 株式会社瑞萨科技 半导体器件及其制造方法
CN101577245A (zh) * 2008-05-05 2009-11-11 中芯国际集成电路制造(北京)有限公司 层间介质层化学机械研磨方法
CN102024754A (zh) * 2009-09-17 2011-04-20 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5820770A (en) 1992-07-21 1998-10-13 Seagate Technology, Inc. Thin film magnetic head including vias formed in alumina layer and process for making the same
US7470142B2 (en) 2004-06-21 2008-12-30 Sang-Yun Lee Wafer bonding method
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6406636B1 (en) 1999-06-02 2002-06-18 Megasense, Inc. Methods for wafer to wafer bonding using microstructures
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US20030089950A1 (en) 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates
US6616854B2 (en) 2001-12-17 2003-09-09 Motorola, Inc. Method of bonding and transferring a material to form a semiconductor device
US20040126993A1 (en) 2002-12-30 2004-07-01 Chan Kevin K. Low temperature fusion bonding with high surface energy using a wet chemical treatment
US6911375B2 (en) 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
TWI261316B (en) 2005-12-28 2006-09-01 Ind Tech Res Inst Wafer bonding method
US7659182B2 (en) 2006-05-23 2010-02-09 Vladimir Vaganov Method of wafer-to-wafer bonding
US20080124895A1 (en) 2006-06-23 2008-05-29 Shih-Shou Lo Wafer bonding method
US8119500B2 (en) 2007-04-25 2012-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer bonding
KR100893182B1 (ko) 2007-06-01 2009-04-15 주식회사 엘트린 웨이퍼 세정방법
US7786535B2 (en) * 2008-01-11 2010-08-31 International Business Machines Corporation Design structures for high-voltage integrated circuits
JP5496598B2 (ja) 2008-10-31 2014-05-21 信越化学工業株式会社 シリコン薄膜転写絶縁性ウェーハの製造方法
FR2938702B1 (fr) 2008-11-19 2011-03-04 Soitec Silicon On Insulator Preparation de surface d'un substrat saphir pour la realisation d'heterostructures
FR2938975B1 (fr) 2008-11-24 2010-12-31 Soitec Silicon On Insulator Procede de realisation d'une heterostructure de type silicium sur saphir
CN105097712A (zh) 2009-07-15 2015-11-25 斯兰纳半导体美国股份有限公司 具有背侧散热的绝缘体上半导体

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6864585B2 (en) * 2000-03-22 2005-03-08 Ziptronix, Inc. Three dimensional device integration method and integrated device
CN1387237A (zh) * 2001-05-22 2002-12-25 华邦电子股份有限公司 薄膜沉积与平坦化工艺
CN101431058A (zh) * 2007-11-09 2009-05-13 株式会社瑞萨科技 半导体器件及其制造方法
CN101577245A (zh) * 2008-05-05 2009-11-11 中芯国际集成电路制造(北京)有限公司 层间介质层化学机械研磨方法
CN102024754A (zh) * 2009-09-17 2011-04-20 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法

Also Published As

Publication number Publication date
US20130105981A1 (en) 2013-05-02
WO2013066455A2 (en) 2013-05-10
CN104054171A (zh) 2014-09-17
GB201408711D0 (en) 2014-07-02
DE112012004106B4 (de) 2018-06-14
WO2013066455A3 (en) 2014-05-08
GB2509683A (en) 2014-07-09
US9355936B2 (en) 2016-05-31
US20140209908A1 (en) 2014-07-31
US8778737B2 (en) 2014-07-15
DE112012004106T5 (de) 2014-07-10
GB2509683B (en) 2015-07-29

Similar Documents

Publication Publication Date Title
CN104054171B (zh) 用于基板接合的平坦化基板表面
US11004770B2 (en) Phase changing on-chip thermal heat sink
TWI763341B (zh) 半導體裝置及半導體裝置的製造方法
CN110720143B (zh) 具有处理器和nand闪存的键合半导体器件及其形成方法
TWI351727B (en) Device and method for fabricating double-sided soi
CN112510031A (zh) 具有处理器和nand闪存的键合半导体器件及其形成方法
CN110770898A (zh) 具有处理器和动态随机存取存储器的键合半导体器件及其形成方法
US8946049B2 (en) Replacement gate structures and methods of manufacturing
US20210202495A1 (en) Bonded semiconductor devices having processor and static random-access memory and methods for forming the same
US8765595B2 (en) Thick on-chip high-performance wiring structures
JP2001237370A (ja) 多層３次元高密度半導体素子及び形成方法
US11646223B2 (en) Metal lead, semiconductor device and methods of fabricating the same
CN111106133B (zh) 用于具有多个半导体器件层的半导体结构的系统和方法
JP2003110108A (ja) 半導体装置の製造方法及びその構造
TW202211457A (zh) 半導體元件及用於製造半導體元件的方法
JP2001053252A (ja) 半導体装置およびその製造方法
KR20060077653A (ko) 적층형 반도체 소자 및 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171123

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171123

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right