CN1040056C - 输入缓冲器 - Google Patents

输入缓冲器 Download PDF

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CN1040056C
CN1040056C CN93119655A CN93119655A CN1040056C CN 1040056 C CN1040056 C CN 1040056C CN 93119655 A CN93119655 A CN 93119655A CN 93119655 A CN93119655 A CN 93119655A CN 1040056 C CN1040056 C CN 1040056C
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pmos transistor
electrode
grid
mos transistor
voltage
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CN1086360A (zh
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韩圣禛
郭忠根
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

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  • General Engineering & Computer Science (AREA)
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  • Logic Circuits (AREA)
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Abstract

本发明的输入缓冲器包括一个使用一上拉晶体管和一下拉晶体管以缓冲输入信号的缓冲装置和一个连接在用于缓冲装置中的上拉晶体管与下拉晶体管之间用于接收启动信号以防止输出高电平电压因电源电压变动而起伏的补偿器。因此能够防止由电源电压变动所引起的高逻辑电平输出电压的起伏。

Description

输入缓冲器
本发明涉及一种半导体装置，较确切地说是一种半导体装置的输入缓冲器。
在常规半导体装置中，由于其输入缓冲器会产生正比于输入电源电压增量的“高电平”输出电压，因而半导体装置表现出不稳定的性能。
图1示出了一种常规半导体装置的输入缓冲器。参照图1，输入缓冲器包含一个PMOS晶体管1(其源极接电源电压而栅极接启动信号EN)、一个PMOS晶体管2(其源极接PMOS晶体管1的漏极而栅极接输入信号IN)、一个NMOS晶体管3(其漏板接PMOS晶体管2的漏极、栅极接输入信号IN而源极接地)以及一个NMOS晶体管4(其漏极接NMOS晶体管3的漏极、源板接地而栅极接启动信号EN)。
前面提到的常规输入缓冲器的运行如下面所述。若启动信号EN处于“高”位，则NMOS晶体管4接通，从而产生一个“低”逻辑电平的输出信号(OUT)。若启动信号EN处于“低”位，则NMOS晶体管4关断而PMOS晶体管1接通，PMOS管2的源极因此升至“高”逻辑位。此时，若输入信号IN处于“高”位，则输出信号为“低”位；反之，若输入信号处于“低”位，则输出信号为“高”位。当启动信号EN和输入信号IN都低时，电源电压的起伏会经由PMOS晶体管1和2传输到输出端，从而引起输出信号起伏。因此，常规输入缓冲器有如下的弊端，从而引起输出信号起伏。因此，常规输入缓冲器有如下的弊端，即高电平的输出电压正比于电源电压的变动而起伏，当电源电压增加时更是如此。
本发明的目的在于提供一种半导体装置的输入缓冲器，这种输入缓冲器的输出电压在高电平条件下甚至在电源电压升高时也不增高。
为实现此目的，本发明提供了一种半导体存储装置的输入缓冲器，它包含一个源极与电源相连而栅极与启动信号相连的PMOS晶体管、一个源极与上述PMOS晶体管的漏极相连而栅极与一输入信号节点相连的PMOS晶体管、一个其漏-源通路连接于输出信号和接地电压之间而其栅极与上述输入信号相连的NMOS晶体管，以及一个漏-源通路连接于上述输出信号和接地电压之间而栅极与上述启动信号相连的NMOS晶体管，其特征是还包含一个连接在上述第二个PMOS晶体管的漏极和上述输出信号节点之间的PMOS晶体管；一个漏-源通路连接于上述PMOS晶体管的栅极和接地电压之间而栅极与电源电压相连的NMOS晶体管；一个源极与电源相连而栅极与上述启动信号相连的PMOS晶体管，以及连接在该PMOS晶体管和该NMOS晶体管的漏极之间的多个PMOS晶体管，这些PMOS晶体管各自的栅极和漏极彼此相连。
根据本发明结合附图的下列详细描述，能更清楚地了解本发明的各种目的、特征、情况和优点。在这些附图中，
图1示出了常规半导体装置的输入缓冲器；
图2示出了本发明的半导体装置的输入缓冲器；
图3是图2中PMOS晶体管14的电源电压变动时的栅极电压变化特性图；
图4是常规输入缓冲器和本发明输入缓冲器的高电平输出电压特性对比图。
本发明的半导体装置输入缓冲器根据附图描述如下。
图2示出了本发明的半导体装置输入缓冲器。参照图2，输入缓冲器包含一个PMOS晶体管5(其源极接电源电压Vcc而栅极接收启动信号EN)、一个PMOS晶体管6(其源极接PMOS晶体管5的漏极而栅极接收输入信号IN)、一个NMOS晶体管7(其栅极接收输入信号IN而源极接地)、一个NMOS晶体管8(其栅极接收启动信号EN、源极接地而漏极接至NMOS晶体管7的漏极)、一个PMOS晶体管9(其源极接电源电压Vcc而栅极接收启动信号EN)、一个PMOS晶体管10(其源极接PMOS晶体管9的漏极而栅极和漏极彼此相接)、一个PMOS晶体管11(其源极接PMOS晶体管10的漏极而栅极和漏极彼此相接)、一个PMOS晶体管12(其源极接PMOS晶体管11的漏极而栅极和漏极彼此相接)、一个NMOS晶体管13(其栅极接电源电压Vcc、漏极接PMOS晶体管12的漏极而源极接地)以及一个PMOS晶体管14(其源极接PMOS晶体管6的漏极、栅极接PMOS晶体管12的漏极而漏板接NMOS晶体管7的漏极)。
在输入缓冲器的上述结构中，PMOS晶体管9、10、11、12和14以及NMOS晶体管13是用于防止电源电压变化引起“高电平”态输出电压的起伏。
当电源电压Vcc变得大于PMOS晶体管9-12的阈值电压总和时，PMOS晶体管14的栅极电压与电源电压的关系可由下式表示： VG 14 = r 13 r 13 + Rtp Vcc
其中，VG14是PMOS晶体管14的栅极电压，r13是NMOS晶体管13的沟道电阻，Rtp是PMOS晶体管9～12的总沟道电阻。可以理解，Rtp仅在电源电压Vcc超过设定值时才对抑制输出信号电平作出贡献。
上述输入缓冲器结构的运行如下所述。
首先，由于NMOS晶体管13总是处于“接通”状态，PMOS晶体管14也就保持“接通”。若启动信号EN变低，则PMOS晶体管5接通而NMOS晶体管8关断。因此，输入信号IN被PMOS晶体管6和NMOS晶体管7反相并缓冲，作为输出信号而被输出。当电源电压Vcc在设定电平以下时，晶体管13上的导通压降低得可以忽略不计，Vcc大多降落在晶体管9～12的沟道电阻上。但当Vcc大于晶体管9～12的阈值电压总和时，PMOS晶体管9接通，NMOS晶体管13的漏极处出现电位增加，使PMOS晶体管14的栅极电压线性上升。因此，PMOS晶体管14的沟道开通情况成为可控，以便输出信号的“高电平”态可被调节。
换言之，根据本发明，输入缓冲器是在启动信号的控制下被启动的，而且，在输入缓冲器的上拉晶体管和下拉晶体管之间接有一个其沟道开通情况可根据电源电压来调节的晶体管。
图3是图2中PMOS晶体管14栅极电压随电源电压变化的曲线。图3的横坐标表示电源电压(Vcc)而纵坐标表示PMOS晶体管14的栅极电压。当电源电压由3V增加到7V时，PMOS晶体管14的栅极电压由零V线性上升到2V。PMOS晶体管14(图2)被调整到只在低于设定电压时才运行(导通)而在高于设定电压时关断，以便输出信号的“高电平”条件能够被控制。
图4示出了高电平输出电压相对于电源电压的特性曲线。此外横坐标表示电源电压(0V到7V)而纵坐标表示输出“高电平”电压条件(0V到3V)。参考字母A表示常规输入缓冲器的特性，其中高电平输出正比于电源电压的增加而线性增加。参考字母B表示本发明的输入缓冲器的特性，其中输出电平在电源电压超过设定值时保持恒定。
可见，本发明的半导体装置输入缓冲器能够在电源电压变动时稳定输出高电平电压的特性。
虽然根据本发明的实施例已详细地描述了本发明，但对本技术领域的技术人员来说，显然可以在不超越所附权利要求规定的构思和范围的条件上实现各种形式上和细节上的改变。

Claims (1)

1.一种输入缓冲器，它具有一个其源极与电源电压相连而栅极与一启动信号相连的PMOS晶体管(5)、一个其源极与上述PMOS晶体管的漏极相连而栅极与一输入信号节点相连的PMOS晶体管(6)、一个其漏-源通路连接于一输出信号节点和一接地电压之间而其栅极与上述输入信号节点相连的NMOS晶体管(7)，以及一个其漏-源通路连接于上述输出信号节点和接地电压之间而其栅极与上述启动信号相连的NMOS晶体管(8)，其特征在于所述输入缓冲器还包括：
一个连接在PMOS晶体管(6)的漏极和上述输出信号节点之间的PMOS晶体管(14)；
一个其漏-源通路连接于上述PMOS晶体管(14)的栅极和一接地电压之间而栅极与电源电压相连的NMOS晶体管(13)；
一个其源极与电源电压相连而其栅极与上述启动信号相连的PMOS晶体管(9)；以及
连接在上述PMOS晶体管(9)和NMOS晶体管(13)的漏极之间的多个PMOS晶体管(10、11、12)，它们各自的栅极和漏极彼此相连。
CN93119655A 1992-10-29 1993-10-29 输入缓冲器 Expired - Fee Related CN1040056C (zh)

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KR1019920019989A KR940010674B1 (ko) 1992-10-29 1992-10-29 입력 버퍼
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JP (2) JPH06225319A (zh)
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DE (1) DE4336720B4 (zh)
GB (1) GB2272120B (zh)
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DE4336720A1 (de) 1994-05-05
GB2272120A8 (en) 1997-01-14
JP3476514B2 (ja) 2003-12-10
GB2272120A (en) 1994-05-04
JPH06225319A (ja) 1994-08-12
KR940010529A (ko) 1994-05-26
US5408191A (en) 1995-04-18
TW257905B (zh) 1995-09-21
GB2272120B (en) 1997-03-12
DE4336720B4 (de) 2005-07-21
CN1086360A (zh) 1994-05-04
KR940010674B1 (ko) 1994-10-24
JPH06209253A (ja) 1994-07-26
GB9322075D0 (en) 1993-12-15

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