JPS6477318A - Input buffer circuit - Google Patents

Input buffer circuit

Info

Publication number
JPS6477318A
JPS6477318A JP62234349A JP23434987A JPS6477318A JP S6477318 A JPS6477318 A JP S6477318A JP 62234349 A JP62234349 A JP 62234349A JP 23434987 A JP23434987 A JP 23434987A JP S6477318 A JPS6477318 A JP S6477318A
Authority
JP
Japan
Prior art keywords
mos
inverter
changed
initial
impressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62234349A
Other languages
Japanese (ja)
Inventor
Yutaka Shinagawa
Futoshi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP62234349A priority Critical patent/JPS6477318A/en
Publication of JPS6477318A publication Critical patent/JPS6477318A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To improve a margin against noise and to prevent the generation of malfunction by connecting a P-MOS to be biased by a state detecting means consisting of a CMOS inverter or the like in series with an N-MOS of the inverter in a first stage. CONSTITUTION:An input signal Vin is impressed only to the gate terminal of an N-MOS Q1 constituting the initial inverter INV1 and an output voltage V1 of a state detecting inverter INV3 constituted of shorting an input terminal and an output terminal is impressed to the gate terminal of a P-MOS Q1. Even when a power supply voltage VCC is changed, the logical threshold voltage VLT of the initial inverter is approximately fixed. When the threshold voltage VthN of the N-MOS Q2 is changed due to the dispersion of a process, the VthN of the N-MOS Q2 consisting the INV3 is similarly changed. Thereby, the VLT of the initial inverter is approximately fixed.
JP62234349A 1987-09-18 1987-09-18 Input buffer circuit Pending JPS6477318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62234349A JPS6477318A (en) 1987-09-18 1987-09-18 Input buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62234349A JPS6477318A (en) 1987-09-18 1987-09-18 Input buffer circuit

Publications (1)

Publication Number Publication Date
JPS6477318A true JPS6477318A (en) 1989-03-23

Family

ID=16969603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62234349A Pending JPS6477318A (en) 1987-09-18 1987-09-18 Input buffer circuit

Country Status (1)

Country Link
JP (1) JPS6477318A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4336720B4 (en) * 1992-10-29 2005-07-21 Samsung Electronics Co., Ltd., Suwon input buffer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4336720B4 (en) * 1992-10-29 2005-07-21 Samsung Electronics Co., Ltd., Suwon input buffer

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