JPS6439116A - Semiconductor integrated circuit with malfunction preventing circuit - Google Patents

Semiconductor integrated circuit with malfunction preventing circuit

Info

Publication number
JPS6439116A
JPS6439116A JP62195574A JP19557487A JPS6439116A JP S6439116 A JPS6439116 A JP S6439116A JP 62195574 A JP62195574 A JP 62195574A JP 19557487 A JP19557487 A JP 19557487A JP S6439116 A JPS6439116 A JP S6439116A
Authority
JP
Japan
Prior art keywords
outputs
circuit
noises
logic
produced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62195574A
Other languages
Japanese (ja)
Inventor
Toshimasa Usui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62195574A priority Critical patent/JPS6439116A/en
Publication of JPS6439116A publication Critical patent/JPS6439116A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a semiconductor integrated circuit having the stable circuit action by setting a noise eliminating circuit between an input buffer and an internal logic to eliminate the noise produced by the simultaneous action of output buffers. CONSTITUTION:In case many outputs act at one time, the input signal is latched continuously as long as the noises are produced so that these noises are never transmitted to an internal logic 22 to avoid malfunctions. An action signal is applied to a pulse generator 24 from the logic 22 when plural outputs work at one time. The generator 24 produces a pulse having the time width larger than the period of noises which emerge at the outputs of the output buffers 20 by simultaneous the simultaneous action of outputs. The produced pulse is used as a control signal 5 of a latch circuit 25 to latch the signal to be transmitted to the logic 22 for a fixed time. As a result, no noise is transmitted to the logic 22 even though the noises are produced at the outputs of the circuits 20. Thus a semiconductor integrated circuit has no malfunction at all.
JP62195574A 1987-08-04 1987-08-04 Semiconductor integrated circuit with malfunction preventing circuit Pending JPS6439116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62195574A JPS6439116A (en) 1987-08-04 1987-08-04 Semiconductor integrated circuit with malfunction preventing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62195574A JPS6439116A (en) 1987-08-04 1987-08-04 Semiconductor integrated circuit with malfunction preventing circuit

Publications (1)

Publication Number Publication Date
JPS6439116A true JPS6439116A (en) 1989-02-09

Family

ID=16343393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62195574A Pending JPS6439116A (en) 1987-08-04 1987-08-04 Semiconductor integrated circuit with malfunction preventing circuit

Country Status (1)

Country Link
JP (1) JPS6439116A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009118107A (en) * 2007-11-06 2009-05-28 Oki Semiconductor Co Ltd Noise rejection circuit
US10293481B1 (en) 2016-12-14 2019-05-21 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Relative deflection detector

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6153826A (en) * 1984-08-24 1986-03-17 Hitachi Ltd Semiconductor integrated circuit device
JPS61133724A (en) * 1984-12-03 1986-06-21 Nec Corp Semiconductor integrated circuit
JPS6298912A (en) * 1985-10-25 1987-05-08 Toshiba Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6153826A (en) * 1984-08-24 1986-03-17 Hitachi Ltd Semiconductor integrated circuit device
JPS61133724A (en) * 1984-12-03 1986-06-21 Nec Corp Semiconductor integrated circuit
JPS6298912A (en) * 1985-10-25 1987-05-08 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009118107A (en) * 2007-11-06 2009-05-28 Oki Semiconductor Co Ltd Noise rejection circuit
US10293481B1 (en) 2016-12-14 2019-05-21 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Relative deflection detector

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