JPS6153826A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stabilize the logical threshold value of an internal circuit and eliminate the probability of malfunction by providing an IC circuit with the group line of a final output circuit and the ground line of an internal logical circuit, etc., independently of each other. CONSTITUTION:In the IC circuit, a ground bus G1 constitutes the common current circuit of an input buffer part 20 and an internal logical circuit 21 and is connected to the ground potential GND through a terminal T1. A ground bus G2 forms the current return circuit of only an output buffer part 22 and connected to the ground GND through a terminal T2, and the buses G1 and G2 are disconnected from each other. Even if a large sink current flows to the side of the output buffer part 22, or even if the current is switched at a high speed, the resulting transient effect extends only to the ground bus G2 and the ground bus G1 is not affected. Therefore, the potential of the bus G1 is held stable regardless of the state of the bus G2 and threshold values of the buffer part 20 and circuit part 21 are held stably, so that malfunction due to variation in threshold value is prevented.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a semiconductor integrated circuit device (IC).

[Background technology]

For example, as shown in "Nikkei Electronics Magazine" dated June 21, 1982, published by Nikkei McGraw-Hill, paragraphs 112 to 208, the development of large integrated LSIs using complementary insulated gate field effect transistors (6MO8) is progressing. It's okay. For example, as shown in Section 119 of the same magazine, large-scale gate arrays are being actively developed in the field of gate arrays.

The present inventors have also conducted studies to increase the integration and speed of gate arrays, and have developed the following technology. In other words, the internal logic circuit is configured using 6MO8 with low power consumption, and an input/output interface part K of the IC and an input/output buffer with a level conversion function are provided, and a part of this input/output buffer is also required. Accordingly, by configuring the gate array with bipolar transistors, it is possible to obtain a gate array that is compatible with, for example, TTL (transistor transistor logic), has low power consumption, and has high speed.

Based on the above technology, the present inventors further investigated ways to increase the scale and speed of the gate array, and proceeded with the development of a highly miniaturized gate array with a minimum processing dimension of 2 μm or less for wiring. In the course of its development, the inventors discovered that the following problems occurred.

In other words, in the internal logic circuit composed of CMO8, a current of only about several tens of microamperes flows, but in an output buffer whose output transistors are bipolar transistors that drive the external load, in one output buffer, For example, it was found that a suction current or extrusion current of 8 mA should flow. If the current return path of each logic circuit formed in the IC is connected to a common ground line, the multiple output buffers can be operated in the same mode (pushing out or sinking current) at the same time, or can be switched at the same time. When a large current flows instantaneously through the common ground line, the potential of the common ground line may rise or fluctuate due to the influence of this current and the inductance component of the ground line. I found out something.

This causes the logic threshold value of the input buffer section or internal circuit section to fluctuate, and in the worst case, the logic threshold value may deviate from the specified standard range and cause malfunction. The above-mentioned problem, which the inventor has clarified will occur, becomes more pronounced as the number of output buffer sofas increases due to larger scale, and as the output buffer switches at higher speed. Become.

[Purpose of the invention]

The purpose of the present invention is to produce highly microfabricated, high-speed, large-scale bipolar 0MO
In 8 mixed type (Bi-0MO8 type) logic semiconductor integrated circuit devices, etc., it is possible to prevent transient effects that occur when driving an external load at high speed from affecting the logic threshold of the input side or internal circuit. The present invention provides a semiconductor integrated circuit device in which the logic threshold value is stabilized and the risk of malfunction is eliminated.

[Summary of the Invention] The above and other objects and novel features of this invention will become clear from the description of this specification and the accompanying drawings. A brief explanation is as follows.

In other words, in a semiconductor integrated circuit device, at least the ground line for the final output circuit and the ground line for internal logic circuits etc. are provided independently, thereby stabilizing the logic threshold of the input side or internal circuits and preventing malfunctions. The objective is to reliably suppress the occurrence of

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a semiconductor integrated circuit device according to the present invention.

The semiconductor integrated circuit device shown in the figure is one of semi-custom ICs, and is generally called a gate array. As shown in the figure, it is formed of an input buffer section 20, an internal circuit section 21, and an output buffer section 22. In the same figure, IN] ~ INn are input terminals, 0UT1 ~
OUTm indicates an output terminal. Further, VCC indicates a common power supply, and GND indicates a common ground potential.

Furthermore, the graph shown in FIG. 1 shows the lower logic level of each part, and the
h22 each indicates a logical threshold.

Mata, ViHi 20~ViH922, V6H20~V
6H22 indicates the logic level of "H" (high potential) of the input and output signals, respectively. ViL20~ViL 22.
VoL 20 to VoL 22 indicate the logic level of "L" (low potential) of the input and output signals, respectively.

Here, in the embodiment shown in FIG. 1, a first . A second two ground busbars G+-02 are provided.

These two ground buses G, , G are separated from each other in circuit terms. And the first ground bus G
, forms a common current return path for the input buffer section 20 and the internal circuit section 21, and connects to the external ground potential GN via the terminal T.
It is designed to be connected to D. Further, the second ground bus G2 forms a current return path for only the output buffer section 22, and is connected to an external common ground potential GND via a terminal T2. In other words, the ground bus G1 on the input side and the ground bus G2 on the output side are separated from each other in circuit terms.

With the above configuration, the output buffer section 2
Even if a large sink or source current flows in G2, and even if the sink or source current is switched at high speed, the resulting transient effects will remain at the second ground bus G2 and will not be connected to the first ground bus G2. It does not reach bus line G1. The potential of the first ground bus G2 is kept stable regardless of the state of the second ground bus G2. This makes it possible to maintain each logic threshold value of the input buffer section 20 and the internal circuit section 21 stably. As a result, malfunctions due to fluctuations in the logical threshold value can be reliably prevented.

FIG. 2 shows an example of a circuit configuration within the semiconductor integrated circuit device IC shown in FIG.

In the figure, input buffer section 20 includes a large number of input buffer circuits 201 to 20n. In addition, the output buffer section 2
2 includes, but is not particularly limited to, a large number of tri-state output buffer circuits 221 to 22m, for example. The state of each output buffer circuit 221 to 22m is controlled by an enable signal EN generated by the internal circuit section 21 or externally. The internal circuit section 21 includes a large number of logic circuits 211
~211.

FIG. 3 shows, for example, a logic circuit 211 in the internal circuit section 21.
An example is shown below. The logic circuit shown in the figure is a two-person NAND
P-channel MO3FETMp5. Mp
6 and N channel MO8FETMn 5. Mn 6
It is made up of.

FIG. 4 shows another example of the logic circuit 211 described above.

The logic circuit 211 shown in the figure is a Bi-CMO8 type logic circuit, and includes an MO8 field effect transistor Mp7. M
p 8. Mn7. It is composed of Mn 8 and bipolar transistors Q,,Q,.

FIG. 5 illustrates in detail another example of each part of the input buffer circuit 211 and the output buffer circuit 221. Input buffer circuit 211 is n-channel MO8FE
A CMOS inverter consisting of TMnl, Mpl, and Mp2, and a MOSFET.

Mp2. It is composed of a CMOS inverter made of Mn3. Cs indicates the load of the manual buffer circuit 201. The output buffer circuit is C-MO81 with increased W/L (gate width/channel length)! Field effect transistor Mp4. It is composed of Mn4. Cx indicates an external capacitive load.

FIG. 6 shows yet another example of the input buffer circuit 201. The input buffer circuit 201 shown in the figure is a Bi-CM
It is configured as O8 type, MO8FETMp9. It consists of a CMOS inverter made of Mn9, a P-MO8FET Mp10, bipolar transistors Q3 to Q0, etc.

FIG. 7 shows another example of the output buffer circuit 221 and its surroundings. The output buffer circuit 221 shown in the figure is also configured as a Bi-CMO8 type. Only the final current return path from the bipolar transistors Q4+, Q, and 42, which are the final output transistors in the output buffer, is connected to the second ground bus G21c, and all other current return paths are connected to the first ground bus G21c. ,It is connected to the.

FIG. 8 shows another embodiment of the invention. The feature of this embodiment is that in the output buffer 22, not only the connection line G but also the power supply line cc2 are connected to the ground line G for the input cover sofa and the internal logic circuit. It is provided separately and independently from C□.

With this configuration, it is possible to almost completely prevent the influence of large current in the output sofa from reaching the input buffer and internal logic circuit.

FIG. 9 shows yet another embodiment of the invention.

The feature of this embodiment is that the final output transistor Q41
+ Power line V at G42. C2t and the ground line G2 are the ground line Gl l for the input buffer and internal logic circuit. It is provided separately and independently from the OL.

FIG. 10 is a plan view showing the above-described semiconductor integrated circuit device including a lead frame. As shown in the figure, a chip 100 is fixed to the center of a tab supported by a lead frame LFI via silver paste (not shown). Bonding pads are arranged around the chip and connected to external connection leads T, , T, etc. via lead wires (L+-Lt, etc.). In the figure, triangular symbols with diagonal lines placed around the chip indicate input buffers, and triangular symbols without diagonal lines indicate output buffers.

As shown in the figure, a first . The second two ground buses G, , G, are each
Pad P,,P,-bonding wire C,l! 2-lead L, , L2 - terminal T, , T,.

It is designed to be connected to an external common ground potential GND via a.

FIG. 11 shows an example of the external appearance of the above-described semiconductor integrated circuit device. As shown in the figure, this semiconductor integrated circuit device IC has two ground terminals T, , T2. In addition,
300 is a resin sealed package.

FIG. 12 shows an example of use of the above-described semiconductor integrated circuit device IC.

As shown in the figure, the above-described semiconductor integrated circuit device IC has a Bi-CMO8 type configuration, so that TTL type logic circuits 401 to 4 On, 501 to 505, 600
It is also compatible at the logical level.

Here, for example, the following three methods are possible for the above-mentioned two ground buses G, , G.

(1) As shown in FIGS. 13 and 14, the ground bus lines G, , G in the semiconductor substrate 100 are separated from each other, but the terminal pads P1. Bonding wire 11 and lead L.

and terminal T1 in common.

(2) As shown in FIGS. 15 and 16, the semiconductor substrate 10
0 terminal pads P, , P2 and bonding wire z
1 and 12 are made separate from each other, and only the lead L and terminal T are made common.

(3) As shown in FIGS. 17 and 18, terminal pads p, l Pt , bonding wires, etc.

72, leads L, , L2, and terminals T, , T.

Separate everything.

In addition, Fig. 13.15.17 shows the planar state, and Fig. 14.1
Figure 6.18 shows the appearance of each.

Of the three above, (2) is better than (1).
(3) gives better results than (2).

Furthermore, the configuration (3) above, as shown in FIG. 19,
Terminal pad PI*P2, bonding wire 11, -
lt, lead L, , L, and terminal T,.

By providing T, at two locations each, the potential of each ground bus G, G2 can be further stabilized. This makes the effect of preventing malfunctions even more reliable.

Furthermore, as shown in FIG. 20, configuration 1 of FIG.
In addition, N1 source bus VCCI that supplies power ■Co
``Like the ground buses G, , G, CC2 is also provided with the input side and the output side separated from each other in circuit terms, thereby making the above effect even more reliable.

〔effect〕

(1) By separating the input side ground bus and the output side ground bus in the semiconductor integrated circuit device from each other in terms of the circuit, it is possible to prevent transient effects occurring on the output side from adversely affecting the input side. This has the effect of stabilizing the logic threshold of the input side or internal circuits and reliably suppressing the occurrence of malfunctions.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the embodiments of this specification, the output buffer is of a tri-state type, but the output buffer is not limited to this, and may be of a totem pole type, an open collector type, or the like.

FIG. 21 shows yet another example of the output buffer.
Ru. This output buffer is a MOSFET,! :It is an output buffer that effectively combines bipolar transistors, has a small number of elements, and can operate at extremely high speed. The figure shows the final output transistor Q45.

Power line ■ connected to Q4e. C21 ground line G and power supply line connected to MOSFET ■c
An example is shown in which o1 and ground line G are provided separately and independently.

Also, it is not necessary to provide an input buffer (,
The present invention is also effective in ICs in which external input signals are directly input to internal logic circuits.

[Application field]

In the above description, the invention made by the present inventor was mainly applied to a Bi-Ch40S type semiconductor integrated circuit device, which is the background field of application, but the invention is not limited thereto. -MO8
It can also be applied to type semiconductor integrated circuit devices or bipolar type conductor integrated circuit devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a circuit diagram showing an example of the circuit configuration within the semiconductor integrated circuit device shown in FIG. 1, and FIG. 3 is the same as that shown in FIG. 4 is a diagram showing an example of a logic circuit constituting an internal circuit section in the semiconductor integrated circuit device shown in FIG.
FIG. 5 is a circuit diagram showing another example of the logic circuit constituting the internal circuit section in the semiconductor integrated circuit device shown in FIG. FIG. 6 is a circuit diagram showing another example of the input buffer circuit; FIG. 7 is a circuit diagram showing another embodiment of the present invention; FIG. 8 is a circuit diagram showing another embodiment of the present invention. FIG. 9 is a circuit diagram showing still another embodiment of the present invention; FIG. 10 is a diagram showing a configuration example of a terminal portion of a semiconductor integrated circuit device according to an embodiment of the present invention; FIG. The figure is the first
FIG. 12 is a circuit diagram showing an example of the use of the semiconductor integrated circuit device shown in FIG. 2. FIG. 13 is a perspective view showing an example of the external appearance of the semiconductor integrated circuit device shown in FIG. FIG. 14 is an external view showing the package state of the IC shown in FIG. 13, FIG. 15 is a diagram showing another embodiment of the ground bus, and FIG. 16 is a diagram showing another embodiment. Figure 15 is an external view showing the IC packaged state; Figure 17 is a diagram showing yet another embodiment of the ground bus; Figure 18 is the IC packaged state shown in Figure 17. Figure 19 is a diagram showing yet another embodiment of the ground bus, Figure 20 is an example of the ground bus and power bus, and Figure 21 is the output. FIG. 7 is a circuit diagram showing still another configuration example of the buffer. IC...Semiconductor integrated circuit device, 100...Semiconductor substrate, 20...Input buffer section, 21...Internal circuit section, 22...Output sofa section, 201-20n...Input buffer circuit, 221~22m...output sofa circuit, T,...ground terminal, T2...ground terminal, G,
1. First ground bus, G2...Second ground bus, ■1.
...Power bus, v2...Power bus, GND...Common ground potential, Fig. 20 Fig. 21 Ql Chi 2

Claims (1)

[Claims] 1. A logic circuit formed in the same semiconductor substrate and an output circuit that outputs an output signal based on the output of the logic circuit, and at least a first reference potential connected to the logic circuit. A semiconductor integrated circuit device, characterized in that a line and a first reference potential line connected to the output circuit are provided independently. 2. A semiconductor integrated circuit device, wherein the final output stage of the output circuit is comprised of bipolar transistors.