CN103975424A - 用于非平面晶体管的夹层电介质 - Google Patents

用于非平面晶体管的夹层电介质 Download PDF

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CN103975424A
CN103975424A CN201180075347.7A CN201180075347A CN103975424A CN 103975424 A CN103975424 A CN 103975424A CN 201180075347 A CN201180075347 A CN 201180075347A CN 103975424 A CN103975424 A CN 103975424A
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material layer
dielectric material
interlayer dielectric
gate
planar transistor
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CN103975424B (zh
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S·普拉丹
J·卢斯
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Intel Corp
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Abstract

本发明涉及在非平面晶体管中形成第一级夹层电介质材料层，其可以借助旋涂技术，之后借助氧化和退火来形成。第一级夹层电介质材料层可以基本上没有空隙，并可以对非平面晶体管的源极/漏极区施加拉伸应变。

Description

用于非平面晶体管的夹层电介质
技术领域
本说明的实施例总体上涉及微电子器件制造的领域，更具体地，涉及在非平面晶体管中的第一级夹层电介质(interlayer dielectric)材料层的制造。
附图说明
在说明书的结束部分中特别指出并明确要求了本公开内容的主题。依据以下的说明和所附权利要求书并结合附图，本公开内容的在前的及其他特征会变得更充分地显而易见。应当理解，附图仅示出了根据本公开内容的几个实施例，因此不应认为限制本公开内容的范围。通过使用附图，将借助额外的特征和细节来描述本公开内容，以便更易于确定本公开内容的优点，在附图中：
图1是根据本说明的实施例的非平面晶体管的透视图。
图2示出了形成在微电子衬底中或上的非平面晶体管鳍片的侧视截面图。
图3示出了根据本说明的实施例的在图2的非平面晶体管鳍片之上沉积的牺牲材料的侧视截面图。
图4示出了根据本说明的实施例的沟槽的侧视截面图，所述沟槽形成在所沉积的牺牲材料中以露出图3的非平面晶体管鳍片的一部分。
图5示出了根据本说明的实施例的在图4的沟槽中形成的牺牲栅极的侧视截面图。
图6示出了根据本说明的实施例的在去除了图5的牺牲材料之后的牺牲栅极的侧视截面图。
图7示出了根据本说明的实施例的在图6的牺牲栅极和微电子衬底之上沉积的保形电介质层的侧视截面图。
图8示出了根据本说明的实施例的从图7的保形电介质层形成的栅极隔离物的侧视截面图。
图9示出了根据本说明的实施例的在图8的栅极隔离物的任一侧上的非平面晶体管鳍片中所形成的源极区和漏极区的侧视截面图。
图10示出了根据本说明的实施例的在图9的结构上所形成的粘附层的侧视截面图。
图11示出了根据本说明的实施例的在图10的栅极隔离物、牺牲栅极、非平面晶体管鳍片和微电子衬底之上沉积的第一夹层电介质材料层的侧视截面图。
图12示出了根据本说明的实施例的被氧化和退火的图11的第一夹层电介质材料层的侧视截面图。
图13示出了根据本说明的实施例的图12的结构的侧视截面图，其中，一部分第一夹层电介质材料层由图13的氧化和退火来硬化。
图14示出了根据本说明的实施例的在使得第一夹层电介质材料层平面化以露出牺牲栅极的顶表面之后的图13的结构的侧视截面图。
图15示出了根据本说明的实施例的在去除了牺牲栅极以形成栅极沟槽之后的图14的结构的侧视截面图。
图16示出了根据本说明的实施例的在栅极隔离物之间邻近非平面晶体管鳍片形成栅极电介质之后的图15的结构的侧视截面图。
图17示出了根据本说明的实施例的在图16的栅极沟槽中沉积的导电栅极材料的侧视截面图。
图18示出了根据本说明的实施例的在去除了过量导电栅极材料以形成非平面晶体管栅极之后的图17的结构的侧视截面图。
图19示出了根据本说明的实施例的在蚀刻掉一部分非平面晶体管栅极以形成凹陷的非平面晶体管栅极之后的图18的结构的侧视截面图。
图20示出了根据本说明的实施例的在将覆盖(capping)电介质材料沉积到由凹陷的非平面晶体管鳍片的形成所导致的凹陷中之后的图19的结构的侧视截面图。
图21示出了根据本说明的实施例的在去除了过量覆盖电介质材料以在非平面晶体管栅极上形成覆盖结构之后的图20的结构的侧视截面图。
图22示出了根据本说明的实施例的在图21的第一夹层电介质材料层、栅极隔离物和牺牲栅极顶表面之上沉积的第二夹层电介质材料层的侧视截面图。
图23示出了根据本说明的实施例的在图22的第二电介质材料上构图的蚀刻掩模的侧视截面图。
图24示出了根据本说明的实施例的通过图23的第一和第二电介质材料层形成的接触开口部的侧视截面图。
图25示出了根据本说明的实施例的在去除了蚀刻掩模之后的图24的结构的侧视截面图。
图26示出了根据本说明的实施例的在图25的接触开口部中沉积的导电接触材料的侧视截面图。
图27示出了根据本说明的实施例的在去除了过量导电接触材料以形成源极/漏极触点之后的图25的结构的侧视截面图。
图28示出了根据本说明的一个实现方式的计算设备。
具体实施方式
在以下的详细说明中参考了附图，其以例示的方式示出了其中可以实施所要求保护的主题的特定实施例。充分详细地说明了这些实施例，以使得本领域技术人员能够实施主题。应当理解，尽管不同，但多个实施例不一定是相互排斥的。例如，在不脱离所要求主题的精神和范围的情况下，本文中结合一个实施例所述的特定特征、结构或特性可以在其他实施例中实施。在本说明书中对“一个实施例”、“实施例”的提及表示结合该实施例说明的特定的特征、结构或特性包括在本发明所包含的至少一个实现方式中。因而，短语“一个实施例”或“在实施例中”的使用不一定指代同一实施例。另外，应当理解，在不脱离所要求的主题的精神和范围的情况下，可以修改每一个公开的实施例内的各个元件的位置或布置。因此，以下的详细说明不应认为是限制意义上的，主题的范围仅由适当理解的所附权利要求书连同所附权利要求书所给与的全部等同形式来限定。在附图中，相似的标记在几个附图通篇中指代相同或相似的元件或功能，本文所示的元件相互不一定按照比例，而是可以放大或缩小单个元件以便更易于理解本说明的内容中的元件。
在诸如三栅极晶体管和FinFET之类的非平面晶体管的制造中，非平面半导体基体可以用于形成能够以极小的栅极长度(例如小于约30nm)完全耗尽的晶体管。这些晶体管基体通常是鳍片形的，因而通称为晶体管“鳍片”。例如，在三栅极晶体管中，晶体管鳍片具有形成于本体半导体衬底或绝缘体上硅结构衬底上的顶表面和两个相对侧壁。栅极电介质可以形成于半导体基体的顶表面和侧壁上，栅极电极可以形成于半导体基体的顶表面上的栅极电介质之上，并邻近半导体基体的侧壁上的栅极电介质。因而由于栅极电介质和栅极电极邻近半导体基体的三个表面，就形成了三个分离的沟道和栅极。由于形成了三个分离的沟道，在导通晶体管时，可以完全耗尽半导体基体。关于finFET晶体管，栅极材料和电极仅接触半导体基体的侧壁，以形成两个分离的沟道(而不是三栅极晶体管中的三个沟道)。
本说明的实施例涉及在非平面晶体管内形成第一级夹层电介质材料层的，其可以借助旋涂技术之后借助氧化和退火来形成。第一级夹层电介质材料层可以基本上没有空隙，并可以对非平面晶体管的源极/漏极区施加拉伸应变。
图1是非平面晶体管100的透视图，包括形成于至少一个晶体管鳍片上的至少一个栅极，所述晶体管鳍片形成于微电子衬底102上。在本公开内容的一个实施例中，微电子衬底102可以是单晶硅衬底。微电子衬底102也可以是其他类型的衬底，例如绝缘体上硅(“SOI”)、锗、砷化镓、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、锑化镓等，其任何一个都可以与硅组合。
显示为三栅晶体管的每一个非平面晶体管可以包括至少一个非平面晶体管鳍片112。非平面晶体管鳍片112可以具有顶表面和横向相对的侧壁对，分别为侧壁116与相对的侧壁118。
如图1进一步示出的，可以在非平面晶体管鳍片112之上形成至少一个非平面晶体管栅极122。通过在非平面晶体管鳍片顶表面114上或邻近它，并在非平面晶体管鳍片侧壁116和相对的非平面晶体管鳍片侧壁118上或邻近它们形成栅极电介质层124来制造非平面晶体管栅极122。可以在栅极电介质层124上或邻近它形成栅极电极126。在本公开内容的一个实施例中，非平面晶体管鳍片112可以在与非平面晶体管栅极122基本上垂直的方向上延伸。
可以由任何公知的栅极电介质材料来形成栅极电介质层124，所述栅极电介质材料包括但不限于，二氧化硅(SiO2)、氮氧化硅(SiOxNy)、氮化硅(Si3N4)和高k电介质材料，所述高k电介质材料例如是，二氧化铪、硅酸铪、氧化镧、铝酸镧、氧化锆、硅酸锆、氧化钽、二氧化钛、钛酸锶钡、钛酸钡、钛酸锶、氧化钇、氧化铝、钽酸钪铅、和铌酸锌铅。可以借助公知的技术来形成栅极电介质层124，例如，如同本领域技术人员应当理解的，通过保形沉积栅极电极材料，随后以公知的光刻法和蚀刻技术来对栅极电极材料进行构图。
栅极电极126可以由任何适合的栅极电极材料来形成。在本公开内容的实施例中，栅极电极126可以由包括但不限于以下的材料形成：多晶硅、钨、钌、钯、铂、钴、镍、铪、锆、钛、钽、铝、碳化钛、一碳化锆、碳化钽、碳化铪、碳化铝、其他金属碳化物、金属氮化物、和金属氧化物。栅极电极126可以借助公知的技术来形成，例如，如同本领域技术人员应当理解的，通过均厚沉积栅极电极材料，随后以公知的光刻法和蚀刻技术来对栅极电极材料进行构图。
可以在栅极电极126的相对侧上的非平面晶体管鳍片112中形成源极区和漏极区(图1中未示出)。在一个实施例中，可以通过掺杂非平面晶体管鳍片112来形成源极和漏极区，如同本领域技术人员应当理解的。在另一个实施例中，源极和漏极区的形成可以通过去除部分非平面晶体管鳍片112，并以适当的材料代替这些部分，以形成源极和漏极区，如同本领域技术人员应当理解的。在又一个实施例中，可以通过在鳍片112上外延生长掺杂的或未掺杂的应变层来形成源极和漏极区。
图2－26示出了制造非平面晶体管的一个实施例的侧视截面图，其中，图2－5是沿图1的箭头A-A和B-B的视图，图6－15是沿图1的箭头A-A的视图，图16－26是沿图1的箭头C-C的视图。
如图2所示的，可以通过借助本领域中公知的任何技术来蚀刻微电子衬底102或在微电子衬底102上形成非平面晶体管鳍片112而形成非平面晶体管鳍片112。如图3所示的，可以在非平面晶体管鳍片112上沉积牺牲材料132，如图3中所示的，可以在牺牲材料132中形成沟槽134，以露出一部分非平面晶体管鳍片112，如图4中所示的。牺牲材料132可以是本领域中公知的任何适当的材料，可以通过本领域中公知的任何技术来形成沟槽134，所述公知技术包括但不限于光刻掩模和蚀刻。
如图5所示的，可以在沟槽134中形成牺牲栅极136(参见图4)。牺牲栅极136可以是诸如多晶硅材料等之类的任何适当的材料，并可以借助本领域中公知的任何技术沉积在沟槽134中(参见图4)，所述公知技术包括但不限于化学气相沉积(“CVD”)和物理气相沉积(“PVD”)。
如图6所示的，可以借助本领域中公知的任何技术来去除图5的牺牲材料132以露出牺牲栅极136，所述公知技术例如是选择性地蚀刻牺牲材料132。如图7所示的，保形电介质层142可以沉积在牺牲栅极136和微电子衬底102上。保形电介质层142可以是任何适当的材料，所述材料包括但不限于氮化硅(Si3N4)和碳化硅(SiC)，并可以借助任何适当的技术来形成，所述技术包括但不限于原子层沉积(“ALD”)。
如图8所示的，可以蚀刻图7的保形电介质层142，例如借助使用适当蚀刻剂的定向蚀刻，以在牺牲栅极136的侧壁146上形成一对栅极隔离物144，同时基本上去除邻近微电子衬底102和牺牲栅极136的顶表面148的保形电介质层142。应当理解，在栅极隔离物114的形成过程中，可以在非平面晶体管鳍片112的侧壁116和118上(参见图1)同时形成鳍片隔离物(未示出)。
如图9所示的，可以在栅极隔离物144的任一侧上形成源极区150a和漏极区150b。在一个实施例中，可以借助N型或P型离子掺杂剂的注入在非平面晶体管鳍片112中源极区150a和漏极区150b。如本领域技术人员应当理解的，掺杂剂注入是为了改变其导电性和电子特性，将杂质引入半导体材料的过程。这通常借助统称为“掺杂剂”的P型离子或N型离子的离子注入来实现。在另一个实施例中，可以借助诸如蚀刻的本领域中公知的任何技术去除部分非平面晶体管鳍片112，并可以形成源极区150a和漏极区150b以代替被去除的部分。在再另一个实施例中，可以通过在鳍片112上外延生长掺杂或未掺杂的应变层来形成源极和漏极区。在下文中将源极区150a和漏极区统称为“源极/漏极区150”。如本领域技术人员应当理解的，将具有P型源极和漏极的晶体管称为“PMOS”或“p沟道金属氧化物半导体”晶体管，将具N型源极和漏极的晶体管称为“NMOS”或“n沟道金属氧化物半导体”晶体管。
如图10所示的，诸如二氧化硅的粘附衬垫(adhesion liner)152可以保形沉积在栅极隔离物144、牺牲栅极顶表面148、非平面晶体管鳍片112和微电子衬底102上。粘附衬垫152可以在随后形成的夹层电介质材料层于图9的结构(即栅极隔离物144、牺牲栅极顶表面148、非平面晶体管鳍片112和微电子衬底102)之间提供足够的粘附力。
如图11所示的，可以借助旋涂技术在粘附衬垫152上形成第一夹层电介质材料层154，这可以用于将基本上均匀的薄膜涂覆在衬底上。在本说明的一个实施例中，可以在粘附衬垫152上沉积过量的夹层电介质材料。随后可以通常以高速旋转微电子衬底102，借助离心力将夹层电介质材料散布到微电子衬底102上；从而形成第一夹层电介质材料层154。旋涂技术可以具有相对间隔尺寸(pitch size)的能力等级，同时即使在高纵横比的情况下仍实现了有效的间隙填充(例如很少或基本上没有空隙形成)。
如图12所示的，第一夹层电介质材料层154可以被氧化随后进行退火(将氧化和退火步骤示为箭头156)。尽管以共同的箭头156在单一附图中示出了氧化和退火步骤，但这仅仅是为了举例说明中的简明。应当理解，氧化和退火步骤可以由一个或多个处理步骤间隔开。
在一个实施例中，在约93％蒸汽气氛中、以约410摄氏度在垂直扩散炉中执行氧化约2小时。氧化可以将溶剂从第一夹层电介质材料层154中驱除，并可以导致约10％到12％之间的第一夹层电介质材料层154的体积收缩。这个收缩可以施加拉伸应变，已经表明由于沟道迁移率增强而将NMOS三栅极晶体管的驱动电流增大高达约7％，如本领域技术人员应当理解的。在一个实施例中，可以借助氦气(或其他此类惰性气体)气氛在高密度等离子体室中以两个步骤退火来实现退火。第一步骤可以包括在约六(6)分钟的持续时间中将高密度等离子体室中的RF电极，例如顶电极和侧电极，加电到约16kW。第二步骤可以包括将高密度等离子体室RF电极，(例如顶电极和侧电极)加电到约6kW，持续约两(2)分钟的持续时间。
如图13所示的，作为前述氧化和退火步骤的结果，可以硬化第一夹层电介质154的一部分158。硬化的电介质部分158有助于在下游处理期间保护第一夹层电介质154。
如图14所示的，可以使第一夹层电介质层154平面化，以露出牺牲栅极顶表面148。第一电介质材料层154的平面化可以借助本领域中公知的任何技术来实现，包括但不限于，化学机械抛光(CMP)。如图14所示的，在平面化之后可以保留一部分硬化的电介质部158。
如图15所示的，可以去除图14的牺牲栅极以形成栅极沟槽164。可以借助诸如选择性蚀刻的本领域中公知的任何技术去除牺牲栅极136。如图16所示的，可以形成同样在图1中示出的栅极电介质层124，以临界非平面晶体管鳍片112，如前所述的。在前面已经论述了形成栅极电介质124的材料和方法。
如图17所示的，导电栅极材料166可以沉积在栅极沟槽164中，可以去除过量的导电栅极材料166(例如不在图16的栅极沟槽166中的导电栅极材料166)，以形成非平面晶体管栅极电极126(同样参见图1)，如图18所示的。在前面已经论述了形成栅极电极126的材料和方法。可以借助本领域中公知的任何技术来实现去除过量栅极材料166，所述公知技术包括但不限于，化学机械抛光(CMP)、蚀刻等。
如图19所示的，可以去除图18的一部分非平面晶体管栅极电极126，以形成凹陷168和凹陷的非平面晶体管栅极172。可以借助任何公知的技术来完成去除，所述公知技术包括但不限于湿法或干法蚀刻。在一个实施例中，凹陷的形成可以由干法蚀刻和湿法蚀刻的组合所产生。
如图20所示的，可以沉积覆盖电介质材料174以填充图19的凹陷168。覆盖电介质材料174可以是任何适当的材料，包括但不限于氮化硅(Si3N4)和碳化硅(SiC)，并可以借助任何适当的沉积技术来形成。可以平面化覆盖电介质材料174以去除过量的覆盖电介质材料174(例如不在图19的凹陷内的覆盖电介质材料174)，以便在凹陷的非平面晶体管栅极172上和栅极隔离物144之间形成覆盖电介质结构176，如图21所示的。可以借助本领域中公知的任何技术来实现去除过量覆盖电介质材料174，所述公知技术包括但不限于化学机械抛光(CMP)、蚀刻等。
如图22所示的，可以在第一电介质材料层154、栅极隔离物144和覆盖电介质结构176之上沉积第二夹层电介质层178。第二夹层电介质层178可以借助任何公知的沉积技术由任何适当的电介质材料形成，所述电介质材料包括但不限于，二氧化硅(SiO2)、氮氧化硅(SiOxNy)和氮化硅(Si3N4)。如图23所示的，可以例如借助公知的光刻技术，以在第二夹层电介质层178上的至少一个开口部184来构图蚀刻掩模182。
如图24所示的，可以借助蚀刻通过图23的蚀刻掩模开口部184以露出一部分源极/漏极区150来通过第一夹层电介质层154和第二夹层电介质层178形成接触开口部192。此后可以去除图24的蚀刻掩模182，如图25所示的。在一个实施例中，第一夹层电介质层154和第二电介质材料层178与栅极隔离物144和覆盖电介质结构176的电介质材料都不同，以使得第一夹层电介质层154和第二夹层电介质层178的蚀刻对于栅极隔离物144和覆盖电介质结构176有选择性(即蚀刻得更快)。这在本领域中称为自动对准。
如图26所示的，可以将导电接触材料196沉积在图25的接触开口部192中。导电接触材料196可以包括但不限于，多晶硅、钨、钌、钯、铂、钴、镍、铪、锆、钛、钽、铝、碳化钛、一碳化锆、碳化钽、碳化铪、碳化铝、其他金属碳化物、金属氮化物、和金属氧化物。应当理解，在沉积导电接触材料196之前，可以在图25的接触开口部192中保形设置或形成多个粘附层、载体层、硅化物层和/或导电层。
如图27所示的，可以去除图26的过量的导电接触材料196(例如不在图24的接触开口部192内的导电接触材料196)以形成源极/漏极触点198。过量导电接触材料196的去除可以借助本领域中公知的任何技术来实现，公知技术包括但不限于，化学机械抛光(CMP)、蚀刻等。
如前所述，在一个实施例中，第一夹层电介质层154和第二夹层电介质层178与栅极隔离物144和覆盖电介质结构176的电介质材料都不同，以使得第一夹层电介质层154和第二夹层电介质层178的蚀刻对于栅极隔离物144和覆盖电介质结构176是选择性的(即蚀刻得更快)。因而在接触开口部192的形成过程中保护了凹陷的非平面晶体管172。这允许相对大尺寸的源极/漏极触点198的形成，这可以增大晶体管驱动电流性能，且没有在源极/漏极触点198与凹陷的非平面晶体管栅极172之间的短路风险。
图28示出了根据本说明的一个实现方式的计算设备1000。计算设备1000容纳板1002。板1002可以包括多个组件，包括但不限于，处理器1004和至少一个通信芯片1006。处理器1004物理且电耦合到板1002。在一些实现方式中，至少一个通信芯片1006也物理且电耦合到板1002。在进一步的实现方式中，通信芯片1006是处理器1004的一部分。
取决于其应用，计算设备1000可以包括其他组件，其可以与板1002物理地且电性地耦合或不耦合。这些其他组件包括但不限于，易失性存储器(例如，DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、加密处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、相机和大容量储存设备(例如，硬盘驱动器、光盘(CD)、数字多用途盘(DVD)等等)。
通信芯片1006实现了无线通信，用于往来于计算设备1000传送数据。术语“无线”及其派生词可以用于描述可以通过非固态介质借助使用调制电磁辐射传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并非暗示相关设备不包含任何导线，尽管在一些实施例中它们可以不包含。通信芯片1006可以实施多个无线标准或协议中的任意一个，包括但不限于，Wi-Fi(IEEE802.11族)、WiMAX(IEEE802.16族)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物，以及被指定为3G、4G、5G及之后的任何其他无线协议。计算设备1000可以包括多个通信芯片1006。例如，第一通信芯片1006可以专用于近距离无线通信，例如Wi-Fi和蓝牙，第二通信芯片1006可以专用于远距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备1000的处理器1004包括封装在处理器1004内的集成电路晶片。在本说明的一些实现方式中，处理器的集成电路晶片包括一个或多个器件，例如根据本说明的实现方式构成的非平面晶体管。术语“处理器”可以指代任何设备或设备的部分，其处理来自寄存器和/或存储器的电子数据，将该电子数据转变为可以存储在寄存器和/或存储器中的其他电子数据。
通信芯片1006也包括封装在通信芯片1006内的集成电路晶片。根据本说明的另一个实现方式，通信芯片的集成电路晶片包括一个或多个器件，例如根据本说明的实现方式构成的非平面晶体管。
在进一步的实现方式中，容纳在计算设备1000中的另一个组件可以包含集成电路晶片，其包括一个或多个器件，例如根据本说明的实现方式构成的非平面晶体管。
在多个实现方式中，计算设备1000可以是膝上型电脑、上网本电脑、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描器、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数码摄像机。在进一步的实现方式中，计算设备1000可以是处理数据的任何其他电子设备。
应当理解，本说明的主题不必然局限于图1-28所示的特定应用。如本领域技术人员应当理解的，该主题可以应用于其他微电子器件制造应用。
如此详细说明了本发明的实施例，应当理解，由所附权利要求书限定的本发明不受以上说明中阐述的特定细节的限制，在不脱离其精神或范围的情况下，其许多显而易见的变化是可能的。

Claims (20)

1.一种制造微电子晶体管的方法，包括：
形成晶体管栅极，所述晶体管栅极包括邻近衬底的栅极电极和位于所述栅极电极的相对侧上的一对栅极隔离物；
形成源极/漏极区；
邻近所述源极/漏极区并邻近至少一个栅极隔离物形成第一夹层电介质材料层；
氧化所述第一夹层电介质材料层；以及
对所述第一夹层电介质材料层进行退火。
2.根据权利要求1所述的方法，其中，形成所述第一夹层电介质材料层包括：以旋涂技术沉积所述第一夹层电介质材料层。
3.根据权利要求1所述的方法，进一步包括，在形成所述第一夹层电介质材料层之前，邻近所述源极/漏极区并邻近至少一个栅极隔离物形成粘附衬垫。
4.根据权利要求1所述的方法，其中，氧化所述第一夹层电介质材料层包括：在蒸汽气氛中加热所述第一夹层电介质材料层。
5.根据权利要求4所述的方法，其中，在蒸汽气氛中加热所述第一夹层电介质材料层包括：在约93％蒸汽气氛中，将所述第一夹层电介质材料层加热2小时，到约410摄氏度的温度。
6.根据权利要求1所述的方法，其中，对所述第一夹层电介质材料层进行退火包括：在惰性气氛中借助高密度等离子体对所述第一夹层电介质材料层进行退火。
7.根据权利要求1所述的方法，其中，对所述第一夹层电介质材料层进行氧化和退火使所述第一夹层电介质材料层收缩，以对所述源极/漏极区施加拉伸应变。
8.一种方法，包括：
在非平面晶体管鳍片之上形成牺牲非平面晶体管栅极；
在所述牺牲非平面晶体管栅极和所述非平面晶体管鳍片之上沉积电介质材料层；
从所述电介质材料层的邻近所述牺牲非平面晶体管栅极的部分形成非平面晶体管栅极隔离物；
形成源极/漏极区；
去除所述牺牲非平面晶体管栅极，以在所述非平面晶体管栅极隔离物之间形成栅极沟槽并露出所述非平面晶体管鳍片的一部分；
在所述栅极沟槽内邻近所述非平面晶体管鳍片形成栅极电介质；
在所述栅极沟槽内沉积导电栅极材料；
去除所述导电栅极材料的一部分，以在所述非平面晶体管栅极隔离物之间形成凹陷；
在所述凹陷内形成覆盖电介质结构；
在所述源极/漏极区、所述非平面晶体管栅极隔离物和所述覆盖电介质结构之上形成第一夹层电介质材料层；以及
氧化所述第一夹层电介质材料层；以及
对所述第一夹层电介质材料层进行退火。
9.根据权利要求8所述的方法，其中，形成所述第一夹层电介质材料层包括：以旋涂技术沉积所述第一夹层电介质材料层。
10.根据权利要求8所述的方法，进一步包括，在形成所述第一夹层电介质材料层之前，邻近所述源极/漏极区并邻近至少一个栅极隔离物形成粘附衬垫。
11.根据权利要求8所述的方法，其中，氧化所述第一夹层电介质材料层包括：在蒸汽气氛中加热所述第一夹层电介质材料层。
12.根据权利要求11所述的方法，其中，在蒸汽气氛中加热所述第一夹层电介质材料层包括：在约93％蒸汽气氛中，将所述第一夹层电介质材料层加热约2小时，到约410摄氏度的温度。
13.根据权利要求8所述的方法，其中，对所述第一夹层电介质材料层进行退火包括：在惰性气氛中借助高密度等离子体对所述第一夹层电介质材料层进行退火。
14.根据权利要求8所述的方法，进一步包括，平面化所述第一夹层电介质材料层。
15.根据权利要求8所述的方法，进一步包括，通过至少一个电介质材料形成触点，以接触所述源极/漏极区的至少部分。
16.根据权利要求8所述的方法，其中，对所述第一夹层电介质材料层进行氧化和退火使所述第一夹层电介质材料层收缩，以对所述源极/漏极区施加拉伸应变。
17.一种微电子晶体管，包括：
晶体管栅极，所述晶体管栅极包括邻近衬底形成的栅极电极和设置在所述栅极电极相对侧上的一对栅极隔离物；
源极/漏极区，所述源极/漏极区邻近所述晶体管栅极；以及
第一夹层电介质材料层，所述第一夹层电介质材料层邻近所述衬底、邻近所述源极/漏极区并邻近至少一个栅极隔离物而形成，其中，所述第一夹层电介质材料层包括硬化部分，所述硬化部分形成在所述第一夹层电介质材料层的第一表面附近处。
18.根据权利要求17所述的微电子晶体管，其中，所述晶体管栅极是非平面的。
19.根据权利要求17所述的微电子晶体管，其中，所述源极/漏极区是非平面的。
20.根据权利要求17所述的微电子晶体管，进一步包括覆盖电介质结构，所述覆盖电介质结构被设置为邻近所述非平面栅极电极并位于一对栅极隔离物之间。
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