CN103915401A - 封装结构中的细长凸块结构 - Google Patents

封装结构中的细长凸块结构 Download PDF

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Publication number
CN103915401A
CN103915401A CN201310119638.2A CN201310119638A CN103915401A CN 103915401 A CN103915401 A CN 103915401A CN 201310119638 A CN201310119638 A CN 201310119638A CN 103915401 A CN103915401 A CN 103915401A
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Prior art keywords
conductive pole
chip
substrate
measuring along
size
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CN201310119638.2A
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CN103915401B (zh
Inventor
庄曜群
庄其达
曾明鸿
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了封装结构中的细长凸块结构，其中封装结构包括附接至衬底的芯片。芯片包括凸块结构，其包括具有沿着导电柱的长轴测量的长度(L)和沿着导电柱的短轴测量的宽度(W)的导电柱。衬底包括焊盘区域和位于焊盘区域上方的掩模层，其中，掩模层具有露出部分焊盘区域的开口。芯片附接至衬底以在导电柱和焊盘区域之间形成互连件。开口具有沿着长轴测量的第一尺寸(d1)和沿着短轴测量的第二尺寸(d2)。在一个实施例中，L大于d1，而W小于d2。

Description

封装结构中的细长凸块结构
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及封装结构中的细长凸块结构。
背景技术
集成电路芯片包括形成在诸如半导体晶圆的衬底上的半导体器件，并且包括用于为集成电路提供电接口的金属化接触件或附接件、焊盘。接合凸块是集成电路中的互连结构的一部分。凸块为集成电路器件提供接口，可通过其实现器件的电连接。用于提供芯片的内部电路和外部电路(诸如电路板、另一种芯片或晶圆)之间连接的传统技术包括引线接合，其中，引线用于将芯片接触焊盘连接至外部电路，并且还可包括本领域公知的其它技术。被称为倒装芯片技术的新近芯片连接技术使用沉积到芯片接触焊盘上的焊料凸块为集成电路器件提供与外部电路的连接。为了将芯片安装至外部电路，翻转芯片以使其顶面朝下并且其接触焊盘与外部电路上的相配接触焊盘对准。然后，焊料在倒装芯片和支撑外部电路的衬底之间流动以完成互连。所得到的倒装芯片封装比传统的基于载体的系统更小，因为芯片被直接放置在外部电路上，使得互连引线可以更短。结果，大大减小了电感热和电阻热，从而器件的速度更快。
高密度倒装芯片互连件的最近趋势引导中央处理单元(CPU)和图形处理单元(GPU)封装使用圆形或类圆形铜柱凸块。铜柱凸块代替传统焊料凸块是吸引人的，因为它们提供与接合引线间距无关的固定基准距(stand-off)。然而，圆形铜柱凸块具有多种缺点。例如，圆形的铜柱凸块增加了互连结构的有效尺寸，因此限制了用于互连的金属迹线的间距尺寸。结果，当前圆形凸块最终将成为集成电路(IC)工业中缩小器件的瓶颈。圆形铜柱凸块的另一个缺点是由于芯片和封装结构不匹配的热膨胀而在封装电路以及下面的层上产生机械应力。已经注意到，在封装之后，凸块下金属化(UBM)层边缘处的应力非常高，因此所引起的应力导致介电层分层，在具有极低k(ELK)介电层(k值低于3)的电路中尤其严重。因此，封装结构越来越易碎。此外，圆形凸块-焊盘接口处较大的电流密度会引起电迁移和电应力。由电迁移引起的损坏类型的实例包括焊料接头中的微变形以及接合层中的分层。
发明内容
根据本发明的一个方面，提供了一种封装结构，包括：芯片，包括凸块结构，凸块结构包括导电柱，导电柱具有沿着导电柱的长轴测量的长度(L)和沿着导电柱的短轴测量的宽度(W)；以及衬底，包括焊盘区域和位于焊盘区域上方的掩模层，掩模层具有露出部分焊盘区域的开口，其中，芯片附接至衬底以在导电柱和焊盘区域之间形成互连件，其中，开口具有沿着长轴测量的第一尺寸(d1)和沿着短轴测量的第二尺寸(d2)；以及其中，L大于d1，而W小于d2。
优选地，该封装结构进一步包括位于导电柱和焊盘区域之间的焊点区域。
优选地，由阻焊材料层形成掩模层。
优选地，导电柱包括铜或铜合金。
优选地，导电柱的长轴垂直于芯片的边缘。
优选地，导电柱的长轴沿着朝向芯片的中央区域的方向。
优选地，L与d1之间的差值大于20μm。
优选地，W与d2之间的差值大于2μm。
优选地，d1基本等于d2。
根据本发明的另一方面，提供了一种封装结构，包括：芯片，包括凸块结构，凸块结构包括导电柱，导电柱具有沿着导电柱的长轴测量的长度(L)和沿着导电柱的短轴测量的宽度(W)；以及衬底，包括位于衬底上方并具有开口的掩模层、以及填充掩模层的开口并从掩模层的顶面突出的导电区域；其中，芯片附接至衬底以在导电柱和导电区域之间形成互连件，其中，开口具有沿着长轴测量的第一尺寸(d1)和沿着短轴测量的第二尺寸(d2)；以及其中，L大于d1，而W小于d2。
优选地，该封装结构进一步包括位于导电柱和导电区域之间的焊点区域。
优选地，由阻焊材料层形成掩模层。
优选地，导电柱包括铜或铜合金。
优选地，导电柱的长轴垂直于芯片的边缘。
优选地，导电柱的长轴沿着朝向芯片的中央区域的方向。
优选地，L与d1之间的差值大于20μm。
优选地，W与d2之间的差值大于2μm。
优选地，d1基本等于d2。
根据本发明的又一方面，提供了一种形成封装结构的方法，包括：在半导体衬底上形成凸块结构，其中，凸块结构包括导电柱，导电柱具有沿着导电柱的长轴测量的长度(L)和沿着导电柱的短轴测量的宽度(W)；在具有焊盘区域的封装衬底上形成阻焊层，在阻焊层中形成开口，其中，开口具有沿着长轴测量的第一尺寸(d1)和沿着短轴测量的第二尺寸(d2)，L大于d1，而W小于d2；以及将芯片附接至封装衬底以在导电柱和焊盘区域之间形成互连件。
优选地，该方法进一步包括在导电柱和焊盘区域中的至少一个上形成焊料层。
附图说明
图1是根据一个实施例的细长凸块结构的截面图；
图2是根据另一个实施例的可选细长凸块结构的截面图；
图3是根据一个实施例的设置在衬底上的多个细长凸块结构的平面图；
图4是根据一个实施例的图3所示细长凸块结构的导电柱的放大图；
图5是根据一个实施例的部分工件的截面图；
图6是包括附接至图5所示工件的芯片的倒装芯片封装结构的示例性实施例的截面图；
图7是根据一个实施例的图6所示倒装芯片封装结构的掩模开口和导电柱之间的关系的俯视图；
图8是根据一个实施例的部分工件的截面图；
图9是包括附接至图8所示工件的芯片的倒装芯片封装结构的示例性实施例的截面图；以及
图10是根据一个实施例的图9所示倒装芯片封装结构的掩模开口和导电柱之间的关系的俯视图。
具体实施方式
以下详细讨论本发明实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中具体化的可应用发明概念。所讨论的具体实施例仅仅说明实施例的制造和使用的具体方式，但不限制本发明的范围。本文描述的实施例涉及用于半导体器件的细长凸块结构的使用。如以下讨论，公开了为了将一个衬底附接至另一个衬底而利用细长凸块结构的实施例，其中，每个衬底均可以是管芯、晶圆、中介衬底、印刷电路板、封装衬底等，从而允许管芯至管芯、晶圆至管芯、晶圆至晶圆、管芯或晶圆至中介衬底或印刷电路板或者封装衬底等。在各个视图和说明性实施例中，类似参考标号用于表示类似元件。
现在，参考附图来详细描述所示的示例性实施例。只要有可能，附图和说明书中使用的相同的参考标号是指相同或类似的元件。在附图中，为了清楚和方便可以夸大形状和厚度。根据本发明，具体地，该说明书引导元件形成部分装置或者与装置直接组合。应该理解，没有明确示出或描述的元件可具有本领域技术人员公知的多个变形。此外，当层被称为位于另一个层上或“位于”衬底上时，它可以直接位于其它层上或位于衬底上，或者还可能存在中介层。本说明书中参照的“一个(one)实施例”或“一个(a)实施例”意思是至少一个实施例包括与实施例相关的所述具体特征、结构或特性。因此，在本说明书中的不同位置出现的短语“在一个(one)实施例中”或“在一个(a)实施例中”不一定全部是指相同的实施例。此外，在一个或多个实施例中，可以用任意合适的方式组合具体特征、结构或特性。应该理解，以下的附图并未按比例绘制；恰恰相反，这些附图仅用于说明。
图1根据一个实施例的细长凸块结构的截面图。
参照图1，示出了具有形成在衬底10中和/或衬底10上的电路的芯片100的一部分。衬底10可以是半导体集成电路制造中常用的各种半导体衬底中的一种，并且集成电路可形成在其中和/或其上。半导体衬底可具有包括半导体材料的任意结构，包括但不限于体硅、半导体晶圆、绝缘体上硅(SOI)衬底或硅锗衬底。还可以使用包括III族、IV族和/或V族半导体的其它半导体材料。虽然未示出，但应理解衬底10可进一步包括多个隔离部件，诸如浅槽隔离(STI)部件或硅局部氧化(LOCOS)部件。隔离部件可隔离形成在衬底10中和/或衬底10上的各种微电子元件(在图1中由元件12表示)。可形成在衬底10中的微电子元件的类型实例包括但不限于晶体管(诸如金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET/NFET))、电阻器、二极管、电容器、电感器、熔丝和/或其它合适元件。执行各种工艺以形成多个微电子元件，包括但不限于沉积、蚀刻、注入、光刻、退火以及其它合适工艺中的一种或多种。互连微电子元件以形成集成电路器件，集成电路器件可包括逻辑器件、存储器件(例如，SRAM)、RF器件、输入/输出(I/O)器件、系统级芯片(SOC)器件以及其它合适类型的器件中的一种或多种。
衬底10进一步包括位于集成电路上方的互连结构14。互连结构14包括集成电路上方的层间介电层和金属化结构。金属化结构中的层间介电层可包括一种或多种低k介电材料、非掺杂硅玻璃(USG)、氮化硅(SiN)、氮氧化硅(SiON)以及其它常用材料。低k介电材料的介电常数(k值)可以小于约3.9或者小于约2.8。可由铜或铜合金形成金属化结构中的金属线。本领域技术人员能够使用适当工艺来执行形成金属化层，因此省略了形成金属化层的描述。
在顶层层间介电层中或顶层层间介电层上形成并图案化导电焊盘16，其是导电路径的一部分。导电焊盘16包括用于提供电连接的接触凸块，其上可形成促进外部电连接的凸块结构(诸如UBM结构或铜柱凸块)。导电焊盘16可由任意合适的导电材料形成，例如包括铜(Cu)、钨(W)、铝(Al)、AlCu合金、银(Ag)或者类似材料中的一种或多种。在一些实施例中，导电焊盘16可以是区域或再分布线的一端以提供期望的引脚或球布局。如图1所示，在导电焊盘16的上方形成并图案化一个或多个钝化层(诸如钝化层18)。在一个实施例中，在钝化层18中提供开口19，露出下面的部分导电焊盘16。在一个实施例中，开口19的直径大于导电焊盘16的宽度。在一些实施例中，开口19的直径等于或小于导电焊盘16的宽度。在至少一个实施例中，由非有机材料形成钝化层18，诸如非掺杂硅玻璃(USG)、SiN、SiON、氧化硅(SiO)或它们的组合。可通过任意合适的方法(诸如化学汽相沉积(CVD)、物理汽相沉积(PVD)等)形成钝化层18。在其他实施例中，由聚合物层(诸如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等)形成钝化层18，虽然也可以使用其它相对较软通常是有机的介电材料。本领域技术人员应当理解，示出导电焊盘的单层以及钝化层仅仅用于说明的目的。同样地，其它实施例可包括任意数量的导电焊盘和/或钝化层。
图1还示出形成在钝化层18上并通过开口19电连接至导电焊盘16的凸块结构20。根据本文描述的实施例的特征，凸块结构20的形状是细长的而不是圆形。各种形状可用于实现细长凸块结构，包括但不限于矩形、至少一边为弧形或圆形的矩形、两条凸曲边的矩形、卵形、椭圆形或任意其它细长形状。
在一个实施例中，凸块结构20包括凸块下金属化(UBM)层22和导电柱24。在钝化层18的表面以及导电焊盘16的露出部分的上方形成UBM层22。在一些实施例中，UBM层22包括扩散势垒层或胶层，其可包括钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)等并通过PVD或溅射形成。UBM层可进一步包括通过PVD或溅射形成在扩散势垒层上的种子层。可由铜(Cu)或者包括Al、铬(Cr)、镍(Ni)、锡(Sn)、金(Ag)或它们的组合的铜合金形成种子层。在至少一个实施例中，UBM层22包括Ti层和Cu种子层。
在UBM层22上形成导电柱24。在至少一个实施例中，导电柱24包括Cu层。Cu层包括纯元素铜、含有无法避免的杂质的铜和/或含有少量元素(诸如Ta、铟(In)、SN、锌(Zn)、锰(Mn)、Cr、Ti、锗(Ge)、锶(Sr)、铂(Pt)、镁(Mg)、铝(Al)或锆(Zr)))的铜合金。可通过溅射、印刷、电镀、化学镀、电化学沉积(ECD)、分子束外延(MBE)、原子层沉积(ALD)和/或常用的CVD方法形成导电柱24。在一个实施例中，通过电化学喷镀(ECP)形成Cu层。在一个示例性实施例中，导电柱24的厚度大于20μm。在另一个示例性实施例中，导电柱24的厚度大于40μm。例如，导电柱24具有约为20至50μm的厚度，或者约40至70μm的厚度，虽然厚度可以更大或更小。在至少一个实施例中，导电柱24的尺寸和形状与UBM层22的尺寸和形状基本相同。在一些实施例中，导电柱24的尺寸和形状因为制造工艺引起的偏差而与UBM层22的尺寸和形状不完全相同。例如，UBM层22被底切。
在可选实施例中，在导电柱24上形成可选导电覆盖层。图2是根据一个实施例的可选细长凸块结构的截面图。如前所述，可在导电柱24的顶部上形成可选导电覆盖层26。导电覆盖层26是金属化层，其可以包括镍(Ni)、Sb、锡铅(SnPb)、Au、Ag、钯(Pd)、In、Pt、NiPdAu、NiAu或其它类似的材料或合金。导电覆盖层26可以是多层结构或单层结构。在一些实施例中，导电覆盖层26可具有约1至5μm的厚度。在至少一个实施例中，覆盖层26是可由无铅焊料材料(诸如Sn、SnAg、Sn-Pb、SnAgCu(Cu的重量百分比小于0.3％)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn、SnAgSb以及其它类似的适当材料)制成的焊料层。
任意合适的工艺可用于形成以上讨论的结构，并且文中不再进行更详细地讨论。本领域的技术人员应该认识到，虽然上文的描述提供了实施例的特定特征的一般描述，但是可以存在许多其它特征。例如，芯片可包括其它电路、衬垫、势垒层、互连金属化配置等。上文的描述仅意味着为本文讨论的实施例提供环境，但不意味着将本发明或者任意权利要求的范围限制在这些具体的实施例。
图3是根据一个实施例的部分衬底10的平面图，其包括形成在其上的与上述凸块结构20相同的多个凸块结构(诸如凸块结构20a、20b)。如前所述，任意多种形状中的一种可用于细长凸块结构20a、20b，包括例如卵形或具有两个圆形边的矩形。芯片100的拐角区域100A处的细长凸块结构(诸如凸块结构20a)指向芯片100的中央区域100C，并且与相邻的芯片边缘100B形成约30至60度的角。沿着芯片边缘100B的细长凸块结构(诸如凸块结构20b)被配置为垂直于最近的一个芯片边缘，其中，凸块结构20b对应一个边缘100B。芯片外围和角落区域通常需要最小的间距，因为与位于中央区域100C的电源和接地端相比，它们通常承载更高密度的互连件。如所公开的，与传统圆柱阵列相比，细长凸块结构阵列提供更紧的间距以及更宽的接合工艺窗口。应该注意，仅用于说明的目的，参照沿芯片边缘或芯片角落中定位的细长凸块结构描述本文公开的各个实施例。其它实施例可利用沿着芯片的内部设置的凸块结构。还应该注意，提供细长凸块结构的布置仅仅为了说明的目的，并且凸块结构的具体位置和图案可以改变并且可以包括例如凸块阵列、位于芯片中间区域中的凸块线、交错凸块等。提供所示的芯片和凸块的尺寸仅供参考并且不用于实际尺寸或者实际的相对尺寸。
图4是根据一个实施例的细长凸块结构20的导电柱24的放大图。细长凸块结构20由UBM层22和导电柱24组成。在一个实施例中，细长形状的导电柱24具有长度L和宽度W，其中，L表示沿导电柱24的长轴200测量的长度，而W表示沿导电柱24的短轴300测量的长度。短轴300垂直于长轴200。随衬底10上的凸块结构阵列的布置变化，在一些实施例中，长轴200沿着朝向芯片100的中央区域100C的方向。例如，长轴200垂直于芯片边缘100B，或者长轴200与相邻的芯片边缘100B形成约30至60度的角。
具有细长凸块结构20的芯片100将被接附于工件，诸如封装衬底、印刷电路板(PCB)、平移(translation)焊盘倒装芯片(TPFC)衬底、中介片、晶圆或者使用晶圆级或管芯级堆叠的另一种芯片等。例如，可在管芯-管芯接合配置、管芯-晶圆接合配置、晶圆-晶圆接合配置、管芯级封装、晶圆级封装等中使用实施例。随后，可通过掩模层的开口将细长凸块结构20连接至工件上的金属迹线。
图5是示出芯片(诸如芯片100)附接至工件400的一部分的截面图。图6是示出通过将芯片100附接至工件400来形成倒装芯片封装结构的示例性实施例的截面图。
参照图5，工件400的一部分包括衬底40，其可以是封装衬底、PCB、晶圆、管芯、中介衬底、电介质衬底或其它合适的衬底。衬底40包括电连接至下面的金属互连件的多个导电迹线。导电迹线的一些区域被定义为用于电连接至细长凸块结构20的平台焊盘区域46。可由基本纯的Cu、AlCu或其它金属材料(诸如W、Ni、Pd、Au和它们的合金)形成平台焊盘区域46。在一个实施例中，在衬底40上形成并图案化掩模层48以覆盖部分导电迹线46。在至少一个实施例中，在掩模层48中形成掩模开口50以分别露出部分平台焊盘区域46P。可由阻焊材料层、介电层、聚合物层或者不与焊料材料发生化学反应的任意其它材料形成掩模层48。具有开口50的掩模层48提供窗口用于其它衬底上的焊料接合凸块结构。例如，在掩模开口50中提供包括Sn、Pb、Ag、Cu、Ni、铋(Bi)或它们的组合的合金的焊料层52。
图1或图2中所示的芯片100可被翻转倒置，并且通过倒装芯片接合技术将其附接至图5中的工件400以形成图6所示的封装结构500。示例性连接工艺包括助焊剂应用、芯片布置、回流融化的焊点和/或清洗助焊剂残留物。可执行诸如回流或热压键合的高温工艺以融化衬底40上的焊料层52和/或衬底10上的焊料层26。因此，融化的焊料层将芯片100和工件400连接在一起，并且将细长凸块结构20电连接至平台焊盘区域46P。通过融化焊料层形成的回流区域502在下文称为焊点区域。导电柱24电连接至平台焊盘区域46P，因此在封装结构500中形成互连件。在焊料接合之后，可将模制底部填充物(未示出)填充到芯片100和工件400之间的间隙，因此，还将模制底部填充物填充到相邻导电迹线之间的间隙。可选地，在封装衬底500中没有提供模制底部填充物。
图7是根据一个实施例的图6所示的所得结构的掩模开口50和导电柱24之间的关系的放大俯视图。导电柱24具有沿着其长轴200测量的长度L，以及沿着其短轴300测量的宽度W。长度L大于宽度W。在一个实施例中，长度L约为70至150μm，而宽度W约为40至100μm。掩模开口50具有沿着导电柱24的长轴200测量的第一尺寸d1，以及沿着导电柱24的短轴300测量的第二尺寸d2。各种形状(例如，圆形、多边形或具有径向对称的其它形状)可用于掩模开口50。在一个实施例中，第一尺寸d1等于第二尺寸d2。在另一个实施例中，第一尺寸d1大于第二尺寸d2。在另一个实施例中，第一尺寸d1小于第二尺寸d2。例如，第一尺寸d1约为50至90μm，而第二尺寸d2约为50至90μm。
本实施例示出了提供具有被设计为增加接合可靠性并减少凸块疲劳的几何设计的凸块结构的尺寸/特性。在至少一个实施例中，长度L、宽度W、第一尺寸d1和第二尺寸d2通过以下关系彼此相关：L＞d1以及d2＞W。在一些实施例中，长度L与第一尺寸d1之间的差值约大于20μm。例如，L-d1＞30μm。在一些实施例中，宽度W与第二尺寸d2之间的差值约为2μm。例如，d2-W＞4μm。可以通过减小导电柱24的宽度W来实现诸如本文公开的实施例，使得可增加芯片100上的两个相邻导电柱24之间的间隙并且降低凸块密度。本实施例可以满足用于模制工艺的更好桥接窗口(bridgewindow)和较低工艺成本的需求。从仿真数据来看，与使用设计100μm/70μm/78μm的L/d1/W的凸块结构相比，使用设计112μm/70μm/65μm的L/d1/W的凸块结构可以减少15％的ELK应力并且减少18％的PSC(预焊裂缝)应力。
在一些实施例中，具有细长凸块结构20的芯片100将附接至诸如平移焊盘倒装芯片(TPFC)衬底的可选工件上。图8是示出TPFC衬底的一部分的截面图。图9是示出通过将芯片100附接至TPFC衬底形成的倒装芯片封装结构700的示例性实施例的截面图。
参照图8，根据一些实施例，工件600是TPFC衬底。工件600的一部分包括衬底60、电连接到下面的金属互连件的多个导电区域62。导电区域62中的一些区域被定义为焊盘区域，包括用于电连接至细长凸块结构20的顶部焊盘区域62a、通孔区域62b和底部焊盘区域62c。在一个实施例中，在衬底60上形成并图案化掩模层64以覆盖部分导电区域62，其中在掩模层64内形成底部焊盘区域62c并且顶部焊盘区域62a从掩模层64的顶面64s突出。在至少一个实施例中，在掩模层64中形成掩模开口66，并且导电区域62填充开口66以形成用于连接焊盘区域62a和62c的通孔区域62b。可由基本纯的Cu、AlCu或者诸如W、Ni、Pd、Au以及它们的组合的其它金属材料形成导电区域62。可由阻焊材料层、介电层、聚合物层或者不与焊料材料发生化学反应的任意其它材料形成掩模层64。在顶部焊盘区域62a上提供焊料层68用于其它衬底上的焊料接合凸块结构。例如，焊料层68包括Sn、Pb、Ag、Cu、Ni、铋(Bi)或它们的组合的合金。
图1或图2所示的芯片100可以被翻转倒置并且通过倒装芯片接合技术附接至图8中的工件600以形成图9所示的封装结构500。示例性连接工艺包括助焊剂应用、芯片布置、回流融化的焊点和/或清洗助焊剂残留物。可执行诸如回流或热压键合的高温工艺以融化衬底40上的焊料层68和/或衬底10上的焊料层26。因此，融化的焊料层将芯片100和工件600连接在一起，并且将细长凸块结构20电连接至顶部焊盘区域62a。通过融化焊料层形成的回流区域702在下文称为焊点区域702。导电柱24电连接至顶部焊盘区域62a，因此在封装结构700中形成互连件。
图10是根据实施例的图9所示的所得结构中的掩模开口66和导电柱24的关系的放大俯视图。导电柱24具有沿着其长轴200测量的长度L，以及沿着其短轴300测量的宽度W。长度L大于宽度W。在一个实施例中，长度L约为70至150μm，而宽度W约为40至100μm。掩模开口66具有沿着导电柱24的长轴200测量的第一尺寸d1，以及沿着导电柱24的短轴300测量的第二尺寸d2。各种形状(例如，圆形、多边形或具有径向对称的其它形状)可用于掩模开口66。在一个实施例中，第一尺寸d1等于第二尺寸d2。在另一个实施例中，第一尺寸d1大于第二尺寸d2。在另一个实施例中，第一尺寸d1小于第二尺寸d2。例如，第一尺寸d1约为50至90μm，而第二尺寸d2约为50至90μm。
本实施例示出了提供具有被设计为增加接合可靠性并减少凸块疲劳的几何的凸块结构的尺寸/特性。在至少一个实施例中，长度L、宽度W、第一尺寸d1和第二尺寸d2通过以下关系彼此相关：L＞d1以及d2＞W。在一些实施例中，长度L与第一尺寸d1之间的差值约大于20μm。例如，L-d1＞30μm。在一些实施例中，宽度W与第二尺寸d2之间的差值约为2μm。例如，d2-W＞4μm。
根据示例性实施例的一个方面，一种封装结构包括附接至衬底的芯片。芯片包括凸块结构，其包括具有沿着导电柱的长轴测量的长度(L)和沿着导电柱的短轴测量的宽度(W)的导电柱。衬底包括焊盘区域和位于焊盘区域上方的掩模层，其中，掩模层具有露出部分焊盘区域的开口。芯片附接至衬底以在导电柱和焊盘区域之间形成互连件。开口具有沿着长轴测量的第一尺寸(d1)和沿着短轴测量的第二尺寸(d2)。在一个实施例中，L大于d1，而W小于d2。
根据示例性实施例的一个方面，一种封装结构包括附接至衬底的芯片。芯片包括凸块结构，其包括具有沿着导电柱的长轴测量的长度(L)和沿着导电柱的短轴测量的宽度(W)的导电柱。衬底包括具有开口的掩模层、以及填充掩模层的开口并从掩模层的顶面突出的导电区域。芯片附接至衬底以在导电柱和导电区域之间形成互连件。开口具有沿着长轴测量的第一尺寸(d1)和沿着短轴测量的第二尺寸(d2)。在一个实施例中，L大于d1，而W小于d2。
根据示例性实施例的一个方面，一种形成封装结构的方法，包括：在半导体衬底上形成凸块结构，凸块结构包括具有沿着导电柱的长轴测量的长度(L)和沿着导电柱的短轴测量的宽度(W)的导电柱；在具有焊盘区域的封装衬底上形成阻焊层；在阻焊层中形成开口，其中，开口具有沿着长轴测量的第一尺寸(d1)和沿着短轴测量的第二尺寸(d2)，其中，L大于d1，而W小于d2；以及将芯片附接至封装衬底以在导电柱和焊盘区域之间形成互连件。
在前面的详细描述中，参照本发明的具体示例性实施例描述了本发明。然而，很明显的是，可以进行各种修改、结构、工艺和改变而不背离本发明的宽广精神和范围。因此，说明书和附图被视为说明性的，而不用于限制。应当理解，能够在各个其它组合和环境中本使用发明，并且能够在本文表达的发明概念中改变和修改本发明。

Claims (10)

1.一种封装结构，包括：
芯片，包括凸块结构，所述凸块结构包括导电柱，所述导电柱具有沿着所述导电柱的长轴测量的长度(L)和沿着所述导电柱的短轴测量的宽度(W)；以及
衬底，包括焊盘区域和位于所述焊盘区域上方的掩模层，所述掩模层具有露出部分所述焊盘区域的开口，
其中，所述芯片附接至所述衬底以在所述导电柱和所述焊盘区域之间形成互连件，
其中，所述开口具有沿着所述长轴测量的第一尺寸(d1)和沿着所述短轴测量的第二尺寸(d2)；以及
其中，L大于d1，而W小于d2。
2.根据权利要求1所述的封装结构，进一步包括位于所述导电柱和所述焊盘区域之间的焊点区域。
3.根据权利要求1所述的封装结构，其中，由阻焊材料层形成所述掩模层。
4.根据权利要求1所述的封装结构，其中，所述导电柱包括铜或铜合金。
5.根据权利要求1所述的封装结构，其中，所述导电柱的所述长轴垂直于所述芯片的边缘。
6.根据权利要求1所述的封装结构，其中，所述导电柱的所述长轴沿着朝向所述芯片的中央区域的方向。
7.根据权利要求1所述的封装结构，其中，L与d1之间的差值大于20μm。
8.根据权利要求1所述的封装结构，其中，W与d2之间的差值大于2μm。
9.一种封装结构，包括：
芯片，包括凸块结构，所述凸块结构包括导电柱，所述导电柱具有沿着所述导电柱的长轴测量的长度(L)和沿着导电柱的短轴测量的宽度(W)；以及
衬底，包括位于所述衬底上方并具有开口的掩模层、以及填充所述掩模层的开口并从所述掩模层的顶面突出的导电区域；
其中，所述芯片附接至所述衬底以在所述导电柱和所述导电区域之间形成互连件，
其中，所述开口具有沿着所述长轴测量的第一尺寸(d1)和沿着所述短轴测量的第二尺寸(d2)；以及
其中，L大于d1，而W小于d2。
10.一种形成封装结构的方法，包括：
在半导体衬底上形成凸块结构，其中，所述凸块结构包括导电柱，所述导电柱具有沿着所述导电柱的长轴测量的长度(L)和沿着所述导电柱的短轴测量的宽度(W)；
在具有焊盘区域的封装衬底上形成阻焊层，
在所述阻焊层中形成开口，其中，所述开口具有沿着所述长轴测量的第一尺寸(d1)和沿着所述短轴测量的第二尺寸(d2)，L大于d1，而W小于d2；以及
将芯片附接至所述封装衬底以在所述导电柱和所述焊盘区域之间形成互连件。
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