CN103843142B - IGBT and manufacture method thereof - Google Patents

IGBT and manufacture method thereof Download PDF

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Publication number
CN103843142B
CN103843142B CN201180073862.1A CN201180073862A CN103843142B CN 103843142 B CN103843142 B CN 103843142B CN 201180073862 A CN201180073862 A CN 201180073862A CN 103843142 B CN103843142 B CN 103843142B
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region
body region
type impurity
semiconductor substrate
floating
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CN103843142A (en
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妹尾贤
宫城恭辅
西胁刚
斋藤顺
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Denso Corp
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Toyota Motor Corp
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    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract

The present invention provides a kind of insulated gate bipolar transistor and manufacture method thereof, and this insulated gate bipolar transistor possesses: launch site；Top body district, it is formed on the downside of launch site；Floating region, it is formed on the downside in top body district；Lower bulk district, it is formed on the downside of floating region；Groove；Gate insulating film, the inner surface of its covering groove；Gate electrode, it is configured in the inside of groove.When observing the n-type impurity CONCENTRATION DISTRIBUTION of top body district and the floating region being positioned at downside compared with launch site along the thickness direction of semiconductor substrate, n-type impurity concentration tends to downside along with the upper end from the top body district being positioned at downside compared with launch site and reduces, and the desired depth place in floating region reaches minimum.

Description

IGBT and manufacturing method thereof
Technical Field
The technology disclosed in this specification relates to an IGBT (insulated gate bipolar transistor).
Background
In japanese patent laid-open publication No. 2010-103326 (hereinafter, referred to as patent document 1), an IGBT having a top body region, a floating region, and a bottom body region is disclosed. In manufacturing the IGBT, after forming the trench gate electrode, a p-type impurity is implanted stopping within the depth of the top body region, an n-type impurity is implanted stopping within the depth of the floating region, and a p-type impurity is implanted stopping within the depth of the bottom body region. Thus, a top body region, a floating region, and a bottom body region are formed.
Disclosure of Invention
Problems to be solved by the invention
In the manufacturing method of patent document 1, each impurity is implanted after forming the trench gate electrode. When impurities are implanted into the respective regions after the formation of the trench gate electrode in this manner, it is difficult to accurately control the depth of implantation of impurities into the region in the vicinity of the trench gate electrode due to the influence of the shape of the recess existing in the upper portion of the trench gate electrode. Patent document 1 describes that the depth of the recess is set to a predetermined value, whereby the depth of implantation of the impurity into the region in the vicinity of the trench gate electrode is stabilized. However, even this method causes a certain degree of variation in the implantation depth. Due to this variation in the implantation depth, variations in the on-state voltage or the gate threshold voltage occur between IGBTs that are mass-produced.
In order to prevent variation in the implantation depth of the impurity in the vicinity of the trench gate electrode, it is also conceivable to form the trench gate electrode after implanting the impurity. However, in the method of directly implanting impurities into each region as in patent document 1, each impurity needs to be implanted to a deep position with high energy, and thus damage to the semiconductor substrate is large. When the trench gate electrode is formed on the semiconductor substrate damaged in this way, an oxidation-induced stacking fault (hereinafter referred to as OSF) is generated in the semiconductor substrate in the heat treatment for forming the gate insulating film. This method is difficult to adopt because a leakage current is generated in the semiconductor substrate on which the OSF is formed.
Therefore, in the present specification, a technique capable of suppressing a deviation of an on-state voltage and a gate threshold voltage between IGBTs that are mass-produced is provided.
Means for solving the problems
The IGBT provided in this specification includes a semiconductor substrate. The IGBT has: an emitter region, a top body region, a floating region, a bottom body region, a trench, a gate insulating film, and a gate electrode. The emitter region is an n-type region formed in a range exposed on the upper surface of the semiconductor substrate. The top body region is a p-type region formed on the lower side of the emitter region. The floating region is an n-type region formed under the top body region and separated from the emitter region by the top body region. The bottom body region is a p-type region formed on the lower side of the floating region and separated from the top body region by the floating region. A trench is formed on an upper surface of the semiconductor substrate and penetrates the emitter region, the top body region, the floating region, and the bottom body region. The gate insulating film covers an inner surface of the trench. The gate electrode is disposed inside the trench. When the p-type impurity concentration distribution in the floating region and the top body region located on the lower side than the emitter region is viewed in the thickness direction of the semiconductor substrate, the p-type impurity concentration decreases from the upper end of the top body region located on the lower side than the emitter region toward the lower side, and reaches an extremely small value at a predetermined depth in the floating region.
In addition, the top body region may be formed not only on the lower side of the emitter region but also on the side of the emitter region. The above-mentioned "range exposed to the upper surface of the semiconductor substrate" means a range which appears on the upper surface of the semiconductor substrate when the electrode or the insulating film formed on the semiconductor substrate is removed. Therefore, even a region whose surface is covered with an electrode or an insulating film may correspond to "a range exposed to the upper surface of the semiconductor substrate". In the description of the impurity concentration distribution in the semiconductor substrate, a waveform having an amplitude of less than 30% of the impurity concentration is a noise generated by a measurement error and is not used as a maximum value or a minimum value. For example, when the p-type impurity concentration distribution in the top body region and the floating region is obtained as shown by the curve a in fig. 41, the positive peak a1 and the negative peak a2 are not used as the maximum value and the minimum value. This is because the amplitude Aw (= (a 1-a 2)/2) of the waveform containing the values a1, a2 is less than 30% of the average value A3 of the values a1 and a 2. When disregarding such a smaller waveform, curve a may be considered like curve B. The positive peak B1 of the curve B is used as a maximum value, and the negative peak B2 is used as a minimum value. This is because the amplitude Bw of the waveform containing the value B1 and the value B2 (B1 to B2)/2) is greater than 30% of the average value B3 of the values B1 and B2. Therefore, the curve a shown in fig. 41 has a structure in which "the p-type impurity concentration decreases as going from the upper end of the top body region located on the lower side than the emitter region toward the lower side, and reaches a minimum value at a predetermined depth within the floating region". Fig. 41 is an exemplary view for explanation, and does not limit the claims. For example, the positive peak B1 may not be present in the bottom body region.
Thus, the top body region in which the p-type impurity concentration is distributed so as to decrease toward the lower side can be formed by implanting a p-type impurity to the vicinity of the upper surface of the semiconductor substrate (within the depth range of the emitter region) and diffusing the implanted p-type impurity. In this method, since the top body region is formed by diffusing the p-type impurity implanted to a shallow position, even if the top body region is formed after forming the trench gate electrode (combination of the gate electrode and the gate insulating film arranged in the trench), the p-type impurity concentration distribution in the top body region is hardly affected by the shape of the trench gate electrode. In addition, in this method, the trench gate electrode can also be formed after the top body region is formed. Even in this case, the OSF is hardly generated in and around the top body region. This is because, since the p-type impurity is implanted in the vicinity of the upper surface of the semiconductor substrate, the peak of the p-type impurity does not exist in the top body region, and the top body region is hardly damaged. Thus, the top body region can be stably formed both before and after formation of the trench gate electrode. The p-type impurity concentration distribution of the top body region has a large influence on the gate threshold voltage of the IGBT. Therefore, when the IGBTs are mass-produced, variations in gate threshold voltage are less likely to occur between the mass-produced IGBTs. In addition, the floating region having the minimum value of the p-type impurity concentration can be realized by implanting a p-type impurity into a region (for example, a bottom body region) on a lower side than the floating region. Since the minimum value of the p-type impurity concentration is set in the floating region in this manner so that the concentration difference between the n-type impurity and the p-type impurity in the floating region becomes large, the floating region can be stably formed. The impurity concentration of the floating region affects the on-state voltage of the IGBT. Therefore, when the IGBTs are mass-produced, variation in on-state voltage is less likely to occur between the mass-produced IGBTs. Further, since the p-type impurity is implanted into a region lower than the floating region with high energy, it is necessary to perform the implantation after the trench gate electrode is formed. When the implantation of the p-type impurity into a deep position is performed after the trench gate electrode is formed, as described above, the implantation depth of the impurity in the vicinity of the trench gate electrode becomes unstable. Therefore, it becomes difficult to control the impurity concentration of a region (for example, a bottom body region) lower than the floating region. However, the inventors of the present invention have found that the impurity concentration distribution in the vicinity of the trench gate electrode on the lower side than the floating region does not greatly affect the characteristics (on-state voltage, gate threshold voltage, and the like) of the IGBT. Therefore, variations in characteristics of the IGBT due to variations in impurity concentration distribution in a region below the floating region hardly occur. Therefore, when the IGBTs are mass-produced, variations in on-state voltage and gate threshold voltage are unlikely to occur between the IGBTs.
In the IGBT described above, it is preferable that when the n-type impurity concentration distribution in the floating region is observed along the thickness direction of the semiconductor substrate, the maximum value of the n-type impurity concentration is not present in the floating region.
Such a floating region can be formed by implanting an n-type impurity into the vicinity of the upper surface of the semiconductor substrate (within the depth range of the emitter region) and diffusing the implanted n-type impurity. Alternatively, such floating regions can also be formed by epitaxial growth. According to these methods, the n-type impurity concentration in the floating region can be controlled without being affected by the shape of the trench gate electrode. Therefore, when the IGBTs are mass-produced, variation in on-state voltage is less likely to occur between the IGBTs.
In the IGBT described above, the floating region is preferably formed by an epitaxial layer.
With this structure, the n-type impurity concentration in the floating region can be made substantially constant. Therefore, the n-type impurity concentration in the floating region can be more accurately controlled. Therefore, when the IGBTs are mass-produced, variation in on-state voltage is less likely to occur between the IGBTs.
In the IGBT described above, preferably, when the p-type impurity concentration distribution in the bottom body region is observed along the thickness direction of the semiconductor substrate, the p-type impurity concentration has a maximum value in the bottom body region.
When the p-type impurity concentration has a maximum value in the bottom body region in this manner, the position of the lower end of the floating region is less likely to be displaced between IGBTs when the IGBTs are mass-produced. Therefore, when the IGBTs are mass-produced, variation in on-state voltage is less likely to occur between the IGBTs.
In the IGBT described above, preferably, the width of the floating region in the thickness direction of the semiconductor substrate is wider at a position in contact with the gate insulating film than at a position away from the gate insulating film.
In this way, if the width of the floating region is increased near the gate insulating film through which holes easily flow, more holes can be accumulated in a region (for example, a drift region) below the floating region when the IGBT is turned on. Therefore, according to this structure, the on-state voltage of the IGBT can be reduced.
In the IGBT described above, preferably, the lower end of the bottom body region is located lower in contact with the gate insulating film than in a position away from the gate insulating film.
With this structure, the feedback capacitance of the IGBT can be reduced.
Further, the present specification provides a new method of manufacturing the IGBT. The manufacturing method comprises the following steps: forming an n-type emitter region in a range exposed on an upper surface of the semiconductor substrate; a step of forming a p-type top body region on the lower side of the depth range of the emitter region by implanting a p-type impurity into the upper surface of the semiconductor substrate so as to stop within the depth range of the emitter region and diffusing the implanted p-type impurity; forming an n-type floating region on the lower side of the depth range of the top body region by implanting an n-type impurity into the upper surface of the semiconductor substrate so as to stop within the depth range of the emitter region and diffusing the implanted n-type impurity; forming a trench on an upper surface of the semiconductor substrate, and forming a gate insulating film covering an inner surface of the trench and a gate electrode disposed in the trench; and forming a p-type bottom body region below the depth range of the floating region by implanting a p-type impurity into the upper surface of the semiconductor substrate so as to stop at a depth below the depth range of the floating region after forming the trench, the gate insulating film, and the gate electrode. After the above steps are performed, the trench is disposed so as to penetrate the emitter region, the top body region, the floating region, and the bottom body region.
The step of forming the emitter region, the step of forming the top body region, the step of forming the floating region, and the step of forming the trench, the gate insulating film, and the gate electrode may be performed in any order. Therefore, the above-described "depth range of the emitter region" has a case of being the depth range of the emitter region which has already been formed and a case of being the depth range of the emitter region which is to be formed. Similarly, the "depth range of the top body region" and the "depth range of the floating region" also exist in the case of the depth range of the region that has already been formed, and in the case of the depth range of the region to be formed. In this specification, the fact that the impurity is implanted so as to stop in a predetermined depth range means that the average stop position of the implanted impurity is in the predetermined depth range.
According to this method, the top body region and the floating region can be stably formed by impurity diffusion. Further, since the bottom body region is formed by implanting a p-type impurity into a deep position after the trench gate electrode is formed, the bottom body region can be formed without excessively raising the p-type impurity of the floating region. Therefore, when the IGBTs are mass-produced by the manufacturing method, it is possible to suppress the variation in the on-state voltage and the gate threshold voltage between the mass-produced IGBTs.
In the above-described manufacturing method, it is preferable that the step of forming the top body region and the step of forming the floating region are performed before the step of forming the trench, the gate insulating film, and the gate electrode.
According to this manufacturing method, the width of the floating region in the vicinity of the gate insulating film is widened when the gate insulating film is formed. Therefore, according to this manufacturing method, an IGBT with a lower on-state voltage can be manufactured.
In the above-described manufacturing method, preferably, in the step of forming the bottom body region, the p-type impurity is implanted into the semiconductor substrate in a state where the upper surface of the gate electrode is located lower than the upper surface of the semiconductor substrate.
According to this manufacturing method, the bottom body region can be formed such that the lower end thereof is located lower in the position in contact with the gate insulating film than in the position away from the gate insulating film. Therefore, the feedback capacitance of the IGBT can be reduced.
In addition, the present specification provides other manufacturing methods. The manufacturing method of the IGBT comprises the following steps: a step of forming an epitaxial layer made of an n-type semiconductor on the upper surface of the base substrate; forming an n-type emitter region in a range exposed on an upper surface of the epitaxial layer; forming a p-type top body region on the lower side of the depth range of the emitter region by implanting a p-type impurity into the upper surface of the epitaxial layer so as to stop within the depth range of the emitter region and diffusing the implanted p-type impurity; forming a trench in an upper surface of the epitaxial layer, and forming a gate insulating film covering an inner surface of the trench and a gate electrode disposed in the trench; and forming a p-type bottom body region in the base substrate by injecting a p-type impurity into the upper surface of the epitaxial layer so as to stop in the base substrate after the trench, the gate insulating film, and the gate electrode are formed. After the above steps are performed, the floating region is formed by leaving the n-type epitaxial layer between the top body region and the bottom body region, and the trench is disposed so as to penetrate the emitter region, the top body region, the floating region, and the bottom body region.
According to this manufacturing method, the top body region and the floating region can be stably formed by epitaxial growth and impurity diffusion. Therefore, when IGBTs are mass-produced by this manufacturing method, it is possible to suppress the generation of variations in the on-state voltage and the gate threshold voltage between IGBTs. In addition, in this manufacturing method, the floating region is formed of an n-type epitaxial layer. Therefore, the n-type impurity concentration in the floating region can be made substantially constant. Therefore, when the IGBTs are mass-produced, the on-state voltage is less likely to vary between the IGBTs.
In the above-described method for manufacturing an epitaxial layer, the step of forming the top body region is preferably performed before the step of forming the trench, the gate insulating film, and the gate electrode.
According to this manufacturing method, the width of the n-type epitaxial layer (i.e., floating region) in the vicinity of the gate insulating film is widened when the gate insulating film is formed. Therefore, according to this manufacturing method, an IGBT with a lower on-state voltage can be manufactured.
In the above-described manufacturing method for growing an epitaxial layer, it is preferable that, in the step of forming the bottom body region, a p-type impurity is implanted into the semiconductor substrate in a state where an upper surface of the gate electrode is located lower than an upper surface of the semiconductor substrate.
According to this manufacturing method, the bottom body region can be formed such that the lower end thereof is located lower in the position in contact with the gate insulating film than in the position away from the gate insulating film. Therefore, the feedback capacitance of the IGBT can be reduced.
Drawings
Fig. 1 is a longitudinal sectional view of an IGBT10 of the first embodiment.
Fig. 2 is a plan view of IGBT10 with emitter 60, cap insulating film 46, and interlayer insulating film 47 omitted from illustration.
Fig. 3 is a graph showing an impurity concentration distribution in the semiconductor substrate at the line a-a of fig. 1.
Fig. 4 is a graph showing an impurity concentration distribution in the semiconductor substrate at the line B-B of fig. 1.
Fig. 5 is a flowchart illustrating a method of manufacturing the IGBT 10.
Fig. 6 is a vertical cross-sectional view of the semiconductor substrate 100 before the manufacturing method of fig. 5 is started.
Fig. 7 is a longitudinal sectional view of the semiconductor substrate 100 after step S2 is performed.
Fig. 8 is a graph showing the impurity concentration distribution in the semiconductor substrate 100 at the line C-C of fig. 7.
Fig. 9 is a longitudinal sectional view of the semiconductor substrate 100 after step S4 is performed.
Fig. 10 is a graph showing the impurity concentration distribution in the semiconductor substrate 100 at the line D-D of fig. 9.
Fig. 11 is a longitudinal sectional view of the semiconductor substrate 100 after step S6 is performed.
Fig. 12 is a graph showing the impurity concentration distribution in the semiconductor substrate 100 at the line E-E of fig. 11.
Fig. 13 is a longitudinal sectional view of the semiconductor substrate 100 after step S8 is performed.
Fig. 14 is a longitudinal sectional view of the semiconductor substrate 100 after step S10 is performed.
Fig. 15 is a vertical cross-sectional view of the semiconductor substrate 100 after step S12 is performed.
Fig. 16 is an enlarged view of the upper surface of the gate electrode 44 of fig. 15.
Fig. 17 is a longitudinal sectional view of the semiconductor substrate 100 after step S14 is performed.
Fig. 18 is a longitudinal sectional view of the semiconductor substrate 100 after step S16 is performed.
Fig. 19 is a vertical cross-sectional view illustrating another method of forming the wide portion of the floating region 24.
Fig. 20 is a vertical cross-sectional view illustrating another method of forming the wide portion of the floating region 24.
Fig. 21 is a longitudinal sectional view of an IGBT having a wide portion 24 b.
Fig. 22 is a plan view of the IGBT according to the first modification corresponding to fig. 2.
Fig. 23 is a plan view of the IGBT according to the second modification corresponding to fig. 2.
Fig. 24 is a graph showing the impurity concentration distribution at a position corresponding to fig. 4 of the IGBT according to the third modification.
Fig. 25 is a graph showing an impurity concentration distribution at a position corresponding to fig. 3 of the IGBT according to the fourth modification.
Fig. 26 is a graph showing an impurity concentration distribution at a position corresponding to fig. 3 of the IGBT according to the fifth modification.
Fig. 27 is a graph showing an impurity concentration distribution at a position corresponding to fig. 3 of the IGBT according to the sixth modification.
Fig. 28 is a graph showing an impurity concentration distribution at a position corresponding to fig. 3 of the IGBT according to the seventh modification example.
Fig. 29 is a graph showing an impurity concentration distribution at a position corresponding to fig. 3 in the IGBT according to the eighth modification.
Fig. 30 is a graph showing the impurity concentration distribution at the position corresponding to fig. 3 of the IGBT according to the second embodiment.
Fig. 31 is a flowchart showing a method for manufacturing the IGBT according to the second embodiment.
Fig. 32 is a longitudinal sectional view of the semiconductor substrate 300 after step S32 is performed.
Fig. 33 is a graph showing the impurity concentration distribution in the semiconductor substrate 300 at the line G-G of fig. 32.
Fig. 34 is a longitudinal sectional view of the semiconductor substrate 300 after step S34 is performed.
Fig. 35 is a vertical cross-sectional view of the semiconductor substrate 300 after step S42 is performed.
Fig. 36 is a longitudinal sectional view of the semiconductor substrate 300 after step S44 is performed.
Fig. 37 is a graph of impurity concentration distribution at each point corresponding to fig. 30 of the IGBT of the eighth modification.
Fig. 38 is a graph of the impurity concentration distribution at the position corresponding to fig. 30 of the IGBT according to the ninth modification.
Fig. 39 is a graph showing the impurity concentration distribution at the position corresponding to fig. 30 of the IGBT according to the tenth modification example.
Fig. 40 is a graph of the impurity concentration distribution at the position corresponding to fig. 30 of the IGBT according to the eleventh modification.
Fig. 41 is a graph illustrating a maximum value and a minimum value of the impurity concentration distribution.
Detailed Description
(first embodiment)
The IGBT10 shown in fig. 1 is composed of a semiconductor substrate 12, and electrodes, insulating films, and the like formed on the upper surface and the lower surface of the semiconductor substrate 12.
A plurality of trenches 40 are formed on the upper surface of the semiconductor substrate 12. The inner surface of each trench 40 is covered with a gate insulating film 42. A gate electrode 44 is formed inside each trench 40. The upper surface of the gate electrode 44 is covered with a cap insulating film 46. Further, an interlayer insulating film 47 is formed on the cap insulating film 46. However, the gate electrode 44 can be connected to the outside at a position not shown in the figure. Hereinafter, the gate insulating film 42 and the gate electrode 44 formed in the trench 40 may be collectively referred to as a trench gate electrode 48. As shown in fig. 2, the respective trench gate electrodes 48 extend in parallel with each other.
Inside the semiconductor substrate 12 are formed: emitter region 20, top body region 22, floating region 24, bottom body region 26, drift region 28, buffer region 30, and collector region 32.
The emitter region 20 is an n-type region, and is selectively formed in a range exposed on the upper surface of the semiconductor substrate 12. The emitter region 20 is in contact with the gate insulating film 42. As shown in fig. 2, the emitter regions 20 extend in parallel along the trench gate electrodes 48.
The top body region 22 is a p-type region, and is formed on the lower side of the emitter region 20 and on the side of the emitter region 20. As shown in fig. 1 and 2, the top body region 22 is exposed at the upper surface of the semiconductor substrate 12 between the two emitter regions 20. The top body region 22 is in contact with the gate insulating film 42 below the emitter region 20.
The floating region 24 is an n-type region and is formed on the underside of the top body region 22. The floating region 24 is separated from the emitter region 20 by the top body region 22. The floating region 24 is in contact with the gate insulating film 42. The boundary on the upper side of the floating region 24 is displaced upward as it approaches the gate insulating film 42. The lower boundary of the floating region 24 is displaced downward as it approaches the gate insulating film 42. Therefore, the width of the floating region 24 in the thickness direction of the semiconductor substrate 12 varies depending on the position. That is, the width W1 of the floating region 24 at the position in contact with the gate insulating film 42 is larger than the width W2 of the floating region 24 at the position away from the gate insulating film 42. Hereinafter, the floating region 24 having a portion with the width W1 is referred to as a wide portion 24 a.
The bottom body region 26 is a p-type region and is formed on the underside of the floating region 24. The bottom body regions 26 are separated from the top body regions 22 by floating regions 24. The bottom body region 26 is in contact with the gate insulating film 42. The lower boundary of the bottom body region 26 is located lower at a position in contact with the gate insulating film 42 than at a position away from the gate insulating film 42. That is, in the bottom body region 26 in the portion in contact with the gate insulating film 42, a displacement portion 26a is formed so as to be displaced downward along the gate insulating film 42.
The drift region 28 is an n-type region containing a low concentration of n-type impurities. A drift region 28 is formed under the bottom body region 26. The drift region 28 is separated from the floating region 24 by the bottom body region 26. The drift region 28 is in contact with a gate insulating film 42 located at the lower end of the trench 40.
The buffer region 30 is an n-type region containing n-type impurities at a higher concentration than the drift region 28. A buffer region 30 is formed on the lower side of the drift region 28.
Collector region 32 is a p-type region containing a high concentration of p-type impurities. Collector region 32 is formed in a range exposed to the lower surface of semiconductor substrate 12. Collector region 32 is separated from bottom body region 26 by drift region 28 and buffer region 30.
Since each region is formed inside the semiconductor substrate 12 as described above, each trench 40 is disposed so as to penetrate the emitter region 20, the top body region 22, the floating region 24, and the bottom body region 26 and reach the drift region 28. The gate electrode 44 is opposed to the emitter region 20, the top body region 22, the floating region 24, and the bottom body region 26 via the gate insulating film 42 on the side surface of the trench 40.
An emitter electrode 60 is formed on the upper surface of the semiconductor substrate 12. The emitter 60 is ohmically connected with respect to the emitter region 20 and the top body region 22. Emitter 60 is insulated from gate electrode 44 by cap insulating film 46 and interlayer insulating film 47. A collector electrode 62 is formed on the lower surface of the semiconductor substrate 12. The collector 62 is ohmically connected with respect to the collector region 32.
Fig. 3 is a graph showing the concentration distributions of the n-type impurity and the p-type impurity in the semiconductor substrate 12 as viewed along the line a-a in fig. 1, and fig. 4 is a graph showing the concentration distributions of the n-type impurity and the p-type impurity in the semiconductor substrate 12 as viewed along the line B-B in fig. 1. In fig. 3 and 4 and other diagrams (except fig. 41) showing the impurity concentration distribution, graphs of minute noise waveforms with measurement error levels removed are shown. In these figures, a logarithmic axis is used as an axis indicating the concentration.
As shown in fig. 3, the p-type impurity concentration is maximum at the upper end of the emitter region 20. The P-type impurity concentration decreases as going from the upper end of the emitter region 20 to the lower side and reaches a minimum value P in the floating region 24LL. The concentration of P-type impurity follows the minimum value PLLIncreases toward the lower side and reaches a maximum value P in the bottom body region 26LH. The concentration of P-type impurity follows the maximum value PLHDecreases towards the lower side and reaches substantially zero at the boundary of the bottom body region 26 and the drift region 28.
The n-type impurity concentration is maximum at the upper end of the emitter region 20. The n-type impurity concentration decreases as going from the upper end of the emitter region 20 to the lower side. The reduction ratio of the n-type impurity concentration becomes gentle at the position 22C within the top body region 22. However, in the region on the lower side from the position 22C, the n-type impurity concentration also decreases toward the lower side. The N-type impurity concentration is reduced to a value of N in the bottom body region 26LAnd the N-type impurity concentration in the drift region 28 is substantially fixed at a value NL。
Further, as shown in fig. 4, even along the line B-B, the p-type impurity concentration is distributed in substantially the same manner as the p-type impurity concentration at the line a-a. Further, at the B-B line, the n-type impurity concentration is lower than the p-type impurity concentration in the depth range of the emitter region 20. Even along the B-B line, the n-type impurity concentration is distributed in substantially the same manner as the n-type impurity concentration at the a-a line at the lower side compared to the depth range of the emitter region 20.
Next, a method for manufacturing the IGBT10 will be described. The IGBT10 is manufactured according to the flowchart shown in fig. 5. The IGBT10 is manufactured from the semiconductor substrate 100 shown in fig. 6. The semiconductor substrate 100 has substantially the same N-type impurity concentration N as the drift region 28L(about 1 × 10 in the present embodiment)14cm3) An n-type silicon substrate of (2). The thickness of the semiconductor substrate 100 is about 700 μm.
In step S2, as shown in fig. 7, the floating region 24 is formed on the semiconductor substrate 100. specifically, first, an n-type impurity (phosphorus in the present embodiment) is ion-implanted into the upper surface of the semiconductor substrate 100. here, the acceleration energy of the ions is set to 30keV to 300keV, and the implantation amount is set to 1 × 1011～1×1014/cm2. The implantation of the n-type impurity is performed so that the implanted n-type impurity stops in a region near the upper surface of the semiconductor substrate 100 (a depth range where the emitter region 20 is formed later). More specifically, the n-type impurity is implanted so that the average stop position of the implanted n-type impurity is in a region (a depth range in which the emitter region 20 is formed later) near the upper surface of the semiconductor substrate 100. Next, the semiconductor substrate 100 is subjected to heat treatment. Here, under nitrogen (N)2) Or oxygen (O)2) The semiconductor substrate 100 is maintained at 900 to 1250 ℃ for 30 to 120 minutes in an atmosphere. The atmosphere for the heat treatment may be a mixed atmosphere of nitrogen and oxygen, or may be a mixture of oxygen, nitrogen, or a mixed gas thereof, to which hydrogen (H) is added2) Of the atmosphere (c). By performing the heat treatment, the n-type impurity implanted into the semiconductor substrate 100 is diffused and activated. Thereby, as shown in FIG. 7, a semiconductor substrate 100 is formedA floating region 24. As shown in fig. 8, in the floating region 24, the n-type impurity concentration is highest at a position on the upper surface of the semiconductor substrate 100 and decreases from the position toward the lower side. The reason why the n-type impurity is distributed in concentration in this manner is that the n-type impurity is implanted so as to stop near the upper surface of the semiconductor substrate 100, and is diffused.
In step S4, as shown in fig. 9, the top body region 22 is formed in the semiconductor substrate 100. specifically, first, a p-type impurity (boron in the present embodiment) is ion-implanted into the upper surface of the semiconductor substrate 100. here, the acceleration energy of the ions is set to 30keV to 150keV, and the implantation amount is set to 1 × 1011～5×1014/cm2. The implantation of the p-type impurity is performed so that the implanted p-type impurity stops in a region near the upper surface of the semiconductor substrate 100 (a depth range where the emitter region 20 is formed later). More specifically, the p-type impurity is implanted so that the average stop position of the implanted p-type impurity is in a region (a depth range in which the emitter region 20 is formed later) near the upper surface of the semiconductor substrate 100. Next, the semiconductor substrate 100 is subjected to heat treatment. The semiconductor substrate 100 is maintained at 900 to 1250 ℃ for 30 to 120 minutes in an atmosphere of nitrogen, oxygen, a mixed gas of nitrogen and oxygen, or a gas obtained by adding hydrogen thereto. By performing the heat treatment, the p-type impurity implanted into the semiconductor substrate 100 is diffused and activated. Thereby, as shown in fig. 9, the top body region 22 is formed inside the semiconductor substrate 100. As shown in fig. 10, the p-type impurity concentration in the semiconductor substrate 100 is highest at a position on the upper surface of the semiconductor substrate 100 and decreases from the position toward the lower side. The reason why the p-type impurity concentration is distributed in this manner is that the p-type impurity is implanted so as to stop near the upper surface of the semiconductor substrate 100 and is diffused.
In step S6, as shown in fig. 11, emitter regions 20 are formed in the semiconductor substrate 100. Specifically, first, a resist layer (res) is formed on the upper surface of the semiconductor substrate 100ist) the resist layer is formed so as to cover a range where the emitter region 20 is not formed (a range where the top body region 22 is exposed to the upper surface of the semiconductor substrate 100 in fig. 11), next, an n-type impurity (arsenic in the present embodiment) is ion-implanted into the upper surface of the semiconductor substrate 100, here, the acceleration energy of the ions is set to 30keV to 150keV, and the implantation amount is set to 1 × 1013～1×1016/cm2. Thereby, the n-type impurity is implanted into the upper surface of the semiconductor substrate 100 in the region not covered with the resist. The implantation of the n-type impurity is performed so that the n-type impurity stops in a region near the upper surface of the semiconductor substrate 100. Next, the semiconductor substrate 100 is subjected to heat treatment. The semiconductor substrate 100 is maintained at 900 to 1250 ℃ for 20 to 120 minutes in an atmosphere of nitrogen, oxygen, a mixed gas of nitrogen and oxygen, or a gas obtained by adding hydrogen thereto. By performing the heat treatment, the n-type impurity implanted into the semiconductor substrate 100 is diffused and activated. Thereby, as shown in fig. 11, the emitting region 20 is formed. As shown in fig. 12, the n-type impurity concentration in the emitter region 20 is highest at a position on the upper surface of the semiconductor substrate 100 and decreases from the position toward the lower side. The reason why the n-type impurity concentration is distributed in this manner is that the n-type impurity is implanted so as to stop near the upper surface of the semiconductor substrate 100 and is diffused.
In step S8, as shown in fig. 13, the trench 40 is formed on the upper surface of the semiconductor substrate 100. Specifically, first, an etching mask is formed on the upper surface of the semiconductor substrate 100. On the etching mask, an opening is formed in advance in a region where the trench 40 is to be formed. Next, the upper surface of the semiconductor substrate 100 in the opening portion is etched by anisotropic etching such as RIE (reactive ion etching). Thereby, the trench 40 is formed on the upper surface of the semiconductor substrate 100. The trench 40 is formed to a depth corresponding to the depth of the drift region 28 in fig. 1. The etch mask is removed after etching.
In step S10, the semiconductor substrate 100 is heat-treated at 800 to 1150 ℃ in an oxidizing atmosphere. Thereby, as shown in fig. 14, an oxide film is formed on the surface of the semiconductor substrate 100. At this time, an oxide film is also formed on the inner surface of the trench 40. The oxide film formed on the inner surface of the trench 40 is a gate insulating film 42. When an oxide film (gate insulating film 42) is grown on the inner surface of the trench 40, the grown oxide film absorbs p-type impurities from the surrounding region, and discharges n-type impurities from among the oxide film itself to the surrounding region. This phenomenon is commonly referred to as segregation. Due to this segregation, when the gate insulating film 42 is formed, as shown in fig. 14, the width of the floating region 24 (the width along the thickness direction of the semiconductor substrate 100) in the vicinity of the gate insulating film 42 is enlarged. As a result, the wide portion 24a of the floating region 24 is formed in the region in contact with the gate insulating film 42.
In step S12, polycrystalline silicon is grown on the surface of the semiconductor substrate 100. Thereby, the inside of the trench 40 is filled with polysilicon. Next, the polysilicon formed on the upper surface of the semiconductor substrate 100 is removed by etching. As a result, the semiconductor substrate 100 is in the state shown in fig. 15. As shown in fig. 15, the gate electrode 44 is formed by polysilicon remaining inside the trench 40. As shown in fig. 16, step S12 is performed such that the upper surface of the gate electrode 44 is located below the upper surface of the semiconductor substrate 100. That is, after step S12 is performed, a step H1 is formed between the gate electrode 44 and the upper surface of the semiconductor substrate 100.
In step S13, the semiconductor substrate 100 is heat-treated in an oxidizing atmosphere. Thereby, the upper surface of the gate electrode 44 is oxidized, and the cap insulating film 46 is formed. Here, the cap insulating film 46 is formed to a thickness of about 30 nm.
In step S14, a p-type impurity is implanted into the semiconductor substrate 100 to form the bottom body region 26. specifically, first, the p-type impurity (boron in the present embodiment) is ion-implanted into the upper surface of the semiconductor substrate 100. here, the acceleration energy of the ions is set to 300keV to 3MeV, and the implantation amount is set to 1 × 1011～1×1014/cm2. The implantation of the p-type impurity is performed so that the p-type impurity stops in a region below the floating region 24 (a depth range where the bottom body region 26 is to be formed). More specifically, the p-type impurity is implanted so that the average stop position of the implanted p-type impurity is located in a region (depth range in which the bottom body region 26 is to be formed) below the floating region 24.
In step S15, an interlayer insulating film 47 is formed on the semiconductor substrate 100 by CVD (chemical vapor deposition). Here, the interlayer insulating film 47 is formed to have a thickness of about 1000 nm.
In step S16, the bottom body region 26 is formed. Specifically, the semiconductor substrate 100 is heat-treated by reflow. In this heat treatment, the semiconductor substrate 100 is maintained at a temperature of 900 to 1000 ℃ for 15 to 60 minutes in a nitrogen atmosphere (i.e., a non-oxidizing atmosphere). By performing the heat treatment, the p-type impurity implanted into the semiconductor substrate 100 in step S14 is diffused and activated. Thereby, as shown in fig. 17, the bottom body region 26 is formed in the semiconductor substrate 100. In addition, since the heat treatment is performed in a non-oxidizing atmosphere, OSF can be prevented from being generated in the semiconductor substrate 100. In addition, the lower n-type region of the bottom body region 26 is the drift region 28. When step S14 is performed, the impurity concentration distribution in the semiconductor substrate 100 along the F-F line of fig. 17 becomes the distribution shown in fig. 3. A maximum value P of the P-type impurity concentration is formed in the bottom body region 26LHThis is because the ion implantation in step S14 is performed so that the p-type impurity stops within the range where the bottom body region 26 is to be formed. Further, since the P-type impurity concentration of the bottom body region 26 becomes high in this way, the minimum value P of the P-type impurity concentration is formed within the floating region 24LL。
In addition, as described above, in the implantation of the p-type impurity in step S14, the step H1 is formed between the upper surface of the gate electrode 44 and the upper surface of the semiconductor substrate 100. Therefore, due to the influence of the shape of the step H1, the average stop position of the p-type impurity is located lower in the region near the trench gate electrode 48 than in the region distant from the trench gate electrode 48. Therefore, the displacement portion 26a is formed in the bottom body region 26 in the range in contact with the gate insulating film 42.
In step S17, the insulating film covering the emitter region 20 and the top body region 22 is removed. Next, as shown in fig. 18, emitter electrodes 60 are formed on the upper surface of semiconductor substrate 100.
In step S18, the lower surface of the semiconductor substrate 100 is processed. Specifically, first, the lower surface of the semiconductor substrate 100 is polished to thin the semiconductor substrate 100. Next, the buffer region 30 and the collector region 32 are formed inside the semiconductor substrate 100 by ion implantation and heat treatment with respect to the lower surface of the semiconductor substrate 100. Thereafter, the collector electrode 62 is formed on the lower surface of the semiconductor substrate 100. When step S18 is performed, the IGBT10 shown in fig. 1 is completed.
Next, the operation of the IGBT10 will be described. When a voltage equal to or higher than the gate threshold voltage (the minimum gate voltage required to turn on the IGBT 10) is applied to the gate electrode 44 in a state where a voltage that makes the collector 62 positive is applied between the emitter 60 and the collector 62, the IGBT10 is turned on. That is, a channel is formed in the top body region 22 and the bottom body region 26 in the region in contact with the gate insulating film 42, and electrons flow from the emitter region 20 to the collector region 32 through the channel. At the same time, holes flow from the collector region 32 into the drift region 28. By the inflow of holes into the drift region 28, a conductivity modulation phenomenon is caused in the drift region 28, and the resistance of the drift region 28 decreases. Therefore, electrons flow in the drift region 28 with low loss. Further, the holes flowing into the drift region 28 flow from the drift region 28 toward the top body region 22. However, the floating region 24 exists between the drift region 28 and the top body region 22, and the floating region 24 serves as a barrier to suppress the movement of holes toward the top body region 22. Therefore, the concentration of holes in the drift region 28 becomes high, and the resistance of the drift region 28 further decreases. Thereby, the on-state voltage of the IGBT10 decreases.
In the above-described manufacturing method, the top body region 22 is formed by diffusing the p-type impurity implanted in the vicinity of the upper surface of the semiconductor substrate 100. As a result, the p-type impurity concentration decreases from the upper side toward the lower side in the top body region 22. According to this method, the top body region 22 can be formed without forming defects such as OSFs in the semiconductor substrate 100 and without being affected by the shape of the trench gate electrode 48. That is, the position of the top body region 22 and the p-type impurity concentration in the top body region 22 can be accurately controlled. Therefore, when the IGBTs 10 of the first embodiment are mass-produced, variations in gate threshold voltage are less likely to occur between the mass-produced IGBTs 10.
Further, in the above-described manufacturing method, the bottom body region 26 is formed by implanting p-type impurities to the depth of the bottom body region 26 directly after forming the trench gate electrode 48. Therefore, the bottom body region 26 can be formed under the condition that the p-type impurity concentration in the floating region 24 is not substantially increased. As a result, a minimum P of the P-type impurity concentration is formed in the floating region 24LL. Therefore, in the floating region 24, the concentration difference of the n-type impurity and the p-type impurity is large. Thereby, the floating region 24 is stably and easily formed. Therefore, when the IGBTs 10 of the first embodiment are mass-produced, the on-state voltage is less likely to vary among the mass-produced IGBTs 10.
Further, when the p-type impurity is implanted to the depth of the bottom body region 26 after the trench gate electrode 48 is formed in this way, the implantation depth of the p-type impurity in the vicinity of the trench gate electrode 48 will vary depending on the shape of the level difference H1 in the upper portion of the trench gate electrode 48. Therefore, the implantation depth of the p-type impurity in the vicinity of the trench gate electrode 48 cannot be controlled so accurately. However, the p-type impurity concentration in the bottom body region 26 near the trench gate electrode 48 has less influence on the on-state voltage or gate threshold voltage of the IGBT 10. Therefore, the variation in the on-state voltage or the gate threshold voltage due to the influence hardly occurs.
Further, when the bottom body region 26 is formed in this way, the displacement portion 26a can be formed in the bottom body region 26. Thus, the following advantages can be obtained. In the IGBT10, the protrusion amount L1 of the trench gate electrode 48 protruding downward from the bottom body region 26 is relatively large. Therefore, holes existing in the drift region 28 in the vicinity of the bottom body region 26 are blocked by the protruding trench gate electrode 48, and are suppressed from moving laterally in the drift region 28. Therefore, a large number of holes accumulate in the drift region 28 in the vicinity of the bottom body region 26. Thereby, the on-state voltage of the IGBT10 decreases. On the other hand, in general, when the protrusion amount of the trench gate electrode is increased, the contact area of the gate insulating film with the drift region will be increased, and the feedback capacitance of the IGBT will be increased. However, in the IGBT10 described above, the displacement portion 26a is formed, so that the contact area between the gate insulating film 42 and the drift region 28 decreases. Therefore, in this IGBT10, although the protrusion amount L1 is large, the feedback capacitance is small. Therefore, the switching loss generated in the IGBT10 of the first embodiment is small.
Further, most of the holes moving from the drift region 28 to the top body region 22 pass through the floating region 24 in the vicinity of the gate insulating film 42 (i.e., in the vicinity of the channel). In the IGBT10 described above, the wide portion 24a of the floating region 24 is formed in the vicinity of the gate insulating film 42. The wide portions 24a prevent holes from moving from the drift region 28 to the top body region 22. Thereby, the on-state voltage of the IGBT10 is further reduced.
In the first embodiment, the floating regions 24, the top body regions 22, and the emitter regions 20 are formed in this order, but the order of forming these regions may be changed arbitrarily. In addition, in the case where the wide portions 24a are not required to be formed in the floating regions 24, the top body regions 22, and the emitter regions 20 may be formed after the trench gate electrodes 48 are formed. In addition, in the case where the emitter region 20 is formed before the trench gate electrode 48 is formed, it is preferable to use arsenic as the n-type impurity for forming the emitter region 20 as described above. This is because arsenic is hard to thermally diffuse, and therefore can remain in the target region even if heat is applied at the time of formation of the trench gate electrode 48. Instead of arsenic, phosphorus can also be used to form the emitter region 20. In this case, since phosphorus is easily thermally diffused, it is preferable to form the emitter region 20 after forming the trench gate electrode 48. In the first embodiment, phosphorus is used as the n-type impurity for forming the floating region 24, but arsenic may be used instead of phosphorus.
Further, in the first embodiment described above, the wide large portion 24a is formed in the floating region 24 by forming the gate insulating film 42 after forming the floating region 24 and the top body region 22. However, the wide portion may be formed in the floating region 24 by the following method. In this method, first, the above-mentioned steps S2 to S4 are performed. Next, as shown in fig. 19, a mask 102 is formed on the upper surface of the semiconductor substrate 100, and the mask 102 is provided with an opening in a region where the trench 40 is formed. Then, an n-type impurity is implanted into the floating region 24 through the mask 102, and the implanted n-type impurity is diffused and activated. Thereby, as shown in fig. 20, the wide width part 24b is formed. After that, trench gate electrode 48 is formed so as to penetrate wide portion 24b, and other necessary steps are performed, thereby completing the IGBT shown in fig. 21.
Further, in the first embodiment described above, the trench gate electrode 48, the emitter region 20, and the top body region 22 are arranged on the upper surface of the semiconductor substrate in the manner shown in fig. 2. However, these portions may be configured in the manner shown in fig. 22 or 23.
In addition, since the floating region 24 is formed in the first embodiment in such a manner that the n-type impurity concentration reaches the maximum at the upper end of the semiconductor substrate 100 as shown in fig. 8, the n-type impurity concentration reaches the maximum at the upper end of the semiconductor substrate 100 even in fig. 4 (impurity concentration distribution at the line B-B of fig. 1). However, when the average stop position of the n-type impurity described above is slightly deeper than that in the first embodiment, the impurity concentration at the B-B line will be as shown in fig. 24. That is, the maximum value N of the N-type impurity concentration is formed within the depth range of the emitter region 20LH. Thus, even in the emission area 20, a maximum value N of the N-type impurity concentration is formedLHThis is not a problem as long as the top body region 22 and the floating region 24 on the lower side of the emitter region 20 do not have the maximum value of the n-type impurity concentration. This is because the implantation depth of the n-type impurity is shallow within the depth range of the emitter region 20, and therefore, the problem of OSF or the like does not occur. Similarly, as shown in fig. 25, the maximum value P of the P-type impurity concentrationLH2May also be present within the depth of the emitter region 20.
Further, as shown in fig. 26, a maximum value N of the N-type impurity concentration may exist in the emitter region 20LH2. Further, as shown in FIG. 27, the minimum value P of the P-type impurityLLThe N-type impurity concentration N of the drift region 28 may be higher thanL. Further, fig. 28 is a diagram in which the concentration distribution of the impurity injected in steps S2, S4, S6, S14 is plotted by dividing into each step. As shown in fig. 28, a part of the p-type impurity implanted in step S14 may also be distributed within the emitter region 20. For example, as shown in fig. 28, the N-type impurity concentration at the intersection C1 between the graph of the p-type impurity concentration implanted in step S14 and the graph of the N-type impurity concentration implanted in step S6 may also be greater than the N-type impurity concentration N of the drift region 28L(n-type impurity concentration of the original semiconductor substrate 100).
Further, as shown in fig. 29, a part of the n-type impurity implanted and diffused in step S2 may be distributed to the lower side of the bottom body region 26. That is, the bottom body region 26 may be formed with the concentration NLAnd a region 28a having a higher concentration than the n-type impurity. In this structure, the drift region 28 is formed by the entire n-type region located below the bottom body region including the region 28 a. This structure can be formed by extending the diffusion distance of the n-type impurity implanted in step S2. By extending the diffusion distance of the n-type impurity in this way, the inclination of the n-type impurity concentration distribution in the floating region 24 is reduced, thereby making the n-type impurity concentration distribution approximately flat. Therefore, the floating region 24 can be stably formed, and the variation in the on-state voltage can be further reduced. In addition, by so doingThe diffusion distance of the n-type impurity is extended to lower the n-type impurity concentration in the top body region 22, thereby further reducing the variation of the gate threshold voltage.
(second embodiment)
Next, an IGBT according to a second embodiment will be described. The IGBT according to the second embodiment is configured with each section in substantially the same manner as the IGBT10 according to the first embodiment shown in fig. 1 and 2. However, the IGBT of the second embodiment has an impurity concentration distribution different from that of the IGBT10 of the first embodiment. As shown in fig. 30, in the IGBT according to the second embodiment, the n-type impurity concentration is substantially constant in the top body region 22 and in the floating region 24.
Next, a method for manufacturing the IGBT according to the second embodiment will be described. The IGBT according to the second embodiment is manufactured according to the flowchart of fig. 31. The IGBT according to the second embodiment has substantially the same N-type impurity concentration N as the drift region 28LThe silicon substrate (hereinafter referred to as a base substrate) of (1) is manufactured.
In step S32, as shown in fig. 32, an n-type semiconductor layer 210 having a higher n-type impurity concentration than the base substrate 200 is epitaxially grown on the base substrate 200. Hereinafter, the n-type semiconductor layer 210 is referred to as an epitaxial layer 210. The epitaxial layer 210 and the base substrate 200 are collectively referred to as a semiconductor substrate 300. When step S32 is performed, the impurity concentration in the semiconductor substrate 300 has a distribution as shown in fig. 33. As shown, the n-type impurity concentration in the epitaxial layer 210 becomes substantially constant.
In step S34, as shown in fig. 34, the top body region 22 is formed within the epitaxial layer 210. Here, p-type impurities are ion-implanted into the upper surface of the epitaxial layer 210 under the same conditions as in step S4 described above. That is, the p-type impurity is implanted so that the average stop position of the implanted p-type impurity is in a region near the upper surface of the epitaxial layer 210 (a depth range where the emitter region 20 is formed later). Next, the semiconductor substrate 300 is heat-treated under the same conditions as in step S4 described above, so that the implanted p-type impurity is diffused and activated. Thereby, the top body region 22 is formed within the epitaxial layer 210. Here, the top body region 22 is formed to leave the n-type epitaxial layer 210 on the lower side of the top body region 22. The lower n-type epitaxial layer 210 of the top body region 22 becomes the floating region 24.
In step S36, the emitter region 20 is formed within the epitaxial layer 210 in the same manner as in step S6 described above. In step S38, a trench 40 is formed on the upper surface of the semiconductor substrate 300, the trench 40 penetrating the emitter region 20, the top body region 22, the floating region 24 and reaching the base substrate 200. In step S40, the gate insulating film 42 is formed in the same manner as in step S10 described above. At this time, the wide portion 24a is formed in the floating region 24 in the vicinity of the gate insulating film 42. In step S42, the gate electrode 44 is formed in the same manner as in step S12 described above. After step S42 is performed, the semiconductor substrate 300 is in the state shown in fig. 35.
In step S44, as shown in fig. 36, the bottom body region 26 is formed in the region in contact with the floating region 24 in the base substrate 200. In step S44, the p-type impurity is implanted so that the average stop position of the implanted p-type impurity is within the region (the depth range of the bottom body region 26 to be formed) on the lower side of the floating region 24 under the same conditions as in step S14 described above. Next, the semiconductor substrate 300 is subjected to heat treatment, whereby p-type impurities are diffused and activated. Thus, as shown in fig. 36, the bottom body region 26 is formed. In addition, a displacement portion 26a is formed in the bottom body region 26 due to the influence of the difference in level between the upper surface of the gate electrode 44 and the upper surface of the epitaxial layer 210.
Steps S45, S46, S48 are performed in the same manner as steps S15, S17, S18. This completes the IGBT having the sectional structure shown in fig. 1 and having the impurity concentration distribution shown in fig. 30.
In the IGBT according to the second embodiment, the following advantageous effects are obtained in addition to the advantageous effects obtained by the IGBT10 according to the first embodiment. In the IGBT according to the second embodiment, the floating region 24 is formed by an n-type epitaxial layer 210. In the case where the floating region 24 is formed by epitaxial growth in this way, the n-type impurity concentration of the floating region 24 can be increased as compared with the case where the floating region 24 is formed by diffusion as in the first embodiment. This enables the floating regions 24 to be formed more stably, and thus, variation in on-state voltage between IGBTs during mass production can be further reduced.
In the IGBT according to the second embodiment, as shown in fig. 30, the n-type impurity concentration in the floating region 24 is substantially constant. Even in this case, the variation in the on-state voltage can be reduced. That is, in the IGBT10 of the first embodiment, as shown in fig. 3, the maximum value N of the N-type impurity concentration in the floating region 24FHPresent at the boundary of the top body region 22 and the floating region 24. When the p-type impurity concentration in the vicinity of the boundary changes, the maximum value NFHChanges also occur. Maximum value NFHThe on-state voltage of the IGBT is affected. Therefore, in the IGBT10 according to the first embodiment, the p-type impurity concentration in the vicinity of the boundary is one of the main factors that determine the on-state voltage of the IGBT 10. On the other hand, in the IGBT according to the second embodiment, since the n-type impurity concentration in the floating region 24 is substantially constant, even if the p-type impurity concentration in the vicinity of the boundary changes, the maximum value of the n-type impurity concentration in the floating region 24 does not change. In this way, since the number of factors for determining the on-state voltage in the IGBT according to the second embodiment is reduced, variation in the on-state voltage is less likely to occur between IGBTs in mass production.
In addition, in the second embodiment, the maximum value P of the P-type impurity concentrationLHIs present within the bottom body region 26. However, as shown in fig. 37, the maximum value PLHIt may also exist at the boundary of the floating region 24 and the bottom body region 26, as shown in FIG. 38, a maximum value PLHMay also be present within the floating region 24. In the second embodiment, the maximum value P is set to be the maximum value PLHIs lower compared to the n-type impurity concentration within the floating region 24. However, as shown in fig. 39, the maximum value PLHIt may be the same as the n-type impurity concentration in the floating region 24, and as shown in FIG. 40, the maximum value PLHMay also be higher than within the floating region 24The n-type impurity concentration of (1). In the IGBT according to the second embodiment, the impurity concentration may be distributed as described above with reference to fig. 24 to 28.
In the IGBT according to the second embodiment, each region may be arranged as shown in fig. 22 and 23.
In the first and second embodiments, the IGBT formed on the semiconductor substrate is described, but other semiconductor elements may be formed on the semiconductor substrate. For example, a diode that conducts in the reverse direction to the IGBT may be formed on the semiconductor substrate in addition to the IGBT.
In the first and second embodiments, the heat treatment for diffusing the impurity into the top body region and the heat treatment for diffusing the impurity into the floating region are performed separately, but the impurity diffusion into the floating region and the impurity diffusion into the top body region may be performed by one heat treatment.
Although the embodiments have been described in detail, these are merely examples and do not limit the claims. The technology recited in the claims includes examples of various changes and modifications to the specific examples illustrated above.
The technical elements described in the present specification or drawings are useful for technical purposes by themselves or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or the drawings are techniques for achieving a plurality of objects at the same time, and achieving one of the objects itself has technical usefulness.

Claims (12)

1. An insulated gate bipolar transistor (10) includes a semiconductor substrate (12),
it is characterized by comprising:
an n-type emitter region (20) formed in a range exposed to the upper surface of the semiconductor substrate (12);
a p-type top body region (22) formed on the underside of the emitter region (20);
an n-type floating region (24) formed on the underside of the top body region (22) and separated from the emitter region (20) by the top body region (22);
a p-type bottom body region (26) formed on the underside of the floating region (24) and separated from the top body region (22) by the floating region (24);
a trench (40) formed on the upper surface of the semiconductor substrate (12) and penetrating the emitter region (20), the top body region (22), the floating region (24), and the bottom body region (26);
a gate insulating film (42) covering the inner surface of the trench (40);
a gate electrode (44) disposed inside the trench (40),
wherein,
when a p-type impurity concentration distribution in a top body region (22) and a floating region (24) located on the lower side than an emitter region (20) is viewed in the thickness direction of a semiconductor substrate (12), the p-type impurity concentration decreases from the upper end of the top body region (22) located on the lower side than the emitter region (20) toward the lower side and reaches an extremely small value at a predetermined depth in the floating region (24).
2. The insulated gate bipolar transistor (10) of claim 1,
when the n-type impurity concentration distribution in the floating region (24) is observed along the thickness direction of the semiconductor substrate (12), the maximum value of the n-type impurity concentration does not exist in the floating region (24).
3. The insulated gate bipolar transistor (10) according to claim 1 or 2,
the floating region (24) is formed by an epitaxial layer (210).
4. The insulated gate bipolar transistor (10) according to claim 1 or 2,
when the p-type impurity concentration distribution in the bottom body region (26) is observed along the thickness direction of the semiconductor substrate (12), the bottom body region (26) has a maximum value of the p-type impurity concentration.
5. The insulated gate bipolar transistor (10) according to claim 1 or 2,
the width of the floating region (24) in the thickness direction of the semiconductor substrate (12) is wider at a position in contact with the gate insulating film (42) than at a position away from the gate insulating film (42).
6. The insulated gate bipolar transistor (10) according to claim 1 or 2,
the lower end of the bottom body region (26) is located lower at a position in contact with the gate insulating film (42) than at a position away from the gate insulating film (42).
7. A method of manufacturing an insulated gate bipolar transistor (10), comprising:
a step (S6) for forming an n-type emitter region (20) within a range exposed on the upper surface of the semiconductor substrate (12);
a step (S4) of forming a p-type top body region (22) on the lower side of the depth range of the emitter region (20) by implanting a p-type impurity into the upper surface of the semiconductor substrate so as to stop within the depth range of the emitter region (20) and diffusing the implanted p-type impurity;
a step (S2) of forming an n-type floating region (24) on the lower side of the depth range of the top body region (22) by implanting an n-type impurity into the upper surface of the semiconductor substrate so as to stop within the depth range of the emitter region (20) and diffusing the implanted n-type impurity;
forming a trench (40) in the upper surface of a semiconductor substrate (12), and forming a gate insulating film (42) covering the inner surface of the trench (40) and a gate electrode (44) arranged in the trench (40) (S8, S10, S12);
a step (S16) of forming a p-type bottom body region (26) below the depth range of the floating region (24) by implanting a p-type impurity into the upper surface of the semiconductor substrate (12) so as to stop at a depth below the depth range of the floating region (24) after forming the trench (40), the gate insulating film (42), and the gate electrode (44),
wherein,
after the above steps are performed, the trench (40) is disposed so as to penetrate the emitter region (20), the top body region (22), the floating region (24), and the bottom body region (26),
the top body region (22) and the bottom body region (26) are formed in a manner spaced apart by a floating region (24),
the p-type impurity implanted when forming the top body region (22) diffuses into the floating region (24) below the top body region (22).
8. The manufacturing method according to claim 7,
a step (S4) of forming a top body region (22) and a step (S2) of forming a floating region (24) are performed before the steps (S8, S10, S12) of forming a trench (40), a gate insulating film (42), and a gate electrode (44).
9. The manufacturing method according to claim 7 or 8,
in the step (S16) of forming the bottom body region (26), a p-type impurity is implanted into the semiconductor substrate (12) in a state where the upper surface of the gate electrode (44) is located below the upper surface of the semiconductor substrate (12).
10. A method of manufacturing an insulated gate bipolar transistor (10), comprising:
a step (S32) for growing an epitaxial layer (210) made of an n-type semiconductor on the upper surface of a base substrate (200);
a step (S36) for forming an n-type emitter region (20) within a range exposed on the upper surface of the epitaxial layer (210);
a step (S34) wherein a p-type top body region (22) is formed below the depth range of the emitter region (20) by implanting a p-type impurity into the upper surface of the epitaxial layer (210) so as to stop within the depth range of the emitter region (20) and diffusing the implanted p-type impurity;
forming a trench (40) in the upper surface of the epitaxial layer (210), and forming a gate insulating film (42) covering the inner surface of the trench (40) and a gate electrode (44) disposed in the trench (40) (S38, S40, S42);
a step (S44) of forming a p-type bottom body region (26) in the base substrate (200) by implanting a p-type impurity into the upper surface of the epitaxial layer (210) so as to stop in the base substrate (200) after forming the trench (40), the gate insulating film (42), and the gate electrode (44),
wherein,
after the above steps are performed, an n-type epitaxial layer (210) is left between the top body region (22) and the bottom body region (26) to form a floating region, the trench (40) is disposed so as to penetrate the emitter region (20), the top body region (22), the floating region, and the bottom body region (26),
the top body region (22) and the bottom body region (26) are formed in a manner spaced apart by a floating region (24),
the p-type impurity implanted when forming the top body region (22) diffuses into the floating region (24) below the top body region (22).
11. The manufacturing method according to claim 10,
a step (S34) of forming a top body region (22) is performed before the steps (S38, S40, S42) of forming a trench (40), a gate insulating film (42), and a gate electrode (44).
12. The manufacturing method according to claim 10 or 11,
the epitaxial layer (210) and the base substrate (200) are collectively referred to as a semiconductor substrate (12),
in the step (S44) of forming the bottom body region (26), a p-type impurity is implanted into the semiconductor substrate (12) in a state where the upper surface of the gate electrode (44) is located below the upper surface of the semiconductor substrate (12).
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