JP5261137B2 - Bipolar semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bipolar type semiconductor device for suppressing occurrence of a surge voltage. <P>SOLUTION: An IGBT 100 has an n-type floating region 15 that is provided in a p-type body region 14 and parts the body region 14 in a direction for connecting a base region 13 and an emitter region 16. The ratio of the total number of carriers (the total number of free electrons/the total number of holes) between the total number of free electrons in the floating region 15 and the total number of holes in a body region 14b existing at the side of the base region 13 as compared of the floating region 15 is set to a range for preventing a parasitic thyristor from operating in turn-on. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a bipolar semiconductor device having an insulated gate.

  An IGBT (Insulated Gate Bipolar Transistor) is known as an example of a bipolar semiconductor device having an insulated gate. The IGBT is driven at a low on-voltage by injecting electrons from the n-type emitter region and holes from the p-type collector region, and these electrons and holes undergo conductivity modulation.

  Patent Documents 1 and 2 disclose IGBTs in which an n-type floating region is provided in a p-type body region. The floating region divides the body region in the direction connecting the emitter region and the base region. The floating region forms a potential barrier against holes. As a result, holes are accumulated at a higher concentration in the body region existing on the base region side than the floating region, and a further lower ON voltage can be realized.

Japanese Patent Laid-Open No. 2005-210047 International Publication No. WO2005 / 109521 Pamphlet

  In order to improve the hole accumulation effect, it is desirable to increase the dopant concentration in the floating region. However, it has been found that when the dopant concentration in the floating region is increased, the current increases rapidly immediately after the IGBT is turned on, and a surge voltage is induced by this rapid increase in current. When this rapid current increase is examined in detail, a pnpn parasitic thyristor composed of a p-type collector region, an n-type base region, a p-type body region existing on the base region side, and an n-type floating region is obtained. It turns out that this is the cause. That is, when the dopant concentration in the floating region is increased, immediately after the IGBT is turned on, electrons are injected from the floating region into the body region existing on the base region side, the potential of the body region rises, and the parasitic thyristor operates. Thus, it has been found that the current suddenly increases, and that a surge voltage is induced by this rapid current increase. The present invention was created when the above phenomenon was found for the first time. An object of the present invention is to provide a bipolar semiconductor device in which generation of a surge voltage is suppressed.

  The technique disclosed in this specification is characterized in that the parasitic thyristor is not substantially operated when turned on in order to suppress the surge voltage. The technique disclosed in this specification is characterized by providing a suitable design condition of the floating region so as not to substantially operate the parasitic thyristor. The conventional technology using the floating region is focused on reducing the on-voltage, and the floating region is not designed in consideration of the operation of the parasitic thyristor in order to suppress the surge voltage. The technology disclosed in this specification considers both reduction of on-voltage and suppression of surge voltage, and can provide a very useful effect.

The technology disclosed in this specification is a bipolar semiconductor device having an insulating gate facing a body region of a second conductivity type that separates a base region of a first conductivity type and an emitter region of the first conductivity type. Embodied. The bipolar semiconductor device includes a first conductivity type floating region provided in the body region and dividing the body region in a direction connecting the base region and the emitter region. When the carrier total amount ratio (the value obtained by dividing the first carrier total amount by the second carrier total amount) between the first carrier total amount in the floating region and the second carrier total amount in the body region existing on the base region side from the floating region is turned on. The parasitic thyristor is set in a range that does not substantially operate. The technology disclosed in this specification can be applied to any case where the form of the insulated gate is a trench type or a planar type.
Here, the total amount of carriers refers to the total amount of free electrons or holes in a non-operating state (a state where the semiconductor device is electrically insulated from the outside). For example, when the floating region is n-type, the first total carrier amount in the floating region refers to the total amount of free electrons contained in the floating region in the non-operating state. Specifically, it can be calculated by subtracting the p-type dopant contained therein from the total amount of n-type dopant contained in the floating region. When the body region is p-type, the second carrier total amount of the body region existing on the base region side with respect to the floating region is the amount of holes contained in the body region existing on the base region side with respect to the floating region in the non-operating state. Refers to the total amount. Specifically, it can be calculated by subtracting the n-type dopant contained therein from the p-type dopant contained in the body region existing on the base region side of the floating region. The technology disclosed in this specification can determine that the cause of the surge voltage is a parasitic thyristor, and whether the parasitic thyristor operates can be evaluated by the carrier total amount ratio of the first carrier total amount and the second carrier total amount. It was the first time that I found out. The technology disclosed in this specification is the first to propose that a bipolar semiconductor device in which a parasitic thyristor does not substantially operate can be designed by using this carrier total amount ratio.

  The technology disclosed in this specification has found that a bipolar semiconductor device in which a parasitic thyristor does not substantially operate can be realized by setting the total carrier amount ratio to 1.83 or less. It is confirmed in this specification that the parasitic thyristor does not substantially operate when the carrier total amount ratio is set within this range.

The total carrier ratio is preferably 0.4 or more.
It has been confirmed in this specification that the on-state voltage is significantly reduced when the carrier total amount ratio is set within this range.

  According to the technology disclosed in this specification, a bipolar semiconductor device in which the operation of the parasitic thyristor is suppressed and the surge voltage is suppressed can be provided.

The techniques disclosed in this specification will be summarized.
(First Feature) The insulated gate is an insulated trench gate.
(Second feature) The carrier total amount ratio (first carrier total amount / second carrier total amount) of the first carrier total amount in the floating region and the second carrier total amount in the body region existing on the base region side from the floating region has a lower limit value. It is preferably over 0 and the upper limit is preferably 1.83 or less. The effect of reducing the on-voltage and the effect of suppressing the surge voltage can be obtained.
(3rd characteristic) As for carrier total amount ratio, it is more preferable that a lower limit is 0.4 or more and an upper limit is 1.83 or less. A remarkable reduction effect of on-voltage and a suppression effect of surge voltage can be obtained.

  FIG. 1 schematically shows a perspective view of a main part of the IGBT 100. FIG. 2 schematically shows a longitudinal sectional view corresponding to the line II-II in FIG. FIG. 3 schematically shows a longitudinal sectional view corresponding to the line III-III in FIG. The IGBT 100 is manufactured by introducing a dopant into a silicon single crystal semiconductor substrate 10 using an ion implantation technique.

The IGBT 100 includes a p ⁺ type collector region 11, an n ⁺ type field stop region 12, an n ⁻ type base region 13, a p type body region 14, an n type floating region 15, and an n ⁺ type. Emitter region 16, p ⁺ -type body contact region 17, and insulating trench gate 20.

The collector region 11 is provided on the back surface portion of the semiconductor substrate 10. The collector region 11 is formed by introducing a dopant from the back surface of the semiconductor substrate 10 using an ion implantation technique. Boron is used as the dopant. The collector region 11 is electrically connected to a collector electrode (not shown). In an example of the collector region 11, the peak value of the dopant concentration on the back surface is about 1 × 10 ¹⁸ cm ⁻³ and the thickness T11 is about 0.2 μm.

The field stop region 12 is provided on the collector region 11. The field stop region 12 is formed by introducing a dopant from the back surface of the semiconductor substrate 10 using an ion implantation technique. Phosphorus is used as the dopant. In an example of the field stop region 12, the peak value of the dopant concentration is about 1 × 10 ¹⁷ cm ⁻³ and the thickness T12 is about 0.3 μm. The IGBT 100 of this embodiment is a punch-through (PT) type, but may be a non-punch-through (NPT) type from which the field stop region 12 is removed.

The base region 13 is provided on the field stop region 12. The base region 13 is formed as a remaining portion after various semiconductor regions are formed on the semiconductor substrate 10. For this reason, the dopant concentration of the base region 13 matches the dopant concentration contained in the semiconductor substrate 10, and the profile thereof is constant in the thickness direction. In an example of the base region 13, the dopant concentration is about 1 × 10 ¹⁴ cm ⁻³ and the thickness T13 is about 165 μm.

The body region 14 is provided on the base region 13. The body region 14 is formed by introducing a dopant from the surface of the semiconductor substrate 10 using an ion implantation technique. Boron (B) is used as the dopant. The body region 14 is provided between the base region 13 and the emitter region 16 and separates the two. In an example of the body region 14, the peak value of the dopant concentration at the surface is about 1 × 10 ¹⁷ cm ⁻³ and the thickness T14 is about 4.5 μm.

The floating region 15 is provided in the body region 14. The floating region 15 is formed by introducing a dopant from the surface of the semiconductor substrate 10 using an ion implantation technique. Phosphorus (P) is used as the dopant. The potential of the floating region 15 is not fixed and varies depending on the surrounding potential. In this specification, such a state where the potential is not fixed is referred to as a floating state. The floating region 15 extends between adjacent insulating trench gates 20 and divides the body region 14 in the direction connecting the base region 13 and the emitter region 16 (vertical direction in the drawing). In this embodiment, the body region 14 present on the emitter region 16 side of the floating region 15 is referred to as a first body region 14a, and the body region 14 present on the base region 13 side of the floating region 15 is referred to as the second body region 14b. That's it. The second body region 14b is separated from the first body region 14a by the floating region 15, and is in a floating state. In an example of the floating region 15, the peak value of the dopant concentration is about 1 × 10 ¹⁷ cm ⁻³ , the depth of the peak value is about 2 μm from the surface of the semiconductor substrate 10, and the thickness (or full width at half maximum) T15 is about 0.6 μm. In one example of the first body region 14a, the peak value of the dopant concentration on the surface is about 1 × 10 ¹⁷ cm ⁻³ and the thickness T14a is about 1.6 μm. In an example of the second body region 14b, the peak value of the dopant concentration is about 3 × 10 ¹⁶ cm ⁻³ , the depth of the peak value is about 2.2 μm from the surface of the semiconductor substrate 10, and the thickness T14b is about 2 .3 μm. In the experiment described later, several examples in which the dopant concentration of the floating region 15 is changed are examined in order to evaluate the characteristics related to the on-voltage of the IGBT 100 and the voltage change amount at the turn-on.

The emitter regions 16 are provided in a distributed manner on the surface portion of the semiconductor substrate 10. The emitter region 16 is formed by introducing a dopant from the surface of the semiconductor substrate 10 using an ion implantation technique. Phosphorus is used as the dopant. Arsenic may be used instead of phosphorus. The emitter region 16 has at least a portion in contact with the insulating trench gate 20. As a result, electrons are injected from the emitter region 16 into the base region 13 via the inversion layer on the side surface of the insulating trench gate 20. The emitter region 16 is electrically connected to an emitter electrode (not shown). In one example of the emitter region 16, the peak value of the dopant concentration at the surface is about 1 × 10 ¹⁹ cm ⁻³ and the thickness T16 is about 0.2 μm.

The body contact regions 17 are provided in a distributed manner on the surface portion of the semiconductor substrate 10. The body contact region 17 is formed by introducing a dopant from the surface of the semiconductor substrate 10 using an ion implantation technique. Boron is used as the dopant. The body contact region 17 is electrically connected to an emitter electrode (not shown). In an example of the body contact region 17, the peak value of the dopant concentration on the surface is about 1 × 10 ¹⁹ cm ⁻³ and the thickness T17 is about 0.3 μm. The pattern of the body contact region 17 and the emitter region 16 according to the present embodiment is an example, and may be formed with other patterns as necessary.

  The insulating trench gate 20 includes a gate insulating film 24 made of silicon oxide and a gate electrode portion 22 made of polysilicon covered with the gate insulating film 24. The insulating trench gate 20 extends from the surface of the semiconductor substrate 10 toward the deep part and penetrates the body region 14. The insulating trench gate 20 faces the body region 14 that separates the base region 13 and the emitter region 16. The width W20 of the insulating trench gate 20 is about 1 μm, the gap G20 between adjacent insulating trench gates 20 is about 4 μm, and the protruding depth T20 protruding from the body region 14 into the base region 13 is about 5.5 μm. is there. Although the pattern of the insulating trench gate 20 according to the present embodiment is striped, it may be formed with other patterns as necessary.

  FIG. 4A schematically shows a profile in the depth direction of the dopant concentration in the semiconductor substrate 10. FIG. 4B schematically shows a profile of the carrier concentration in the semiconductor substrate 10 in the depth direction. In addition, the vertical axis | shaft of FIG. 4 (A) and (B) is a logarithm display.

  As shown in FIG. 4A, the profile of the p-type dopant concentration in the body region 14 decreases from the surface toward the deep portion. The profile of the n-type dopant concentration in the floating region 15 has a peak value in the body region 14. The n-type dopant originally contained in the semiconductor substrate 10 exists, and the profile of the n-type dopant concentration is constant in the depth direction.

  As shown in FIG. 4B, the carrier concentration is the difference between the n-type dopant concentration and the p-type dopant concentration. In the region where the n-type dopant concentration is higher than the p-type dopant concentration, the carrier concentration is the concentration of free electrons. In a region where the p-type dopant concentration is higher than the n-type dopant concentration, the carrier concentration is the hole concentration. For this reason, there is no carrier concentration in a region where the n-type dopant concentration and the p-type dopant concentration coincide, for example, in the interface between the floating region 15 and the first body region 14a and in the interface between the floating region 15 and the second body region 14b. Further, the interface between the base region 13 and the second body region 14b has a wide region where no carrier concentration exists due to depletion.

  The IGBT 100 is characterized by including a floating region 15 in the body region 14. The floating region 15 forms a potential barrier against holes. For this reason, when the IGBT 100 is on, holes injected from the collector region 11 on the back surface are accumulated in the second body region 14b at a high concentration. For this reason, the IGBT 100 can be driven with a low on-voltage.

  In order to improve the hole accumulation effect, it is desirable to increase the dopant concentration of the floating region 15. However, when the dopant concentration of the floating region 15 is increased, immediately after the turn-on, the pnpn composed of the p-type collector region 11, the n-type base region 13, the second body region 14b, and the n-type floating region 15 is formed. The parasitic thyristor operates and a sudden current increase occurs, causing a surge voltage. The IGBT 100 is characterized in that the dopant concentration of the floating region 15 is adjusted so that the parasitic thyristor does not substantially operate immediately after being turned on.

  The parasitic thyristor is caused by the fact that immediately after the IGBT 100 is turned on, electrons are injected from the floating region 15 into the second body region 14b, and the potential of the second body region 14b increases. In order to suppress this phenomenon, it is important to make the carrier total amount ratio (total free electron amount / total hole amount) of the total free electron amount in the floating region 15 and the total hole amount in the second body region 14b smaller than a predetermined value. is there.

  FIG. 5 shows the on-voltage of the IGBT 100 and the voltage change at turn-on when the ratio of the total amount of free electrons in the floating region 15 to the total amount of holes in the second body region 14b is changed. The on-voltage is shown on the left scale, and the amount of voltage change at turn-on is shown on the right scale. FIG. 6 is an enlarged view of the results when the carrier total amount ratio is 0-3. The total amount of free electrons and the total amount of holes are obtained by using the profile in the depth direction of the dopant concentration detected by SIMS (Secondary Ionization Mass Spectrometer) as data, and using the following equation (1). The carrier concentration in the direction is calculated, and the total concentration of free electrons in the floating region 15 and the total amount of holes in the second body region 14b are calculated by integrating the carrier concentration in the depth direction using Equation 2 below. In this experiment, several examples in which the carrier total amount ratio is changed are compared. The carrier total amount ratio is changed by changing the dopant concentration introduced into the floating region 15. 5 and 6, the example in which the carrier total amount ratio is “0” is a result when the floating region 15 is not formed. An example in which the total carrier amount ratio is increased is a result when the carrier concentration (free electron concentration) of the floating region 15 is high.

  Here, n (x) is the free electron concentration in the depth direction, p (x) is the hole concentration in the depth direction, and Nfloating (x) is the dopant concentration in the depth direction of the floating region 15. , Nsub (x) is a dopant concentration in the depth direction of the semiconductor substrate 10, and Nbody (x) is a dopant concentration in the depth direction of the body region 14.

As shown in FIGS. 5 and 6, when the floating region 15 is provided, the on-voltage rapidly decreases. When the carrier total amount ratio is 0.4 or more, the on-voltage reduction effect is saturated. When the carrier total amount ratio is 0.4 or more, a remarkable on-voltage reduction effect is obtained. When the carrier total amount ratio is 0.4, the built-in potential generated by the concentration difference between the carrier concentration peak value of the floating region 15 and the carrier concentration peak value of the second body region 14b is 0.732 eV. Further, when the carrier total amount ratio is 0.4, the total amount of free electrons in the floating region 15 is 5.37 × 10 ¹¹ cm ⁻² , and the total amount of holes in the second body region is 1.28 × 10 ¹² cm ^−2. It is.

As shown in FIGS. 5 and 6, the amount of voltage change at turn-on is constant up to the carrier total amount ratio of 1.83, and increases rapidly when the carrier total amount ratio exceeds 1.83. This carrier total amount ratio “1.83” is the point at which the parasitic thyristor operates. When the total carrier ratio is 1.83 or less, there is an inevitable voltage change associated with turn-on, but there is no voltage change associated with the operation of the parasitic thyristor. When the carrier total amount ratio is 1.83, the built-in potential generated by the concentration difference between the carrier concentration peak value of the floating region 15 and the carrier concentration peak value of the second body region 14b is 0.754 eV. In addition, when the carrier total amount ratio is 1.83, the free electron total amount in the floating region 15 is 1.93 × 10 ¹² cm ⁻² and the hole total amount in the second body region is 1.09 × 10 ¹² cm ^−2. It is.

  From the results of FIGS. 5 and 6, if the total carrier ratio exceeds 0 and is 1.83 or less, it is possible to obtain an effect of reducing the on-voltage and a state in which the parasitic thyristor is not substantially operated. That is, if the total carrier ratio exceeds 0 and is equal to or less than 1.83, both the ON voltage reduction effect and the surge voltage suppression effect can be achieved simultaneously. Furthermore, if the carrier total amount ratio is 0.4 or more and 1.83 or less, it is possible to simultaneously achieve both a remarkable reduction effect of the ON voltage and a suppression effect of the surge voltage. Even when manufacturing tolerances are taken into consideration, the lower limit of the carrier total amount ratio is preferably 0.6 or more, and the upper limit is preferably 1.60 or less. More preferably, the lower limit value of the carrier total amount ratio is 0.8 or more, and the upper limit value is 1.40 or less.

(Examination by simulation)
The above experimental results are obtained when the carrier total amount ratio is changed by changing the dopant concentration of the floating region 15 under the condition that the thickness of the floating region 15 and the dopant concentration and thickness of the second body region 14b are constant. It is. For example, the carrier total amount ratio changes even when the thickness of the floating region 15 is changed, when the dopant concentration of the second body region 14b is changed, or when the thickness of the second body region 14b is changed. . In the following simulation, it was verified that the parasitic thyristor can be evaluated only by the carrier total amount ratio as an index that the parasitic thyristor does not substantially operate.

  FIG. 7 schematically shows the relationship between the concentration and thickness of each of the first body region 14a, the floating region 15, and the second body region 14b used in the simulation. FIG. 7A is a simulation example 1, FIG. 7B is a simulation example 2, FIG. 7C is a simulation example 3, and FIG. 7D is a simulation example 4. FIG. 8 specifically shows the sample conditions used in the simulation. Further, in FIG. 8, in simulations 2 to 4, different portions are highlighted with reference to simulation example 1. In the simulation, the dopant concentration in each region is constant in the thickness direction.

In Simulation Example 1, the dopant concentration of the first body region 14a is 2 × 10 ¹⁷ cm ⁻³ , the thickness thereof is 1.7 μm, the thickness of the floating region 15 is 0.4 μm, and the central position (dopant The depth of the concentration peak position is 1.9 μm, the concentration of the second body region 14 b is 1.5 × 10 ¹⁶ cm ⁻³ , its thickness is 2.4 μm, and its center position (dopant concentration) The depth of the peak position is 3.3 μm. In the simulation example 1, the total thickness (total depth) of the first body region 14a, the floating region 15, and the second body region 14b is 4.5 μm. The depth of the insulating trench gate is 5.5 μm, and the depth protruding from the base region (trench protruding amount) is 1.0 μm.

  The simulation example 2 differs from the simulation example 1 in the thickness of the second body region 14b. The simulation example 3 differs from the simulation example 1 in the concentration of the second body region 14b. The simulation example 4 differs from the simulation example 1 in the thickness of the floating region 15.

  FIG. 9 shows the on-state voltage and the amount of voltage change at turn-on when the ratio of the total amount of free electrons in the floating region 15 and the total amount of holes in the second body region 14a is changed in simulation examples 1 to 3. The on-voltage is shown on the left scale, and the amount of voltage change at turn-on is shown on the right scale. In simulation examples 1 to 3, some results of changing the carrier total amount ratio are shown. The carrier total amount ratio is changed by changing the dopant concentration of the floating region 15.

  As shown in FIG. 9, it can be seen that the same results are obtained in any of the simulation examples 1 to 4. That is, since the same result can be obtained by changing any of the dopant concentration and thickness of each of the floating region 15 and the second body region 14b, the characteristics relating to the on-voltage and the amount of voltage change at turn-on are the total carrier amount. It can be seen that the ratio can be evaluated.

  In the results of simulation examples 1 to 4, the carrier total ratio in which the parasitic thyristor operates is different from the experimental result (1.83) related to the IGBT 100 of the above embodiment. This arises from the difference between the actually manufactured IGBT 100 and the simulation. However, the knowledge obtained from the simulation result is that the characteristics relating to the on-voltage and the voltage change amount at the turn-on can be evaluated only by the carrier total amount ratio. Therefore, in the actually manufactured IGBT 100, the results shown in FIG. 5 and FIG. 6 (the total carrier ratio is 1.83) even if the dopant concentration and thickness of the floating region 15 and the second body region 14b are changed. It is presumed that a parasitic thyristor will operate substantially if exceeded. Therefore, it was confirmed that in the bipolar semiconductor device, the parasitic thyristor does not substantially operate if the total carrier ratio is 1.83 or less.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part perspective view of IGBT is shown typically. The longitudinal cross-sectional view corresponding to the II-II line of FIG. 1 is shown typically. The longitudinal cross-sectional view corresponding to the III-III line of FIG. 1 is shown typically. (A) The profile of the thickness direction of the dopant concentration in a semiconductor substrate is shown. (B) The profile of the thickness direction of the carrier concentration in a semiconductor substrate is shown. The on-voltage related to the IGBT and the amount of voltage change at turn-on when the carrier total amount ratio is used as a parameter are shown. FIG. 6 shows a partially enlarged view of FIG. 5. (A) The relationship between the dopant concentration and thickness of Simulation Example 1 is schematically shown. (B) The relationship between the dopant concentration and thickness of Simulation Example 2 is schematically shown. (C) The relationship between the dopant concentration and thickness of Simulation Example 3 is schematically shown. (D) The relationship between the dopant concentration and thickness of Simulation Example 4 is schematically shown. The simulation conditions are specifically shown. The on-voltage and the voltage change amount at turn-on according to each simulation example when the carrier total amount ratio is used as a parameter are shown.

Explanation of symbols

10: Semiconductor substrate 11: Collector region 12: Field stop region 13: Base region 14: Body region 14a: First body region 14b: Second body region 15: Floating region 16: Emitter region 17: Body contact region 20: Insulating trench Gate

Claims (3)

A semiconductor device having an insulated gate facing a body region of a second conductivity type that separates a base region of a first conductivity type and an emitter region of the first conductivity type,
A first conductivity type floating region provided in the body region and dividing the body region in a direction connecting the base region and the emitter region;
In the non-operating state of being electrically insulated from the outside, in a total amount of majority carriers contained the first carrier amount is the total amount of majority carriers included in the floating region to the body region that is present in the base region side than the floating region A bipolar semiconductor device, wherein a carrier total amount ratio divided by a second carrier total amount is 1.83 or less. The first conductivity type is n-type;
The second conductivity type is p-type;
The first carrier total amount is the total amount of free electrons;
The bipolar semiconductor device according to claim 1, wherein the total amount of the second carriers is the total amount of holes. 3. The bipolar semiconductor device according to claim 1 , wherein the carrier total amount ratio is 0.4 or more.

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