CN103839816A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103839816A
CN103839816A CN201210483608.5A CN201210483608A CN103839816A CN 103839816 A CN103839816 A CN 103839816A CN 201210483608 A CN201210483608 A CN 201210483608A CN 103839816 A CN103839816 A CN 103839816A
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CN103839816B (zh
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殷华湘
朱慧珑
马小龙
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种半导体器件，包括：衬底上沿第一方向延伸的多个鳍片，沿第二方向延伸并且跨越了每个鳍片的栅极，位于栅极两侧的鳍片上的源漏区以及栅极侧墙，其中，鳍片的顶部和/或侧壁上具有表面层。依照本发明的半导体器件及其制造方法，在鳍片顶部以及侧壁选择性外延生长形成了高迁移率材料层，有效提高了沟道区载流子迁移率，有效提高了器件的性能和可靠性。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件及其制造方法，特别是涉及一种能有效提高载流子迁移率的三维多栅FinFET及其制造方法。
背景技术
在当前的亚20nm技术中，三维多栅器件(FinFET或Tri-gate)是主要的器件结构，这种结构增强了栅极控制能力、抑制了漏电与短沟道效应。
例如，双栅SOI结构的MOSFET与传统的单栅体Si或者SOI MOSFET相比，能够抑制短沟道效应(SCE)以及漏致感应势垒降低(DIBL)效应，具有更低的结电容，能够实现沟道轻掺杂，可以通过设置金属栅极的功函数来调节阈值电压，能够得到约2倍的驱动电流，降低了对于有效栅氧厚度(EOT)的要求。而三栅器件与双栅器件相比，栅极包围了沟道区顶面以及两个侧面，栅极控制能力更强。进一步地，全环绕纳米线多栅器件更具有优势。
现有的FinFET结构以及制造方法通常包括：在体Si或者S0I衬底中刻蚀形成多个平行的沿第一方向延伸的鳍片和沟槽；在沟槽中填充绝缘材料形成浅沟槽隔离(STI)；在鳍片顶部以及侧壁沉积通常为氧化硅的较薄(例如仅1～5nm)假栅极绝缘层，在假栅极绝缘层上沉积通常为多晶硅、非晶硅的假栅极层；刻蚀假栅极层和假栅极绝缘层，形成沿第二方向延伸的假栅极堆叠，其中第二方向优选地垂直于第一方向；在假栅极堆叠的沿第一方向的两侧沉积并刻蚀形成栅极侧墙；刻蚀栅极侧墙的沿第一方向的两侧的鳍片形成源漏沟槽，并在源漏沟槽中外延形成源漏区；在晶片上沉积层间介质层(ILD)；刻蚀去除假栅极堆叠，在ILD中留下栅极沟槽；在栅极沟槽中沉积高k材料的栅极绝缘层以及金属/金属合金/金属氮化物的栅极导电层。
另一方面，随着器件尺寸减小，驱动能力受到较大限制。一种可行的方案是采用硅之外的材料，例如Ge、GaAs、InP、GaSb、InAs、InSb等，在这些材料中，载流子-电子或者空穴的迁移率明显大于硅材料中的速率，使得器件驱动能力显著提高，可有效提高器件性能。
上述这些高迁移率材料膜层通常是在硅衬底上外延形成很厚的体层，或者在具有浅沟槽隔离等隔离结构的硅衬底上选择性外延形成仍较厚的膜层。这些高迁移率材料层的形成工艺难以与常用的CMOS标准工艺兼容，并且与CMOS工艺中目前主流的高k栅介质(HK)/金属栅极(MG)的后栅工艺兼容性差。此外，较厚的高迁移率膜层还存在缺陷多，性能不稳定、可靠性差的问题。
发明内容
由上所述，本发明的目的在于克服上述技术困难，提出一种新的FinFET结构及其制造方法，能有效提高鳍片沟道区的载流子迁移率，从而有效提高器件性能和可靠性。
为此，本发明提供了一种半导体器件制造方法，包括：在衬底上形成沿第一方向延伸的多个鳍片；在鳍片上形成沿第二方向延伸的假栅极堆叠结构；在假栅极堆叠结构沿第一方向的两侧形成栅极侧墙和源漏区；去除假栅极堆叠结构，形成栅极沟槽；在鳍片顶部和/或侧壁上形成表面层；在栅极沟槽中形成栅极堆叠结构。
其中，表面层包括高迁移率材料。
其中，高迁移率材料包括Ge、GaAs、InP、GaSb、InAs、InSb、SiGe、Si:C、SiGe:C、应变硅(Strained-Si)、GeSn、GeSiSn及其组合。
其中，表面层为多层结构。
其中，形成栅极侧墙和源漏区的步骤进一步包括：以栅极侧墙为掩模，刻蚀鳍片，形成源漏沟槽；在源漏沟槽中外延生长形成抬升源漏区。
其中，形成表面层的步骤进一步包括：刻蚀鳍片顶部和/或侧壁形成凹进；在凹进中选择性外延生长形成表面层。
其中，形成表面层之后进一步包括在栅极沟槽中形成界面层。
本发明还提供了一种半导体器件，包括：衬底上沿第一方向延伸的多个鳍片，沿第二方向延伸并且跨越了每个鳍片的栅极，位于栅极两侧的鳍片上的源漏区以及栅极侧墙，其中，鳍片的顶部和/或侧壁上具有表面层。
其中，表面层包括高迁移率材料，高迁移率材料包括Ge、GaAs、InP、GaSb、InAs、InSb、SiGe、Si:C、SiGe:C、应变硅(Strained-Si)、GeSn、GeSiSn及其组合。
其中，表面层为多层结构。
依照本发明的半导体器件及其制造方法，在鳍片顶部以及侧壁选择性外延生长形成了高迁移率材料层，有效提高了沟道区载流子迁移率，有效提高了器件的性能和可靠性。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1A和图1B为依照本发明的FinFET制造方法步骤的剖面示意图；
图2A和图2B为依照本发明的FinFET制造方法步骤的剖面示意图；
图3A和图3B为依照本发明的FinFET制造方法步骤的剖面示意图；
图4A和图4B为依照本发明的FinFET制造方法步骤的剖面示意图；
图5A和图5B为依照本发明的FinFET制造方法步骤的剖面示意图；以及
图6A和图6B为依照本发明的FinFET制造方法步骤的剖面示意图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果，公开了有效提高了沟道区载流子迁移率、提高了器件的性能和可靠性的三维多栅FinFET及其制造方法。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
值得注意的是，以下某图A是沿垂直于沟道方向(沿第二方向)的剖视图，某图B是沿平行于沟道方向(沿第一方向)的剖视图。
参照图1A以及图1B，形成沿第一方向延伸的多个鳍片结构，其中第一方向为未来器件沟道区延伸方向。提供衬底1，衬底1依照器件用途需要而合理选择，可包括单晶体硅(Si)、单晶体锗(Ge)、应变硅(Strained Si)、锗硅(SiGe)，或是化合物半导体材料，例如氮化镓(GaN)、砷化镓(GaAs)、磷化铟(InP)、锑化铟(InSb)，以及碳基半导体例如石墨烯、SiC、碳纳管等等。出于与CMOS工艺兼容的考虑，衬底1优选地为体Si。光刻/刻蚀衬底1，在衬底1中形成多个沿第一方向平行分布的沟槽1G以及沟槽1G之间剩余的衬底1材料所构成的鳍片1F。沟槽1G的深宽比优选地大于5∶1。在鳍片1F之间的沟槽1G中通过PECVD、HDPCVD、RTO(快速热氧化)、旋涂、FlowCVD等工艺沉积填充材质例如为氧化硅、氮氧化硅、氢氧化硅、有机物等的绝缘隔离介质层，从而构成了浅沟槽隔离(STI)2。
参照图2A以及图2B，在鳍片1F上形成假栅极堆叠结构3/4以及栅极侧墙5，并在栅极侧墙5两侧形成源漏区1S/1D。
在晶片衬底上沉积假栅极绝缘层3和假栅极层4。通过LPCVD、PECVD、HDPCVD、RTO、MBE、ALD、MOCVD、蒸发、溅射等常规方法，依次在衬底1上沉积假栅极绝缘层3和假栅极层4，使得假栅极绝缘层3覆盖了STI2的顶部、鳍片1F顶部和侧壁，假栅极层4覆盖假栅极绝缘层3。假栅极绝缘层3厚度例如仅1～5nm并优选1～3nm，其材质例如是氧化硅。假栅极层4材质例如是多晶硅、非晶硅、非晶锗、非晶碳、SiGe、Si:C及其组合，其厚度例如为20～500nm。此外，以上各层的厚度不必按照图示的比例，而是根据具体的器件尺寸以及电学性能需求而合理设定
随后，平坦化假栅极层4以消除鳍片1F顶部处的突起，避免线条在后续刻蚀过程中失真。例如，采用化学机械抛光(CMP)或者回刻(etch-back)技术，平坦化假栅极层4，消除顶部的突起。
之后，图案化假栅极层4和假栅极绝缘层3，形成假栅极堆叠。可以在假栅极层4上涂覆光刻胶形成软掩模、或者沉积并刻蚀形成氮化硅等材质的硬掩模(均未示出)，以软/硬掩模为掩模，刻蚀假栅极层4和假栅极绝缘层3，形成沿第二方向延伸的假栅极堆叠4/3。其中，刻蚀可以是湿法刻蚀，例如采用TMAH针对硅材质的假栅极层4、稀释的缓释刻蚀剂(dBOE)或者稀释氢氟酸(dHF)针对氧化硅材质的假栅极绝缘层3；刻蚀也可以是干法刻蚀，例如采用等离子体刻蚀、反应离子刻蚀(RIE)，刻蚀气体可以是碳氟基气体、氯基气体，并且可以增加氧气等氧化性气体以及惰性气体以调节刻蚀速率。
接着，在假栅极堆叠4/3沿第一方向的两侧形成栅极侧墙5。在假栅极堆叠上，通过LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD等方法沉积氮化硅、非晶碳、DLC等材料及其组合，并采用湿法或者干法刻蚀，形成栅极侧墙5。在本发明一个实施例中，刻蚀方法是RIE。
之后，以栅极侧墙5为掩模，刻蚀鳍片1F形成源漏沟槽，并在源漏沟槽中外延生长形成抬升的源漏区1S与1D。在本发明一个实施例中，采用各向异性的刻蚀方法沿栅极侧墙5的两侧向下刻蚀鳍片1F，直至抵达鳍片1F与衬底1之间的界面，也即STI2的顶部，形成具有垂直侧壁的源漏区凹槽(未示出)。在本发明的其他实施例中，可以继续采用各向同性的刻蚀方法横向刻蚀源漏区凹槽的垂直侧壁，在鳍片1F的顶部的侧面以及下方形成朝向沟道区凹进的源漏区凹槽，优选地互相穿通从而使得鳍片1F的顶部部分地或者完全与衬底1分离，从而提供良好绝缘隔离。横向凹进的源漏区凹槽的截面形状依照需要可以是∑形(多段折线构成)、梯形、倒梯形、三角形、D形(曲面的一半，曲面例如为圆球面、椭圆球面、双曲面、马鞍面等等)、C形(曲面的大部分，超过曲面的一半，其中曲面例如为圆球面、椭圆球面、双曲面、马鞍面等等)、矩形等。在上述形成的垂直或者具有凹进部分的源漏沟槽中，通过UHVCVD、MOCVD、ALD、MBE、常压外延等外延生长工艺，在上述源漏凹槽中外延生长了嵌入式的源漏区1S和1D，源漏区1S/1D之间(沿第一方向)的鳍片1F的顶部构成器件的沟道区。对于PMOS而言，源漏区1S/1D可以是SiGe、SiSn、GeSn、Si等及其组合，从而向沟道区施加压应力，提高空穴迁移率；而对于NMOS而言，源漏区1S/1D可以是Si:C、Si:H、SiGe:C、Si等及其组合，从而向沟道区施加张应力，提高电子迁移率。其中，如图2B所示，源漏区1S/1D顶部高于鳍片1F的沟道区(因此构成提升源漏，可以有效降低接触电阻)并且低于假栅极层4的顶部，这种配置仅出于示意目的，因此顶部高度差可以任意设定。优选地，在外延生长源漏区的同时可以进行原位掺杂，以改变源漏区导电类型和浓度。此外，可以在外延生长之后进行源漏离子注入。掺杂方法为外延之后的离子注入、多角度离子注入，等离子体掺杂，分子层或者原子层沉积掺杂。掺杂深度可以是包覆源漏鳍片的表面掺杂，也可以是体掺杂。依照MOSFET类型而调整源漏区的导电类型，例如对于NMOS而言掺杂磷P、砷As、锑Sb等，对于PMOS而言掺杂硼B、铝Al、镓Ga、铟In等。随后可以退火以激活上述各种掺杂剂。优选地，在源漏区顶部形成金属硅化物以降低源漏接触电阻。
参照图3A和图3B，在晶片衬底上形成层间介质层(ILD)6以及栅极沟槽6G。ILD 6的材质例如是氧化硅、氮氧化硅或低k材料，低k材料包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、BSG、PSG、BPSG)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)，形成方法包括旋涂、喷涂、丝网印刷、CVD沉积等方法。
采用刻蚀工艺去除假栅极堆叠4/3，在ILD 6中留下栅极沟槽6G。其中，刻蚀可以是湿法刻蚀，例如采用TMAH针对硅材质的假栅极层4、稀释的缓释刻蚀剂(dBOE)或者稀释氢氟酸(dHF)针对氧化硅材质的假栅极绝缘层3；刻蚀也可以是干法刻蚀，例如采用等离子体刻蚀、反应离子刻蚀(RIE)，刻蚀气体可以是碳氟基气体、氯基气体，并且可以增加氧气等氧化性气体以及惰性气体以调节刻蚀速率。
参照图4A和图4B，刻蚀鳍片1F表面，使得鳍片1F顶部以及侧壁形成凹进1R。针对鳍片1F的材质，可以选用湿法或者干法刻蚀。对于硅材质的鳍片1F而言，可以选用TMAH、KOH湿法腐蚀，并调节温度和浓度，使得基本各向同性刻蚀。也可以采用碳氟基、氯基气体等离子体干法刻蚀，调整刻蚀气体比例使得基本上各向同性刻蚀。凹进1R的深度(宽度或者厚度)优选地小于鳍片1F自身厚度(沿水平方向、第一方向上的宽度)的1/4并优选地大于鳍片1F自身厚度的1/10。
参照图5A和图5B，在鳍片1F的凹进1R处选择性外延生长，形成高迁移率材料构成的表面层7。表面层7的材质是高迁移率材料，例如Ge、GaAs、InP、GaSb、InAs、InSb、SiGe、Si:C、SiGe:C、应变硅(Strained-Si)、GeSn、GeSiSn等及其组合。虽然图中所示层7为单层，但是实际上可以依照晶格匹配需要沉积多个高迁移率层，例如Si-SiGe-SiGe:C、Si-SiGe-GaAs-InAs、Si-SiGe-GeSn等等。值得注意的是，表面层7材质不限于上述具体示例，只要表面层7中载流子迁移率大于鳍片1F的(硅)材料中载流子迁移率即可实现本发明技术方案，达到本发明技术效果。表面层7的形成方法可以是PECVD、HDPCVD、MOCVD、UHCVD、MBE、ALD等。表面层7的厚度以填充鳍片1F表面凹进1R直至齐平为准，也即剩余鳍片1F与表面层7的厚度(宽度)之和等于图1中原始鳍片1F的厚度(宽度)。优选地，形成表面层7之后，采用化学氧化方法(例如在含有10ppm臭氧的去离子水中浸泡20s)以生成极薄的氧化物构成的界面层(未示出)，以便减小未来沟道区(表面层7以及下方的鳍片1F的顶部)与高k材料的栅极绝缘层之间的界面缺陷。
值得注意的是，图4以及图5采用先刻蚀形成凹进然后沉积的方式形成表面层，仅是为了保持鳍片的小尺寸。实际上，也可以不经过刻蚀形成凹进，而直接在鳍片顶部以及侧壁沉积形成表面层，如此稍微增大了器件的线条宽度。
参照图6A和图6B，在栅极沟槽中形成栅极堆叠。在栅极沟槽中依次沉积高k材料的栅极绝缘层8以及金属/金属合金/金属氮化物材料的栅极导电层9，构成栅极堆叠结构。之后，可以采用现有工艺完成器件制造，例如包括：CMP平坦化栅极堆叠结构直至暴露ILD 6；在ILD 6中刻蚀源漏接触孔(未示出)直达源漏区1S/1D，在源漏接触孔中沉积金属氮化物的阻挡层以及金属材料的导电层，形成源漏接触塞(未示出)。
最后形成的器件结构的立体图如图6A和6B所示，包括：衬底上沿第一方向延伸的多个鳍片，沿第二方向延伸(与第一方向相交并且优选地垂直)并且跨越了每个鳍片的栅极，位于栅极两侧的鳍片上的源漏区以及栅极侧墙，其中，鳍片顶部和/或沿第二方向的侧壁上具有高迁移率材料的表面层。上述这些结构的材料和几何形状已在方法描述中详述，因此在此不再赘述。
依照本发明的半导体器件及其制造方法，在鳍片顶部以及侧壁选择性外延生长形成了高迁移率材料层，有效提高了沟道区载流子迁移率，有效提高了器件的性能和可靠性。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (10)

1.一种半导体器件制造方法，包括：
在衬底上形成沿第一方向延伸的多个鳍片；
在鳍片上形成沿第二方向延伸的假栅极堆叠结构；
在假栅极堆叠结构沿第一方向的两侧形成栅极侧墙和源漏区；
去除假栅极堆叠结构，形成栅极沟槽；
在鳍片顶部和/或侧壁上形成表面层；
在栅极沟槽中形成栅极堆叠结构。
2.如权利要求1的方法，其中，表面层包括高迁移率材料。
3.如权利要求2的方法，其中，高迁移率材料包括Ge、GaAs、InP、GaSb、InAs、InSb、SiGe、Si:C、SiGe:C、应变硅(Strained-Si)、GeSn、GeSiSn及其组合。
4.如权利要求2的方法，其中，表面层为多层结构。
5.如权利要求1的方法，其中，形成栅极侧墙和源漏区的步骤进一步包括：
以栅极侧墙为掩模，刻蚀鳍片，形成源漏沟槽；
在源漏沟槽中外延生长形成抬升源漏区。
6.如权利要求1的方法，其中，形成表面层的步骤进一步包括：
刻蚀鳍片顶部和/或侧壁形成凹进；
在凹进中选择性外延生长形成表面层。
7.如权利要求1的方法，其中，形成表面层之后进一步包括在栅极沟槽中形成界面层。
8.一种半导体器件，包括：衬底上沿第一方向延伸的多个鳍片，沿第二方向延伸并且跨越了每个鳍片的栅极，位于栅极两侧的鳍片上的源漏区以及栅极侧墙，其中，鳍片的顶部和/或侧壁上具有表面层。
9.如权利要求8的半导体器件，其中，表面层包括高迁移率材料，高迁移率材料包括Ge、GaAs、InP、GaSb、InAs、InSb、SiGe、Si:C、SiGe:C、应变硅(Strained-Si)、GeSn、GeSiSn及其组合。
10.如权利要求8的半导体器件，其中，表面层为多层结构。
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