CN103779297B - 金属凸块接合结构 - Google Patents

金属凸块接合结构 Download PDF

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Publication number
CN103779297B
CN103779297B CN201310055099.0A CN201310055099A CN103779297B CN 103779297 B CN103779297 B CN 103779297B CN 201310055099 A CN201310055099 A CN 201310055099A CN 103779297 B CN103779297 B CN 103779297B
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layer
barrier layer
metal coupling
metal
semiconductor
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CN103779297A (zh
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林俊成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种结构包括具有第一金属凸块的第一半导体芯片和具有第二金属凸块的第二半导体芯片。该结构还包括电连接第一半导体芯片和第二半导体芯片的焊料接合结构，其中焊料接合结构包括位于第一金属凸块和第二金属凸块之间的金属间化合物区域，其中金属间化合物区域具有第一高度尺寸；和沿着第一金属凸块和第二金属凸块的外壁形成的围绕部分，其中围绕部分具有第二高度尺寸，并且第二高度尺寸大于第一高度尺寸。本发明提供了金属凸块接合结构。

Description

金属凸块接合结构
技术领域
本发明涉及半导体器件，具体而言，涉及金属凸块接合结构。
背景技术
由于各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体产业经历了快速发展。大多数情况下，这种集成密度提高源自于最小部件尺寸的不断减小，这允许更多的元件集成在给定的区域内。近来，随着对甚至更小的电子器件的需求的增加，对更小型且更具有创造性的半导体管芯封装技术的需要也在增长。
随着半导体技术进一步发展，已经出现了基于芯片级或芯片尺寸封装的半导体器件，其作为用于进一步减小半导体芯片的物理尺寸的有效替换方式。在基于芯片级封装的半导体器件中，对具有由各种凸块(包括铜凸块和/或焊球等)提供的接触件的管芯生成封装。可以通过应用基于芯片级封装的半导体器件实现高得多的密度。此外，基于芯片级封装的半导体器件可以实现更小的形状因数、成本高效益、增强的性能、更低的功耗和更少的热发生。
发明内容
为了解决现有技术中存在的问题，根据本发明的一方面，提供了一种结构，包括：第一半导体元件，所述第一半导体元件包括：第一金属凸块，形成在所述第一半导体元件的顶面上方；和第一阻挡层，形成在所述第一金属凸块上方；第二半导体元件，所述第二半导体元件包括：第二金属凸块，形成在所述第二半导体元件的顶面上方；和第二阻挡层，形成在所述第二金属凸块上方；以及焊料接合结构，电连接所述第一金属凸块和所述第二金属凸块，其中，所述焊料接合结构包括：金属间化合物区域，形成在所述第一阻挡层和所述第二阻挡层之间，其中，所述金属间化合物区域具有第一高度尺寸；和围绕部分，沿着所述第一金属凸块和所述第二金属凸块的外壁形成，其中，所述围绕部分具有第二高度尺寸，并且所述第二高度尺寸大于所述第一高度尺寸。
在所述的结构中，所述围绕部分具有半椭圆形状；以及所述围绕部分包括：从所述第一阻挡层到所述半椭圆形状的表面的第一距离；和从所述第二阻挡层到所述半椭圆形状的表面的第二距离，并且其中：所述第一距离大于所述第一尺寸；以及所述第二距离大于所述第一尺寸。
在所述的结构中，所述第一阻挡层由镍形成；以及所述第二阻挡层由镍形成。
在所述的结构中，所述金属间化合物区域包含Ni3Sn4。
在所述的结构中，所述第一金属凸块由铜形成；以及所述第二金属凸块由铜形成。
在所述的结构中，所述第一半导体元件是半导体芯片；以及所述第二半导体元件是封装基板。
在所述的结构中，所述第一半导体元件是封装基板；以及所述第二半导体元件是半导体芯片。
在所述的结构中，所述第一半导体元件是第一半导体芯片；以及所述第二半导体元件是第二半导体芯片。
根据本发明的另一方面，提供了一种器件，包括：第一半导体芯片，所述第一半导体芯片包括：第一半导体衬底；第一互连结构，形成在所述第一半导体衬底上方；第一铜凸块，形成在所述互连结构上；和第一阻挡层，位于所述第一铜凸块上方；第二半导体芯片，堆叠在所述第一半导体芯片上，其中，所述第二半导体芯片包括：第二半导体衬底；第二互连结构，形成在所述第二半导体衬底上方；第二铜凸块，形成在所述第二互连结构上方；和第二阻挡层，位于所述第二铜凸块上方；以及焊料接合结构，电连接所述第一铜凸块和所述第二铜凸块，其中，所述焊料接合结构包括：金属间化合物区域，形成在所述第一阻挡层和所述第二阻挡层之间，其中所述金属间化合物区域具有第一高度尺寸；和围绕部分，沿着所述第一铜凸块和所述第二铜凸块的外壁形成，其中所述围绕部分具有第二高度尺寸，并且所述第二高度尺寸大于所述第一高度尺寸。
在所述的器件中，所述第一互连结构包括：形成在所述第一半导体衬底上方的第一金属层；形成在所述第一金属层上的第一介电层；形成在所述第一介电层上的第二金属层；形成在所述第二金属层上方的第一钝化层；形成在所述第一钝化层上方的第二钝化层；嵌入所述第一钝化层和所述第二钝化层中的接合焊盘；形成在所述第二钝化层上的聚合物层；以及形成在所述接合焊盘上的第一铜凸块。
在所述的器件中，所述第一阻挡层由镍形成；以及所述第二阻挡层由镍形成。
在所述的器件中，所述围绕部分具有半椭圆形状。
在所述的器件中，所述金属间化合物区域包含Ni3Sn4。
在所述的器件中，所述金属间化合物区域的高度在约3μm至约5μm的范围内。
在所述的器件中，所述围绕部分的高度在约4μm至约6μm的范围内。
根据本发明的又一方面，提供了一种方法，包括：在第一半导体元件的顶面上方形成第一金属凸块；在所述第一金属凸块上方沉积第一阻挡层；在第二半导体元件的顶面上方形成第二金属凸块；在所述第二金属凸块上方沉积第二阻挡层；以及通过回流工艺将所述第二半导体元件接合在所述第一半导体元件上，其中，熔化焊球以形成焊料接合结构，所述焊料接合结构包括：金属间化合物区域，形成在所述第一阻挡层和所述第二阻挡层之间，其中，所述金属间化合物区域具有第一高度尺寸；和围绕部分，沿着所述第一金属凸块和所述第二金属凸块的外壁形成，其中，所述围绕部分具有第二高度尺寸，并且所述第二高度尺寸大于所述第一高度尺寸。
所述的方法还包括：在所述第一阻挡层上形成所述焊球；以及实施回流工艺以熔化所述焊球从而形成所述焊料接合结构。
所述的方法还包括：在所述第二阻挡层上形成所述焊球；以及实施回流工艺以熔化所述焊球从而形成所述焊料接合结构。
所述的方法还包括：在衬底上方形成第一金属层；在所述第一金属层上形成第一介电层；以及在所述第一介电层上形成第二金属层。在一个实施例中，上述方法还包括在所述第二金属层上方形成第一钝化层；在所述第一钝化层上方形成第二钝化层；形成接合焊盘，其中，所述接合焊盘嵌入所述第一钝化层和所述第二钝化层中；以及在所述第二钝化层上形成聚合物层。
附图说明
为了更全面地理解本发明及其优点，现在将参考结合附图所进行的以下描述，其中：
图1示出根据本发明的各个实施例的半导体器件的截面图；以及
图2详细地示出根据本发明的各个实施例的在图1中示出的半导体芯片的截面图。
除非另有说明，不同附图中的相应标号和符号通常是指相应部件。绘制附图用于清楚地示出各实施例的相关方面而不必按比例绘制。
具体实施方式
在下面详细论述本发明的实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅是制造和使用本发明的说明性具体方式，而不用于限制本发明的范围。
将结合具体环境中的实施例描述本发明，即位于两个半导体管芯之间的界面处的金属凸块接合结构(joint structure)。然而，本发明还可以适用于各种半导体器件的接合结构。在下文中，将参照附图详细说明各个实施例。
图1示出根据本发明各个实施例的半导体器件的截面图。半导体器件100包括第一半导体元件130和第二半导体元件150。如图1所示，通过金属凸块接合结构在第一半导体元件130的顶部上堆叠第二半导体元件150。金属凸块接合结构包括在第一半导体元件130上方形成的第一金属凸块132、在第二半导体元件150上方形成的第二金属凸块152和位于两个半导体元件130和150之间的界面处的焊料接合结构144。应当注意到，虽然图1示出在每个半导体元件(例如，第一半导体元件130)处仅有一个金属凸块(例如，金属凸块132)，但是半导体元件130和150都可以容纳任何数量的金属凸块。
在一些实施例中，半导体元件130和150都是半导体芯片。在可选的实施例中，半导体元件130和150可以是封装基板和/或中介层等。为了简明，在整个说明书中，第一半导体元件130和第二半导体元件150分别被可选地称为第一半导体芯片130和第二半导体芯片150。将在下面参照图2描述第一半导体芯片130和第二半导体芯片150的详细结构。
金属凸块132和152可以由铜形成。图1示出第一金属凸块132和第二金属凸块152都具有矩形形状。应当注意到，图1中示出的金属凸块132和152的形状仅是实例。本领域的技术人员将了解到本发明适用于各种半导体凸块，诸如梯形凸块，其通常也被称为梯形连接件。
如图1所示，分别在金属凸块132和152上方形成阻挡层134和154。阻挡层134和154可以由镍(Ni)、金(Au)、银(Ag)、钯(Pd)、铂(Pt)、镍钯金、镍金、和/或它们的任何组合等形成。可以采用诸如镀层和/或类似技术等合适的制造技术来形成阻挡层134和154。
在将第一半导体芯片130和第二半导体芯片150接合到一起的回流工艺之前，可以在第一半导体芯片130或第二半导体芯片150上形成焊球(未示出)。可选地，可以在一个芯片上形成焊球，而在另一芯片上形成薄焊层(未示出)。
焊球可以由任何合适的材料制成。根据一些实施例，焊球可以包含SAC405。SAC405包含95.5％ Sn、4.0％ Ag和0.5％ Cu。
可以通过任何合适的倒装芯片接合技术将第一半导体芯片130和第二半导体芯片150接合在一起。焊球因而将第一半导体芯片130和第二半导体芯片150连接在一起。实施回流工艺以熔化焊球，从而形成图1中示出的焊料接合结构144。在一些实施例中，可以在约220度至约280度的温度范围下实施回流工艺。
在回流工艺之后，因为焊料(例如，焊球)和镍(例如，由镍形成的阻挡层134和154)之间的冶金反应，在第一金属凸块132和第二金属凸块152之间的界面处形成金属间化合物(IMC)层142。在一些实施例中，IMC层142可以包含Ni3Sn4。如图1所示，焊料接合结构144可以包括两个部分，即IMC部分142和围绕部分146。如通过图1中示出的虚线矩形所示，IMC部分142主要位于第一阻挡层134和第二阻挡层154之间。围绕部分146围绕第一金属凸块132和第二金属凸块152的外壁。
图1示出围绕部分146的截面图。在半导体器件100的俯视图(未示出)中，围绕部分146像是卷绕第一金属凸块132和第二金属凸块152之间的界面的带状物。围绕部分146可以在每个横截面具有一致的厚度。但是，由于工艺和操作变化，围绕部分146的各个横截面的厚度可能是不一致的。假定图1的截面图是在围绕部分146最薄的部分获得的。
如图1所示，IMC层142的高度被定义为H1。第一阻挡层134和焊料接合结构144的外表面之间的水平距离被定义为D1。同样地，第二阻挡层154和焊料接合结构144的外表面之间的水平距离被定义为D2。
从图1中示出的截面图来看，围绕部分146具有半椭圆形状。半椭圆形状的高度被限定为D3。在整个说明书中，半椭圆形状的高度被可选地称为围绕部分146的高度。
为了获得可靠的焊料接合，可以对焊料接合结构144的尺寸进行如下限制。D1与H1的第一比率大于1。同样地，D2与H1的第二比率大于1，并且D3与H1的第三比率大于1。
在一些实施例中，H1在约3μm至约5μm的范围内。D1、D2和D3在约4μm至约6μm的范围内。
进行上面所示的限制的一个优势特征是尺寸限制有助于防止裂纹沿着第一金属凸块132和第二金属凸块152之间的界面蔓延。此外，在可靠性测试(例如，对堆叠的半导体芯片实施的热循环)中可以观察到，采用图1中示出的焊料接合结构144，所得到的堆叠的半导体芯片的可靠性得到了显著提高。
图2详细示出根据本发明的各个实施例的在图1中示出的半导体芯片的截面图。如图1所示，半导体器件100包括第一半导体芯片130和第二半导体芯片150，其中通过焊料接合将第一半导体芯片130连接至第二半导体芯片150。第一半导体芯片130和第二半导体芯片150可以具有相同的结构。为了简明起见，在图2中仅示出第一半导体芯片130的详细结构。
如图2所示，第一半导体芯片130可以包括衬底102和在衬底102上方形成的多个互连元件。衬底102可以由硅形成，然而其还可以由诸如硅、锗、镓、砷和/或它们的组合等其他III族、IV族和/或V族元素形成。
衬底102还可以是绝缘体上硅(SOI)的形式。SOI衬底可以包括在硅衬底中形成的绝缘层(例如，隐埋氧化物等)的上方形成的半导体材料(例如，硅和/或锗等)层。此外，可以使用的其他衬底包括多层衬底、梯度衬底、和/或混合定向衬底等。衬底102还可以包括各种电路(未示出)。在衬底102上形成的电路可以是适合于特定应用的任何类型的电路。
根据一些实施例，电路可以包括各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。可以将电路互连以执行一个或多个功能。功能可以包括存储结构、处理结构、传感器、放大器、功率分布、输入/输出电路等。本领域的普通人员将了解到，上面提供的实例仅用于示出目的以进一步说明本发明的应用而不意味着以任何方式限制本发明。
在衬底102的顶部上形成层间介电层104。例如，层间介电层104可以由诸如氧化硅的低K介电材料形成。可以通过本领域中公知的任何合适的方法，诸如旋涂、化学汽相沉积(CVD)和等离子体增强化学汽相沉积(PECVD)和/或类似方法等形成层间介电层104。还应当注意到，本领域的技术人员将了解到层间介电层104还可以包括多个介电层。
在层间介电层104上方形成底部金属化层106和顶部金属化层108。如图2所示，底部金属化层106包括第一金属线126。同样地，顶部金属化层108包括第二金属线128。金属线126和128由诸如铜或铜合金等金属材料形成。可以通过任何合适的技术(例如，沉积、镶嵌等)形成金属化层106和108。通常，采用一个或多个金属间介电层和相关的金属化层将衬底102中的电路彼此互连以形成功能电路以及进一步提供外部电气连接。
应当注意到，虽然图2示出底部金属化层106和顶部金属化层108，本领域的技术人员将了解到在底部金属化层106和顶部金属化层108之间形成一个或多个金属间介电层(未示出)和相关的金属化层(未示出)。具体而言，底部金属化层106和顶部金属化层108之间的层可以由交替的电介质(例如，极低k介电材料)层和导电材料(例如，铜)层形成。
在顶部金属化层108的顶部上形成介电层110。如图2所示，顶部金属连接件124嵌入介电层110中。具体而言，顶部金属连接件在金属线128和半导体器件的电气连接结构之间提供导电沟道。顶部金属连接件124可以由金属化材料诸如铜、铜合金、铝、银、金和它们的任何组合制成。可以通过合适的技术诸如CVD形成顶部金属连接件124。可选地，可以通过溅射和/或电镀等形成顶部金属连接件124。
在介电层110的顶部上形成第一钝化层112。根据实施例，第一钝化层112由诸如非掺杂的硅酸盐玻璃、氮化硅、氧化硅等非有机材料形成。可选地，第一钝化层112可以由诸如碳掺杂的氧化物等低k电介质形成。此外，极低k(ELK)电介质诸如多孔碳掺杂的二氧化硅可以用于形成第一钝化层112。可以通过诸如CVD和/或类似技术等任何合适的技术形成第一钝化层112。如图2所示，可以在第一钝化层112中形成开口。开口用于容纳接合焊盘116，将在下面对其作详细论述。
在第一钝化层112的顶部上形成第二钝化层114。第二钝化层114可以类似于第一钝化层112，并因此对其不作更详细的论述以避免不必要的重复。如图2所示，在第一钝化层和第二钝化层的开口中形成接合焊盘116。根据一些实施例，接合焊盘116可以由铝形成。为了简明，在整个说明书中，接合焊盘116可以被可选地称为铝焊盘116。
铝焊盘116可以被第一钝化层112和第二钝化层114包围。具体而言，铝焊盘116的底部嵌入第一钝化层112中，而铝焊盘116的顶部嵌入第二钝化层114中。第一钝化层112和第二钝化层114与铝焊盘116的边缘重叠并且密封铝焊盘116的边缘从而通过阻止铝焊盘116的边缘受到侵蚀来提高电稳定性。此外，钝化层112和114可以有助于减少半导体器件的泄漏电流。
在第二钝化层114的顶部上形成聚合物层118。聚合物层118由诸如环氧树脂、聚酰亚胺等聚合物材料制成。具体而言，聚合物层118可以包含光可限定的聚酰亚胺材料，诸如HD4104。为了简明，在整个说明书中，聚合物层118可以被可选地称为PI层118。可以通过本领域中公知的任何合适的方法诸如旋涂和/或类似方法等制造PI层118。如果接合焊盘被重新安置于新的位置，可以在半导体器件100中形成再分布层(未示出)。再分布层在金属线(例如，金属线128)和再分布的接合焊盘之间提供导电路径。再分布层的操作原理为本领域中众所周知的，因而在本文中对其不作详细论述。
图案化PI层118以形成多个开口。此外，在开口的顶部上形成各种凸块下金属(UBM)结构(未示出)。UBM结构用于将铝焊盘(例如，铝焊盘116)与各种输入端子和输出端子(例如，金属凸块132)连接。可以通过任何合适的技术诸如电镀形成UBM结构。根据所需的材料，可以可选地使用其他形成工艺，诸如溅射、蒸发、和/或PECVD等。
在一些实施例中，金属凸块132可以是铜凸块。铜凸块的高度可以为约16μm。可以采用各种半导体封装技术(诸如溅射、电镀和光刻)来形成金属凸块132。如本领域中已知的，为了确保铜凸块和接合焊盘116之间可靠的粘着性和电气连续性，可以在金属凸块132和接合焊盘116之间形成其他层，包括阻挡层、粘着层和晶种层(均未示出)。
尽管已经详细地描述了本发明的实施例及其优点，但应该理解，可以在不背离所附权利要求限定的本发明的主旨和范围的情况下，在此做各种不同的改变、替换和更改。
此外，本申请的范围并不仅限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的发明内容将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与根据本文所述相应实施例基本上相同的功能或获得基本上相同结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求应该在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (20)

1.一种半导体器件的结构，包括：
第一半导体元件，包括：
第一金属凸块，形成在所述第一半导体元件的顶面上方；和
第一阻挡层，形成在所述第一金属凸块的第一平坦表面上而不形成在所述第一金属凸块的侧表面上；
第二半导体元件，包括：
第二金属凸块，形成在所述第二半导体元件的顶面上方；和
第二阻挡层，形成在所述第二金属凸块的第二平坦表面上而不形成在所述第二金属凸块的侧表面上；以及
焊料接合结构，电连接所述第一金属凸块和所述第二金属凸块，其中，所述焊料接合结构包括：
金属间化合物区域，形成在所述第一阻挡层和所述第二阻挡层之间，所述金属间化合物区域由焊料与所述第一阻挡层和/或所述第二阻挡层之间的冶金反应形成，所述金属间化合物区域未与所述第一金属凸块和所述第二金属凸块直接接触，其中，所述金属间化合物区域具有第一高度尺寸；和
围绕部分，沿着所述第一金属凸块和所述第二金属凸块的外壁形成，其中，所述围绕部分具有第二高度尺寸，并且所述第二高度尺寸大于所述第一高度尺寸。
2.根据权利要求1所述的结构，其中：
所述围绕部分具有半椭圆形状；以及
所述围绕部分包括：
从所述第一阻挡层到所述半椭圆形状的表面的第一距离；和
从所述第二阻挡层到所述半椭圆形状的表面的第二距离，并且其中：
所述第一距离大于所述第一高度尺寸；以及
所述第二距离大于所述第一高度尺寸。
3.根据权利要求1所述的结构，其中：
所述第一阻挡层由镍形成；以及
所述第二阻挡层由镍形成。
4.根据权利要求1所述的结构，其中：
所述金属间化合物区域包含Ni3Sn4。
5.根据权利要求1所述的结构，其中：
所述第一金属凸块由铜形成；以及
所述第二金属凸块由铜形成。
6.根据权利要求1所述的结构，其中：
所述第一半导体元件是半导体芯片；以及
所述第二半导体元件是封装基板。
7.根据权利要求1所述的结构，其中：
所述第一半导体元件是封装基板；以及
所述第二半导体元件是半导体芯片。
8.根据权利要求1所述的结构，其中：
所述第一半导体元件是第一半导体芯片；以及
所述第二半导体元件是第二半导体芯片。
9.一种半导体器件，包括：
第一半导体芯片，包括：
第一半导体衬底；
第一互连结构，形成在所述第一半导体衬底上方；
第一铜凸块，形成在所述第一互连结构上；和
第一阻挡层，位于所述第一铜凸块的第一平坦表面上而不位于所述第一铜凸块的侧表面上；
第二半导体芯片，堆叠在所述第一半导体芯片上，其中，所述第二半导体芯片包括：
第二半导体衬底；
第二互连结构，形成在所述第二半导体衬底上方；
第二铜凸块，形成在所述第二互连结构上方；和
第二阻挡层，位于所述第二铜凸块的第二平坦表面上而不位于所述第二铜凸块的侧表面上；以及
焊料接合结构，电连接所述第一铜凸块和所述第二铜凸块，其中，所述焊料接合结构包括：
金属间化合物区域，形成在所述第一阻挡层和所述第二阻挡层之间，所述金属间化合物区域由焊料与所述第一阻挡层和/或所述第二阻挡层之间的冶金反应形成，所述金属间化合物区域未与所述第一铜凸块和所述第二铜凸块直接接触，其中所述金属间化合物区域具有第一高度尺寸；和
围绕部分，沿着所述第一铜凸块和所述第二铜凸块的外壁形成，其中所述围绕部分具有第二高度尺寸，并且所述第二高度尺寸大于所述第一高度尺寸。
10.根据权利要求9所述的半导体器件，其中，所述第一互连结构包括：
形成在所述第一半导体衬底上方的第一金属层；
形成在所述第一金属层上的第一介电层；
形成在所述第一介电层上的第二金属层；
形成在所述第二金属层上方的第一钝化层；
形成在所述第一钝化层上方的第二钝化层；
嵌入所述第一钝化层和所述第二钝化层中的接合焊盘；
形成在所述第二钝化层上的聚合物层；以及
形成在所述接合焊盘上的第一铜凸块。
11.根据权利要求9所述的半导体器件，其中：
所述第一阻挡层由镍形成；以及
所述第二阻挡层由镍形成。
12.根据权利要求9所述的半导体器件，其中：
所述围绕部分具有半椭圆形状。
13.根据权利要求9所述的半导体器件，其中：
所述金属间化合物区域包含Ni3Sn4。
14.根据权利要求9所述的半导体器件，其中：
所述金属间化合物区域的高度在3μm至5μm的范围内。
15.根据权利要求9所述的半导体器件，其中：
所述围绕部分的高度在4μm至6μm的范围内。
16.一种形成半导体器件的方法，包括：
在第一半导体元件的顶面上方形成第一金属凸块；
在所述第一金属凸块的第一平坦表面上而不在所述第一金属凸块的侧表面上沉积第一阻挡层；
在第二半导体元件的顶面上方形成第二金属凸块；
在所述第二金属凸块的第二平坦表面上而不在所述第二金属凸块的侧表面上沉积第二阻挡层；以及
通过回流工艺将所述第二半导体元件接合在所述第一半导体元件上，其中，熔化焊球以形成焊料接合结构，所述焊料接合结构包括：
金属间化合物区域，形成在所述第一阻挡层和所述第二阻挡层之间，所述金属间化合物区域由焊料与所述第一阻挡层和/或所述第二阻挡层之间的冶金反应形成，所述金属间化合物区域未与所述第一金属凸块和所述第二金属凸块直接接触，其中，所述金属间化合物区域具有第一高度尺寸；和
围绕部分，沿着所述第一金属凸块和所述第二金属凸块的外壁形成，其中，所述围绕部分具有第二高度尺寸，并且所述第二高度尺寸大于所述第一高度尺寸。
17.根据权利要求16所述的方法，还包括：
在所述第一阻挡层上形成所述焊球；以及
实施回流工艺以熔化所述焊球从而形成所述焊料接合结构。
18.根据权利要求16所述的方法，还包括：
在所述第二阻挡层上形成所述焊球；以及
实施回流工艺以熔化所述焊球从而形成所述焊料接合结构。
19.根据权利要求16所述的方法，还包括：
在衬底上方形成第一金属层；
在所述第一金属层上形成第一介电层；以及
在所述第一介电层上形成第二金属层。
20.根据权利要求19所述的方法，还包括：
在所述第二金属层上方形成第一钝化层；
在所述第一钝化层上方形成第二钝化层；
形成接合焊盘，其中，所述接合焊盘嵌入所述第一钝化层和所述第二钝化层中；以及
在所述第二钝化层上形成聚合物层。
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US20140110839A1 (en) 2014-04-24
US10083928B2 (en) 2018-09-25
US9559072B2 (en) 2017-01-31
US9112049B2 (en) 2015-08-18
US20150325547A1 (en) 2015-11-12
US20170141067A1 (en) 2017-05-18

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