CN1036666A - 场效应控制的双极型功率半导体器件及其制造方法 - Google Patents

场效应控制的双极型功率半导体器件及其制造方法 Download PDF

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CN1036666A
CN1036666A CN89101864.6A CN89101864A CN1036666A CN 1036666 A CN1036666 A CN 1036666A CN 89101864 A CN89101864 A CN 89101864A CN 1036666 A CN1036666 A CN 1036666A
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弗里德·海姆·鲍尔
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Abstract

在IGT(绝缘栅晶体管)中，用埋在结构中的专 门的金属硅化物导电层使n型区(5c)与n型发射层 的ρ型区(4b)，以及ρ型基极层短路。
n型区(5c)的长度缩短与阴极接触层(8)和栅极 (7)之间的距离无关，使器件实际上不会闭锁。

Description

本发明涉及一种功率半导体器件。特别涉及一种场效应控制双极型功率半导体器件。它包括：
-位于基片中，阳极与阴极之间的P-型发射层、n-型基极层、P-型基极层，和n-型发射层，其中
-P-型基极层，在横向被空隙分隔成彼此隔开的多个单独的P-型区;
-在空隙中，n-型基极层露在基片表面;和
-n-型发射层以单个n-型区形式埋入每个P-型区中，因此，在P-型区（4a、……C）的边缘，和埋入P-型区中的n-型区之间，均是P-型基极层露在基片表面;和
-位于阴极边的，由栅极和阴极接触层交替排列构成的栅极-阴极结构，其中
-每个P-型区上面有一层阴极接触层，该接触层使P-型区所带的全部n-型区成电气连接，并连接这些n-型区之间的P-型区;和
-在相邻的P型区之间的每一个空隙上设置一个用栅绝缘层与基片绝缘的栅电极，该栅电极在相邻P型区的边缘，盖住露在表面的P型基极层。
这样的一种器件已在B.J.Baliga等的文章（IEEE    Jnt.Electron    Dev.Meet.Tech.Dig.，S.264-267，1982）中公开了。
本发明还涉及一种制造该器件的方法。按该方法，首先在基片上制出各层，并在阴极边用栅极绝缘层将整个表面复盖。
电源设备，作为电能生产者与用户之间的中间环节，必须用简单方式控制电源开关。
迄今使用的器件，如GTO或功率BJT，其控制费用均非常昂贵。如GTO的断路就要求有高的栅电流，这就需要设置控制电路。
通常，采用带有绝缘控制电极的器件能理想地简化控制电路，例如功率MOSFET。
但是，带有绝缘控制电极的通用器件的缺点在于，器件中单极电流传输取决于高导通电阻。
近来公开的一种新器件，它兼有双极型功率器件和MOS功率器件的优点（参见本文开始引用的B.J.Baliga等的文章，或J.P.Russel等人的文章，IEEE    Electron    Dev.Lett.EDL-4.S.63-65    1983）。
IGT（绝缘栅晶体管），或IGR，或COMFET，这些器件的结构，除漏区外，与最新的功率MOSFET器件的结构是一致的。在这种器件中，一个P+型掺杂的P-型发射区占据了n-型掺杂漏区的位置。
该区的空穴发射由流过绝缘栅下面的，MOS-反型层沟道的电子激励和控制。按这种方式，低功率的控制和电导率的调节在原理上是一致的。
但是，IGT有一个重大缺点，它的结构是按P-n-P-n的顺序排列的四层掺杂层构成的，因此，器件中存在寄生闸流晶体管结构，由于这一原因，正如所报道的那样（参见Nachad等人的文章，IEEE    Trans，Electron    Dev，ED-32，S    594-598，1985），在临界条件下，IGT中有阳极电流的闭锁趋势（“latch-uP”）。在这种情况下，电流不受栅极控制，使器件在短时间内被烧坏。
防止被烧坏的最有效方法是，设计出消除烧坏过程发生的最佳IGT结构。一个重要的原则是，尽可能减少n型区下面的P型区中的通路电阻。
例如，在B.J.Baliga的文章中（IEEE Electron Dev.Lett.，EDL-5.S.323-325，1984）已提出，在每一个P型区的n型区之间附加一个P+区，防止临界情况出现。
虽然采用这种措施使器件出现闭锁时的电流密度明显增大，但不能完全避免器件闭锁的危险。
本发明的任务是改变IGT的结构，这种结构无论带有附加的P+区或不带附加的P+区均能提高闭锁电流密度，使器件在很大程度上不受闭锁影响。
本发明的任务是用本文一开始所述的方式来完成的，即用一层导电层连接每个阴极接触层，并同所带的n型区之间连接。该导电层在基片表面上穿过阴极接触层和所带的n型区之间。
本发明的出发点同样是减小n型区下面的通路电阻。企图用缩短n型区来降低通路电阻。能实现的n型区的最小范围取决于所用工艺。
n型区的长度（图2中的X3）一方面必须足够大，以确保n型区和P型区短路，另一方面，要根据调整精度使阴极接触层的接触孔和栅电极之间保持最小距离。
就迄今已知的IGT结构而言，在阴极接触层底延伸的n型区可实现的最小长度显然超过2微米。
本发明的核心在于，为确保短路，不再采用一个较长的穿过一个与阴极接触层搭接的大的搭接区的n型区，而是在基片表面设置一个特定的短路导电层。按照这种方式，n型区的长度可以不受上述的最小距离影响而明显缩短。
根据第一个最佳实施例。所说的导电层由金属硅化物构成，所用金属选自钛、钨、钽、和钴金属中的一种金属。采用这种金属硅化物，由于具有较高的电导率，因此接触良好，有高的稳定性和好的工艺兼容性。
根据本发明的另一最佳实施例，栅电极用多晶硅制成，在多晶硅表面同样设置一层金属硅化物导电层。因此这种栅结构的电阻与用单纯多晶硅制成的栅电极电阻相比，降低约1个数量级。从而彻底改善了器件的动态特性。
本发明所述方法的特征工艺步骤如下：
-去掉除栅极下部和边缘区以外的栅极绝缘层;
-将导电层复盖基片的暴露表面;
-n型区和栅电极再复盖一层栅绝缘层;和
-紧接着形成阴极接触层。
根据本发明所述方法的一个最佳实施例，用多晶硅制成栅极，并在制成的多晶硅栅极上同样形成一层金属硅化物为导电层。首先选择钛、钨、钽、钴系列中的一种金属淀积在栅电极的整个表面，紧接着进行热处理，形成相应的金属硅化物。
本发明的其他实施例用从属权利要求给出。
本发明将结合有关附图用实施例作详细说明。
图1.现有技术中IGT结构剖面图（部分）;
图2.图1的部分放大图;
图3A-D.根据本发明的一个实施例制造IGT的各个步骤。
图1所示的现有技术中IGT结构的一部分，已在本文开始所述的B.J.Baliga等人的文章，或J.P.Kussel等人的文章中公开。
在这种通用的结构中，基片1中处于阳极A和阴极K之间的各个掺杂层和它们的范围按层序排列。
各个掺杂层的层序为：一层P+掺杂的P-型发射层2，一层n掺杂的n-型基极层3，一层P掺杂的P-型基极层4和一层n+掺杂的n-型发射层5。
P-型基极层4由空隙10分隔成单个的P-型区4a，……，C。在这些空隙10中，位于下部的n型基极层3在阳极边的基片表面露出。
n型发射层5以单独的n型区5a，……，e的形式埋入每一个P型区4a，……C中。同时，P型基极层4在P型区4a，……，C的边缘和所带的n型区之间，在阴极边的基片表面露出。
阴极边的栅极-阴极结构包括交替放置的栅极7和阴极接触层8。在每个P型区4a，……，C上面都有一个阴极接触层8，该阴极接触层直接与各个P型区中所带的n型区接触，也与这些n型区之间露在表面的P型区接触。
在每个空隙10上部的基片表面设置栅电极7，它用普通的栅绝缘层6，例如SiO2形成的绝缘层与基片电绝缘。栅电极7不仅跨接相应的空隙10，也跨接相邻的P型区，在这些空隙中P型基极层4露在基片表面。
栅电极7与器件的栅极连接。在阳极边，在P型发射层2上形成平面阳极接触层11，与阳极A相连。
此外，每个P型区中的n型区之间还可以设置一个P+型区9，该P+型区通过P型基极层4延伸到n型基极层3中，从而降低器件的闭锁（“latch-up”）趋势。
IGT的工作机理在此无需进一步研究，它在所引用的文章中有详细说明。
已知的IGT结构的缺点从图2所示的单个IGT结构中可以清楚地看到，如本文开始所述，在n型区（5c）下面的P型区（4b）中的通路电阻，对IGT中的寄生闸流晶体管的闭锁起关键性作用。通路电阻越小，器件闭锁趋势就越小。
减小导通区（例如，通过P+区9）的电阻率，或缩短通路均能减小通路电阻。
本发明企图缩短通路。n型区5c的长度X3对通路长度的确定起决定性作用。
n型区长度X3由所采用工艺确定：在IGT中，按现有技术，X3必须足够大，以确保n型区与P基极层短路。这要求n型区与阴极接触层的搭接长为X1（图2）。
另一方面，由于不可避免的调整精度，必须保证阴极接触层8的接触孔与相邻栅电极之间有一个最小距离（图2中的长度X2）。由于有这些先决条件，长度X2显然要超过2微米，而不会再降低。
当不能用不多的费用来减小长度X2时，若按本发明保持长度X1和X2之间的关系，也就是说使n型区无搭接短路，长度X3则会明显下降。
在这种情况下，n型区5c和所带的阴极接触层8之间所必需的电连接是用特制的导电层12（图3D）完成的，导电层在基片表面从n型区5c延伸到阴极接触层8。
导电层12主要由薄层金属硅化物构成，所用金属是钛、钨、钽和钴中的一种。
这种金属硅化物-接触系统已在高度集成化中证明对半导体工艺有兼容性和高稳定性（例如S.J.Lai等的文章所述，IEEE    Trans、Electron    Dev.ED-33.S.345-353    1988）。
按此方法，阴极接触层8和栅极绝缘层6下埋设的导电层12使n型区5c与P型区4b短路。从而使长度X3能达到工艺上能实现的那么短。而且至少可以省去搭接长度X1。并使n型区完全被栅极绝缘层6复盖。
若在多晶硅栅电极7表面附加形成另一层同样的导电层13（图3D），则会有更多的优越性。并使较高的栅极电阻明显下降，器件的动态特性会得到明显改善。
此外，导电层12和13很容易在一个单独的工序中制成。
图3A-D描绘了本发明所述方法一个最佳实施例的各个步骤。
从基片1中已预先经过掺杂的情况开始，形成相应的栅电极（用多晶硅制成），并使栅电极的整个表面复盖一层栅绝缘层6（由按LPCVD法气相沉积的SiO2构成）（图3A）。
本发明与现有技术的差别在于，栅极绝缘层6被各向异性的全平面腐蚀，此时反应离子起蚀刻作用。由于栅电极7的边缘厚度不均匀，因此在此处留下一个绝缘层边缘区;在栅电极7的下面同样获得绝缘层（图3B）。
现在，在结构的整个表面上蒸发或沉积一层金属，蒸发或沉积的金属与硅形成高温稳定的金属硅化物（参见T.P.Chow等人的文章，IEEE    Trans.Electron    Dev.ED-30.S.1480-1497，1983）。适用的金属有钛、钨、钽和钴。
蒸发或沉积金属之后进行热处理形成金属硅化物，热处理温度应使金属硅化物仅在基片和多晶硅栅电极上形成。而不在栅电极边缘处和SiO2绝缘层的边缘区形成金属硅化物。用湿式化学蚀刻工序除去残留的无用金属。图3C给出了制成的结构。在该结构中导电层12、13用X号标示。
为了使硅化物层有尽可能高的电导率，还应在高温下进一步进行热处理。
紧接着使结构按惯用方法继续加工，在沉积SiO2绝缘层之后在该绝缘层上开一个接触孔，最后制成阴极金属化层（阴极接触层8）（图3D）。
将图2与图3D相比，本发明显然有全面的改善：
-高导电率的导电层12使n型区与P型发射区短路。这表明n型区的长度X3可以做到工艺上允许的那么小。同时避免器件闭锁而具有高稳定性。
-由于导电层12具有高导电率，因而不需要较深的n型区，因此可以增大n型区下面的P型发射层4的垂直范围（图2中的长度X4）。这同样有利于降低通路电阻。
-带有n型区的多晶硅栅电极，通常规定，也同样有一层电导率不是特别高的导电层13。栅极电阻可以降低约一个数量级。从而使器件的动态特性有明显改善。
-本发明不仅适用于无P+区的IGT，也适用于带P+区的IGT结构。
最后还应特别指出，本发明不仅适用于有所述层序的器件，也适用于具有互补层序的器件，正如J.P.Kussel等人的文章所述（IEEE    Electron    Dev.Lett，EDL-5.S.437-439、1984）。在这种情况下，可以用相应的n型发射层，P型基极层、n型基极层、P型发射层、n型区和P型区的层序来取代P型发射层、n型基极层、P型基极层、n型发射层、P型区和n型区的层序。
标号说明
1    基片
2    P-型发射层
3    n型基极层
4    P型基极层
4a，…，e    P型区
5    n型发射层
5a，…，e    n型区
6    栅绝缘层
7    栅电极
8    阴极接触层
9 P+型区
10    空隙
11    阳极接触层
12、13    导电层
A    阳极
K    阴极
G    栅极
X1…X4    长度

Claims (10)

1、场效应控制双极型功率半导体器件，它包括：
(a)基片(1)中阳极(A)和阴极(K)之间的一层P型发射层(2)，一层n型基极层(3)，一层P型基极层(4)和一层n型发射层(5)，其中
(aa)P型基极层(4)在横向被彼此隔离的空隙(10)隔离成许多单个的P型区(4a，……，c)；
(bb)在空隙(10)中n型基极层(3)露在基片(1)的表面；和
(cc)n型发射层(5)以单个n型区(5a，……e)的形式埋入每个P型区(4a，……，c)中，因此，P型基极层(4)在P型区(4a，……，c)的边缘和每一个P型区中的n型区之间露在基片(1)的表面；和
(b)阴极边，栅极一阴极结构交替排列成栅电极(7)和阴极接触层(8)，其中，
(aa)每个P型区(4a……，c)上设置一层阴极接触层(8)，该接触层与P型区所带的所有n型区成电气连接，并与这些n型区之间的P型区连接；和
(bb)在相邻P型区之间的每个空隙(10)上设置用栅绝缘层(6)与基片(1)绝缘的栅电极(7)，栅电极复盖在相邻的P型区的边缘露出在表面上的P型基极层(4)；
其特征在于
(c)制造一层导电层(12)使每一层阴极接触层(8)和所带的n型区之间成电连接，该导电层在基片(1)表面上从阴极接触层(8)延伸到所带的n型区。
2、按权利要求1的器件，其特征在于，在每一个P型区的n型区之间总设置一个P+型区，该区从基片（1）的表面穿过P型基极层（4）伸到n型基极层（3）中。
3、按权利要求1或2的器件，其特征在于，导电层（12）由金属硅化物构成。
4、按权利要求3的器件，其特征在于，导电层（12）所用的金属是钛、钨、钽和钴中的一种。
5、按权利要求4的器件，其特征在于，n型区（5a，…，e）用栅绝缘层（6）完全复盖。
6、按权利要求5的器件，其特征在于，栅电极（7）用多晶硅制成，并在多晶硅栅电极上设置一层同样的导电层（13）。
7、制造权利要求1所述器件的方法，在该方法中，首先将基片（1）制成不同的层（2、3、4、5），和区（4a，……，C;5a，……，e），形成栅极（7），并在阴极边完全复盖一层栅绝缘层（6）;
其特征在于：
aa）除去除栅极（7）下面和边缘范围以外的栅绝缘层（6）;
（b）在基片（1）的露出表面上形成导电层（12）;
（c）在n型区（5a，…，e）和栅电极（7）上复盖栅绝缘层（6）;和
（d）紧接着形成阴极接触层。
8、按权利要求7的方法，其特征在于，栅电极（7）用多晶硅制成，并在基片上形成导电层（12）的同时，也在栅电极（7）上形成导电层（13）。
9、按权利要求8的方法，其特征在于，为了形成导电层（12、13），首先选择金属钛、钨、钽和钴中的一种金属沉积在整个表面，紧接着在热处理中形成相应的金属硅化物。
10、按权利要求9的方法，其特征在于：
（a）用SiO2作栅绝缘层（6）;
（b）首先进行热处理，在该温度下，仅在基片（1）的表面和栅电极（7）上，而不是在栅绝缘层的表面形成硅化物;
（c）然后除去栅绝缘层（6）表面上的金属;和
（d）紧接着在较高的温度下继续热处理。
CN89101864.6A 1988-02-22 1989-02-22 场效应控制的双极型功率半导体器件及其制造方法 Pending CN1036666A (zh)

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