CN103635999A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN103635999A
CN103635999A CN201280029271.9A CN201280029271A CN103635999A CN 103635999 A CN103635999 A CN 103635999A CN 201280029271 A CN201280029271 A CN 201280029271A CN 103635999 A CN103635999 A CN 103635999A
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semiconductor chip
electrode
chip
semiconductor device
rewiring
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CN201280029271.9A
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CN103635999B (zh
Inventor
山下裕贵
油井隆
川端毅
萩原清己
横山贤司
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明的半导体装置，在具有电极(20a)以及(20b)的芯片(6)的外缘设置扩展部(1)而成的扩展型半导体芯片(31)上，搭载具有电极(24)的芯片(5)。电极(20a)和电极(24)通过导电构件(8)而电连接。从芯片(6)上的导电构件(8)的配置区域的外侧遍及到扩展部(，1)上而形成有重新布线构造(2)。在扩展部(1)上形成有经由重新布线构造(2)与电极(20b)电连接的连接端子(21)。

Description

半导体装置
技术领域
本公开涉及半导体装置，尤其涉及通过利用芯片叠加(chip-on-chip)技术来层叠芯片而构成的半导体装置。
背景技术
在数字电视、记录器(recorder)等的系统中，伴随高功能化，处理的数据量飞跃增加。因此，不仅搭载于系统的半导体存储器的容量增加，而且要求具有高数据传输速率的半导体存储器。此外，为了将很多半导体存储器搭载于系统，开发了一种安装存储器控制器来使半导体逻辑电路和存储器成为一体的半导体装置。
在使逻辑电路和存储器成为一体的方法中，存在将逻辑电路和存储器集成于1个芯片的系统级芯片(SoC：system-on-chip)、和将逻辑电路芯片与存储器芯片层叠而收纳在1个封装中的系统级封装(SiP：system-in-package)。其中根据SiP，能够均衡地响应系统所要求的、低成本化、高功能化、低耗电化、小型化、轻便化、规格的灵活性等。因此，虽然也取决于系统构成、规格，但总的来说SiP有效的情况不断增加。
SiP根据其构造上的差异，分类为CoC(chip-on-chip，芯片叠加)型、芯片堆叠(chip stack)型、封装层叠型、基板连接型这4个种类。其中，CoC型的SiP具有在半导体芯片上重叠另一个芯片并将各芯片的电路形成面之间彼此连接的构造(例如参照专利文献1)。在此，上下2枚芯片分别在电路形成面具有多个连接用凸起(bump)。该凸起一般远远小于倒装芯片连接用的凸起，被称作微凸起。在CoC型的SiP中，因为能够对上下的各芯片选择最佳的设计、工艺，因此系统构成选择的自由度提高。
此外，在CoC型的SiP中，在利用微凸起对上下的各芯片进行接合时，为了根据CoC连接部(即微凸起)的配置位置来使芯片电极位置最佳化，一般采用在上下各芯片的至少一方对从芯片电极到CoC连接部进行重新布线的构造。
在先技术文献
专利文献
专利文献1：JP特开2010-141080号公报
发明内容
发明要解决的课题
但是，专利文献1中公开的CoC技术，以搭载于上侧的芯片比搭载于下侧的芯片更小型为前提，因此，在因性能制约等导致应搭载于下侧的芯片比上侧的芯片更小型的情况下，专利文献1中公开的CoC技术无法从为了与安装基板电连接而设置于下侧芯片的连接端子，通过引线接合(wirebond)等简易的连接方法物理地引出导电构件。
此外，在专利文献1所公开的CoC技术中，采用了将下侧的芯片上的微凸起(CoC连接部)的周边以及引线接合部等其他连接部的周边全部用抗蚀剂覆盖的构成。在这样的构成中，除了连接部的布线宽度、布线空隙的精度之外，抗蚀剂开口自身的曝光精度等成为制约，难以实施与之前形成的CoC连接部的微细间距化相对应的重新布线。特别是，在下侧的芯片设置有比上侧的芯片更高密度的布线，需要在下侧的芯片进行更微细的重新布线处理的情况下，由于前述的理由，下侧的芯片的连接部及其周边的重新布线的微细化对应变得困难从而存在无法实现CoC型构成的情况。
鉴于上述情况，本公开的目的在于，提供一种对下侧的芯片比上侧的芯片更小的情况以及CoC连接部被微细间距化的情况的任一情况都能够对应的CoC型的SiP。
解决课题的手段
为了达成上述目的，本发明者们想到了如下发明：在CoC型的SiP的安装中，在下侧芯片的外缘设置扩展部而构成扩展型半导体芯片，并且在将上下的各芯片电连接的导电构件的配置区域的外侧在扩展部上侧以及下侧的芯片上设置重新布线构造，由此不经由重新布线构造地将上下的各芯片电连接。
具体来说，本公开所涉及的半导体装置的一个方式，具备：基台，其具有第1电极；第1半导体芯片，其配置在基台上的形成有第1电极的面上，并且具有第2电极；扩展部，其设置为从第1半导体芯片的外缘向外侧方延伸，并且与第1半导体芯片一起构成扩展型半导体芯片；第2半导体芯片，其具有第3电极，并且配置在扩展型半导体芯片上，使得形成有第3电极的面与第1半导体芯片上的形成有第2电极的面相对置；第1导电构件，其将第2电极与第3电极相连接；重新布线构造，其从第1半导体芯片上的第1导电构件的配置区域的外侧遍及到扩展部上而形成；连接端子，其设置在扩展部上，并且经由重新布线构造与第2电极中没有与第1导电构件连接的电极相连接；第2导电构件，其将第1电极与连接端子相连接。
在本公开所涉及的半导体装置中，重新布线构造至少避开第1导电构件的配置区域而配置，由此，重新布线构造也可以在第1导电构件的配置区域具有开口。在此情况下，重新布线构造的开口的中心与第1导电构件的配置区域的中心也可以不一致。此外，重新布线构造的开口，也可以设置为到达扩展型半导体芯片的外周中的1边，也可以设置为到达扩展型半导体芯片的外周中的2边，也可以设置为到达扩展型半导体芯片的外周中的3边，也可以设置为到达扩展型半导体芯片的外周中的4边。此外，重新布线构造的开口，也可以设置为到达第2半导体芯片的外周中的1边的外侧，也可以设置为到达第2半导体芯片的外周中的2边的外侧，也可以设置为到达第2半导体芯片的外周中的3边的外侧，也可以设置为到达第2半导体芯片的外周中的4边的外侧。
在本公开所涉及的半导体装置中，第1导电构件也可以是凸起。
在本公开所涉及的半导体装置中，连接端子也可以是引线接合端子，第2导电构件也可以是引线。
在本公开所涉及的半导体装置中，重新布线构造也可以具有将第1电极与连接端子相连接的重新布线、和覆盖重新布线的层间膜。在该情况下，层间膜也可以由覆盖扩展型半导体芯片的树脂材料构成。此外，树脂材料也可以是感光性树脂材料，感光性树脂材料的分辨率也可以比用于第2半导体芯片的其他感光性树脂材料的分辨率更小。此外，层间膜的至少上部也可以由阻焊剂构成。
在本公开所涉及的半导体装置中，重新布线构造的厚度也可以与扩展型半导体芯片和第2半导体芯片之间的接合间隙实质上相同或小于该接合间隙。
在本公开所涉及的半导体装置中，重新布线的布线宽度以及布线间隔也可以分别大于在第2半导体芯片上形成的其他布线的布线宽度以及布线间隔。
在本公开所涉及的半导体装置中，第2半导体芯片的平面形状也可以大于第1半导体芯片的平面形状，扩展型半导体芯片的平面形状也可以大于第2半导体芯片的平面形状。
此外，本公开所涉及的半导体装置的其他方式，具备：第1半导体芯片，其具有第1电极；扩展部，其设置为从第1半导体芯片的外缘向外侧方延伸，并且与第1半导体芯片一起构成扩展型半导体芯片；第2半导体芯片，其具有第2电极，并且配置在扩展型半导体芯片上，使得形成有第2电极的面与第1半导体芯片上的形成有第1电极的面相对置；导电构件，其将第1电极与第2电极相连接；重新布线构造，其从第1半导体芯片上的导电构件的配置区域的外侧遍及到扩展部上而形成；和连接端子，其设置在扩展部上，并且经由重新布线构造与第1电极中没有与导电构件连接的电极相连接。
发明效果
根据本公开，能够提供一种对下侧的芯片比上侧的芯片更小的情况以及CoC连接部被微细间距化的情况都能够对应的CoC型的SiP。
附图说明
图1是表示实施方式所涉及的半导体装置的剖面图。
图2是对图1的区域A进行放大表示的剖面图。
图3是示意性地表示实施方式所涉及的半导体装置的重新布线构造2的开口的俯视图。
图4(a)～(e)是表示实施方式所涉及的半导体装置的制造方法的各工序的剖面图。
图5(a)～(e)是表示实施方式所涉及的半导体装置的制造方法的各工序的剖面图。
图6(a)～(c)是表示实施方式所涉及的半导体装置的制造方法的各工序的剖面图。
图7(a)～(e)是示意性地表示变形例所涉及的半导体装置的重新布线构造2的开口的俯视图。
图8(a)～(d)是示意性地表示变形例所涉及的半导体装置的重新布线构造2的开口的俯视图。
图9是表示变形例所涉及的半导体装置的剖面图。
具体实施方式
本发明所涉及的半导体装置，以在前述的“解决课题的手段”中描述的构成为基础，能够采用以下所述的各种方式。
(实施方式)
图1表示本实施方式所涉及的半导体装置的剖面构造。此外，图2对图1的区域A进行了放大表示。
如图1以及图2所示，例如从作为逻辑电路芯片的芯片6的外缘向外侧方延伸地设置有例如由树脂构成的扩展部1，由芯片6和扩展部1构成了扩展型半导体芯片31。在芯片6的上表面，形成有与芯片6中的各种元件(图示省略)电连接的多个电极20a、和通过芯片6的内部布线(图示省略)与多个电极20a电连接的多个电极20b。在扩展型半导体芯片31上，具有多个电极24并且搭载有例如作为存储器芯片的芯片5。在此，在扩展型半导体芯片31上层叠有芯片5，使得芯片6中的形成有电极20a的面、与芯片52中的形成有电极24的面相对置。此外，在芯片5中的各电极24上形成有凸起8a，并且在芯片6中的各电极20a上形成有凸起8b，通过凸起8a与凸起8b的连接，从而各电极24与各电极20a被电连接。换言之，各电极24和各电极20a，经由由凸起8a和凸起8b构成的导电构件(CoC连接部)8而电连接。此外，在芯片5的多个电极24中，也可以包括没有与芯片6的电极20a电连接的电极。另一方面，芯片6的多个电极20a存在于导电构件(CoC连接部)8的配置区域。
此外，如图1以及图2所示，在扩展部1上，经由由重新布线22和覆盖该重新布线22的重新布线层间膜18构成的重新布线构造2，形成有多个连接端子21。在此，多个连接端子21通过重新布线构造2(具体来说为重新布线22)与设置于芯片6的多个电极20b电连接。此外，重新布线层间膜18也可以由绝缘性树脂材料构成。
此外，在图2中，示出了芯片6的电极20a、20b从晶片表面露出，但这是为了简化图示，实际上，也可以采用覆盖晶片最上层地形成表面保护膜的通常的晶片工艺。即，在图2所示的构造中，也可以形成包括重新布线层构造2的下方在内、对芯片6表面覆盖并且对电极20a、20b的形成部位进行开口的表面保护膜(未图示)。
作为本实施方式的特征，重新布线构造2从芯片6上的导电构件8的配置区域(即电极20a的配置区域)的外侧遍布扩展部1上而形成。在此，重新布线构造2避开导电构件8的配置区域而配置，由此例如如图3所示，重新布线构造2也可以在导电构件8的配置区域具有开口17a。图3是示意性地表示重新布线构造2的开口的俯视图，在图3中，对与图1以及图2所示的半导体装置相同的构成要素附加相同的符号。
通过如上的重新布线构造2的配置方法，能够不经由重新布线构造2地通过导电构件8将扩展型半导体芯片31(具体来说，是例如作为逻辑电路芯片的下侧的芯片6)、与例如作为存储器芯片的上侧的芯片5进行电连接。
此外，在本实施方式中，作为导电构件8形成了凸起8a以及8b，但导电构件8当然不限于此。此外，作为连接端子21，也可以形成引线接合(wire bonding)用焊盘。在此，在作为导电构件8形成凸起8a以及8b，作为连接端子21形成引线接合用焊盘的情况下，能够应用现有的制造技术容易地形成。
此外，在本实施方式中，在芯片6的周缘形成有扩展部1，使得芯片5的平面尺寸大于芯片6的平面尺寸，另一方面扩展型半导体芯片31的平面尺寸大于芯片5的平面尺寸。因此，扩展型半导体芯片31的各边的长度比芯片5的任意一边的长度长。
此外，在本实施方式中，如图1所示，也可以通过在芯片5与扩展型半导体芯片31之间注入底部填充剂9，来固定芯片5与扩展型半导体芯片31的接合部。
此外，在本实施方式中，如图1所示，将扩展型半导体芯片31和芯片5层叠而成的层叠芯片，也可以通过固晶(dies bond)19固定在树脂基板7上。在此，也可以在树脂基板7的下表面形成封装球(package ball)12。由此，能够进行与半导体装置的外部的电连接。此外，在将扩展型半导体芯片31和芯片5层叠而成的层叠芯片的搭载区域的外侧的树脂基板7的上表面也可以形成多个电极焊盘3。进而，树脂基板7上表面的多个电极焊盘3、与扩展部1上的多个连接端子21，也可以通过引线4电连接。
此外，在本实施方式中，将扩展型半导体芯片31(即芯片6)与芯片5连接的导电构件8(即凸起8a以及8b)的配置间距，也可以比扩展部1上的连接端子21的配置间距更小。此外，扩展部1上的连接端子21的配置间距，也可以比半导体装置的外部端子即封装球12的配置间距更小。
具体来说，为了应对作为存储器芯片的芯片5中的频带增加以及高速化所伴随的多管脚化，对扩展型半导体芯片31和芯片5进行了CoC连接的导电构件8(即凸起8a以及8b)的配置间距，例如，也可以为20μm～50μm之程度。此外，扩展部1上的连接端子21的配置间距，例如，也可以为40μm～200μm之程度，半导体装置的外部端子即封装球12的配置间距，例如，也可以为400μm～1000μm。
此外，在本实施方式中，重新布线22的布线宽度、布线间隔以及布线间距也可以分别比形成在芯片5或芯片6上的布线(图示省略)的布线宽度、布线间隔以及布线间距大。通过这种构成，由于在形成重新布线22时不需要特别应用微细的工艺，因此能够实现工序的简化以及低成本的制造。此外，通过使重新布线22的布线宽度变粗，从而能够在电气上将电感降低，因此能够强化电源以及接地来降低布线噪声。
此外，在本实施方式中，虽然省略了图示，但也可以通过由树脂来密封将扩展型半导体芯片31和芯片5层叠而成的层叠芯片，从而构成CoC型的层叠半导体封装。此外，作为用于搭载将扩展型半导体芯片31和芯片5层叠而成的层叠芯片的机械材料(基台)，也可以取代树脂基板7，而采用例如引线框等。
基于以上说明的本实施方式，在具有CoC构造的半导体封装中，由于在下侧的芯片6的外缘设置扩展部1来构成扩展型半导体芯片31，因此即使在下侧的芯片6比上侧的芯片5更小的情况下，也能够使扩展型半导体芯片31比上侧的芯片5更大。因此通过对扩展型半导体芯片31实施重新布线处理，从而能够确保用于进行与外部的电连接的连接端子区域。具体来说，无需使用特别的半导体工艺，换言之，使用引线接合等简易的连接方法，就能够从为了与树脂基板7的电连接而在扩展型半导体芯片31的扩展部1设置的连接端子21引出导电构件(例如引线4)。因此，能够不受所层叠的芯片5以及6的尺寸的大小关系的制约地，对芯片5以及6进行层叠来构成具有CoC构造的半导体封装。
此外，根据本实施方式，在具有CoC构造的半导体封装中，由于在将上下的各芯片5以及6电连接的导电构件(CoC连接部)8的配置区域的外侧，在扩展部1上以及下侧的芯片6上设置有重新布线构造2，因此能够不经由重新布线构造2地将各芯片5以及6电连接。因此，即使在导电构件(CoC连接部)8被微细间距化的情况下，也不需要相应地将重新布线构造2微细化。因此，能够不受重新布线工艺规则的制约，例如，不受对重新布线22上的绝缘性树脂材料设置开口时的曝光精度等的制约地，利用微细工艺在扩展型半导体芯片31与芯片5之间形成微细的接合构造，来实现芯片面积的缩小，同时构成具有CoC构造的半导体封装。
此外，根据本实施方式，由于芯片6上的电极20a和电极20b通过芯片6的内部布线而电连接，因此能够防止电极20a和电极20b的电连接受到底部填充剂、水分等的影响，因而能够抑制漏电流的产生实现高可靠性。
此外，在图2中，例示了设置有1层重新布线22的重新布线构造2，但在重新布线构造2中也可以形成多层重新布线22。通过将重新布线22设置2层以上，从而能够使布线密度提高来实现高密度的CoC构成。
此外，在本实施方式中，作为覆盖重新布线22的重新布线层间膜18的材料，采用了绝缘性树脂材料，但重新布线构造2中的位于重新布线22上侧的部分，只要是例如阻焊剂(solder resist)、聚酰亚胺等绝缘性树脂材料即可。
在扩展部1上不需要设置微细的布线的情况下，通过使用阻焊剂作为覆盖重新布线22的绝缘性树脂材料，从而能够实现低成本的制造。具体来说，在引线接合部的间距比CoC连接部(连接构件8)宽的情况下，也可以利用阻焊剂等低分辨率的感光性绝缘材料来形成包括该引线接合部在内的扩展部1上的重新布线构造2。换言之，成为覆盖重新布线22的重新布线层间膜18的感光性绝缘材料的分辨率，也可以小于用于芯片5的感光性树脂材料的分辨率。这样一来，能够兼顾微细化和成本。
另一方面，在扩展部1上需要设置微细的布线的情况下，也可以使用例如聚酰亚胺等树脂材料作为覆盖重新布线22的绝缘性树脂材料。
此外，在本实施方式中，图2所示的、扩展型半导体芯片31(芯片6)与芯片5之间的接合间隙13，既可以大于重新布线构造2的厚度，也可以小于重新布线构造2的厚度。在此，在将接合间隙13和重新布线构造2的厚度设定为相同程度的情况下，能够通过重新布线构造2的厚度，容易地进行接合间隙13的高度控制。此外，重新布线构造2的厚度，若与扩展型半导体芯片31和芯片5的接合间隙13为相同程度或小于该接合间隙13，则能够容易地进行芯片5向扩展型半导体芯片31上的搭载。
此外，在本实施方式中，通过引线4对扩展部1上的连接端子21(引线接合用焊盘)和树脂基板7上的电极焊盘3进行了电连接。但是，作为替代，也可以在扩展部1上设置作为通常的电极端子的连接端子21，并经由沿着扩展部1的侧壁面、树脂基板7的上表面而形成的布线，将该连接端子21和树脂基板7上的电极焊盘3电连接。
以下，参照图4(a)～(e)、图5(a)～(e)以及图6(a)～(c)对本实施方式所涉及的半导体装置的制造方法进行说明。此外，在图4(a)～(e)、图5(a)～(e)以及图6(a)～(c)中，对与图1以及图2所示的本实施方式所涉及的半导体装置相同的构成要素附加相同的符号。
首先，如图4(a)所示，从芯片6的外缘向外侧方延伸地形成扩展部1。由此，由芯片6和扩展部1构成扩展型半导体芯片31。在此，在芯片6的上表面，形成有与芯片6中的各个元件(省略图示)电连接的多个电极20a、和通过芯片6的内部布线(图示省略)与多个电极20a电气连接的多个电极20b。
接着，如图4(b)所示，在扩展型半导体芯片31上，覆盖各电极20a以及20b地形成绝缘性树脂层18A。
接着，如图4(c)所示，在利用电极20b的形成区域以及CoC连接部形成区域被开口了的掩膜51进行了曝光之后，如图4(d)所示，选择性地去除绝缘性树脂层18A中的感光区域。
接着，如图4(e)所示，在包括残留的绝缘性树脂层18A上在内的扩展型半导体芯片31上形成了重新布线种子层23之后，如图5(a)所示，在重新布线种子层23上涂敷抗蚀剂50。
接着，如图5(b)所示，在利用CoC连接部形成区域被开口的掩膜52进行了曝光之后，如图5(c)所示，选择性地去除抗蚀剂50中的非感光区域。
接着，如图5(d)所示，在通过残留的抗蚀剂50覆盖了CoC连接部形成区域的状态下，在重新布线种子层23上进行镀敷生长，由此形成了与电极20b连接的重新布线22，之后，如图5(e)所示，去除抗蚀剂50以及在其下方残留的重新布线种子层23。
接着，如图6(a)所示，在包括重新布线22上在内的扩展型半导体芯片31上的整个面形成绝缘性树脂层18B。在此，绝缘性树脂层18B具有感光性。
接着，如图6(b)所示，在利用CoC连接部形成区域被开口的掩膜53进行了曝光之后，如图6(c)所示，选择性地去除绝缘性树脂层18B中的感光区域。由此，由重新布线22和覆盖该重新布线22的绝缘性树脂层18A以及18B(以下，一起称为重新布线层间膜18)形成重新布线构造2。在此，重新布线构造2在CoC连接部形成区域具有开口。
然后，虽然省略了图示，但在芯片6的各电极20a上形成了凸起之后，在扩展型半导体芯片31上搭载芯片5，并对两者进行CoC接合。然后，将扩展型半导体芯片31和芯片5之间的层叠体固晶在基板上，并且通过引线接合将该基板和扩展型半导体芯片31电连接之后，进行模铸，由此获得所希望的CoC封装。
(第1变形例)
本变形例所涉及的半导体装置，与图1～图3所示的前述实施方式所涉及的半导体装置的不同点在于，重新布线构造2的开口图案的形状。
即，在前述的实施方式所涉及的半导体装置中，如图3所示，重新布线构造2的开口17a的中心与导电构件8的配置区域的中心实质上一致。
与此相对，在本变形例中，如图7(a)所示，虽然重新布线构造2在导电构件8的配置区域具有开口17b，但该开口17b的中心与导电构件8的配置区域的中心不一致。具体来说，本变形例的重新布线构造2的开口17b设置在导电构件8的配置区域以及与该配置区域相邻的区域B。在此，图7(a)是示意性地表示本变形例的重新布线构造2的开口的俯视图，在图7(a)中，对与图1以及图2所示的半导体装置相同的构成要素附加相同的符号。
根据如上的本变形例，除了与前述实施方式同样的效果之外，还能够获得如下效果。即，例如在将底部填充剂材料(成为图1的底部填充剂9的材料)从图7(a)所示的区域B注入的情况下，因为能够将底部填充剂材料的溢出抑制在开口17b内，所以能够缩短从导电构件8的配置区域到扩展型半导体芯片31(具体来说是扩展部1)上的连接端子21(图示省略)的距离。因此，由于能够缩小扩展型半导体芯片31的面积，因而能够实现低成本的半导体装置制造。
(第2变形例)
本变形例所涉及的半导体装置与图1～图3所示的前述实施方式所涉及的半导体装置的不同点在于，重新布线构造2的开口图案的形状。
即，在前述的实施方式所涉及的半导体装置中，如图3所示，由重新布线构造2包围了重新布线构造2的开口17a的整个周围。
与此相对，在本变形例中，如图7(b)所示，虽然重新布线构造2在导电构件8的配置区域具有开口17c，但该开口17c被设置为到达扩展型半导体芯片31的外周中的1边。在此，图7(b)是示意性地表示本变形例的重新布线构造2的开口的俯视图，在图7(b)中，对与图1以及图2所示的半导体装置相同的构成要素附加了相同的符号。
根据如上的本变形例，除了与前述实施方式同样的效果之外，还能够获得如下效果。即，例如在将底部填充剂材料(成为图1的底部填充剂9的材料)从重新布线构造2的开口17c所到达的扩展型半导体芯片31的1边侧进行了注入的情况下，能够从该1边侧选择性地排出底部填充剂材料。因此，由于在扩展型半导体芯片31的其他3边侧不再需要采取底部填充剂材料的溢出对策，换句话说，由于能够使底部填充剂9的填充性提高，因此能够实现低成本的半导体装置制造。
(第3变形例)
本变形例所涉及的半导体装置，与图1～图3所示的前述实施方式所涉及的半导体装置的不同点在于，重新布线构造2的开口图案的形状。
即，在前述的实施方式所涉及的半导体装置中，如图3所示，由重新布线构造2包围了重新布线构造2的开口17a的整个周围。
与此相对，在本变形例中，如图7(c)所示，虽然重新布线构造2在导电构件8的配置区域具有开口17d，但该开口17d设置为到达扩展型半导体芯片31的外周中的2边。在此，图7(c)是示意性地表示本变形例的重新布线构造2的开口的俯视图，在图7(c)中，对与图1以及图2所示的半导体装置相同的构成要素附加了相同的符号。
根据如上的本变形例，除了与前述实施方式同样的效果之外，还能够获得如下效果。即，例如在将底部填充剂材料(成为图1的底部填充剂9的材料)从重新布线构造2的开口17d所到达的扩展型半导体芯片31的2边中的至少1边侧进行了注入的情况下，能够从该2边侧选择性地排出底部填充剂材料。因此，由于不再需要在扩展型半导体芯片31的其他2边侧采取底部填充剂材料的溢出对策，换言之，由于能够使底部填充剂9的填充性提高，因而能够实现低成本的半导体装置制造。
此外，根据本变形例，由于能够从重新布线构造2的开口17d所到达的扩展型半导体芯片31的2边侧排出底部填充剂材料，因此在扩展型半导体芯片31的其他2边侧，与前述第2变形例相比，能够更进一步抑制底部填充剂材料的溢出。
(第4变形例)
本变形例所涉及的半导体装置，与图1～图3所示的前述实施方式所涉及的半导体装置的不同点在于，重新布线构造2的开口图案的形状。
即，在前述实施方式所涉及的半导体装置中，如图3所示，由重新布线构造2包围了重新布线构造2的开口17a的整个周围。
与此相对，在本变形例中，如图7(d)所示，虽然重新布线构造2在导电构件8的配置区域具有开口17e，但该开口17e设置为到达扩展型半导体芯片31的外周中的3边。在此，图7(d)是示意性地表示本变形例的重新布线构造2的开口的俯视图，在图7(d)中，对与图1以及图2所示的半导体装置相同的构成要素附加相同的符号。
根据如上的本变形例，除了与前述实施方式同样的效果之外，还能够获得如下效果。即，例如在将底部填充剂材料(成为图1的底部填充剂9的材料)从重新布线构造2的开口17e所到达的扩展型半导体芯片31的3边中的至少1边侧进行了注入的情况下，能够从该3边侧选择性地排出底部填充剂材料。因此，由于不再需要在扩展型半导体芯片31的其他1边侧采取底部填充剂材料的溢出对策，换言之，由于能够使底部填充剂9的填充性提高，因而能够实现低成本的半导体装置制造。
此外，根据本变形例，由于能够从重新布线构造2的开口17d所到达的扩展型半导体芯片31的3边侧排出底部填充剂材料，因此在扩展型半导体芯片31的其他1边侧，与前述第2变形例以及第3变形例相比，能够更进一步抑制底部填充剂材料的溢出。
(第5变形例)
本变形例所涉及的半导体装置，与图1～图3所示的前述实施方式所涉及的半导体装置的不同点在于，重新布线构造2的开口图案的形状。
即，在前述的实施方式所涉及的半导体装置中，如图3所示，由重新布线构造2包围了重新布线构造2的开口17a的整个周围。
与此相对，在本变形例中，如图7(e)所示，虽然重新布线构造2在导电构件8的配置区域具有开口17f，但该开口17f设置为到达扩展型半导体芯片31的外周中的4边。在此，图7(e)是示意性地表示本变形例的重新布线构造2的开口的俯视图，在图7(e)中，对与图1以及图2所示的半导体装置相同的构成要素附加了相同的符号。
根据如上的本变形例，除了与前述实施方式同样的效果之外，还能够获得如下效果。即，例如在将底部填充剂材料(成为图1的底部填充剂9的材料)从重新布线构造2的开口17f所到达的扩展型半导体芯片31的4边中的至少1边侧进行了注入的情况下，能够从该4边侧选择性地排出底部填充剂材料。因此，由于在扩展型半导体芯片31上的没有设置开口17f的区域中不再需要采取底部填充剂材料的溢出对策，换言之，由于能够使底部填充剂9的填充性提高，因此能够实现低成本的半导体装置制造。
此外，根据本变形例，由于能够从重新布线构造2的开口17d所到达的扩展型半导体芯片31的4边侧排出底部填充剂材料，因此在扩展型半导体芯片31上的没有开口17f的区域中，与前述第2～第4变形例相比，能够更进一步抑制底部填充剂材料的溢出。
(第6变形例)
本变形例所涉及的半导体装置，与图1～图3所示的前述实施方式所涉及的半导体装置的不同点在于，重新布线构造2的开口图案的形状。
即，在前述的实施方式所涉及的半导体装置中，如图3所示，重新布线构造2的开口17a设置在导电构件8的配置区域。
与此相对，在本变形例中，如图8(a)所示，虽然重新布线构造2在导电构件8的配置区域具有开口17g，但该开口17g设置为到达芯片5的外周中的1边的外侧。在此，图8(a)是示意性地表示本变形例的重新布线构造2的开口的俯视图，在图8(a)中，对与图1以及图2所示的半导体装置相同的构成要素附加了相同的符号。
根据如上的本变形例，除了与前述实施方式同样的效果之外，还能够获得如下效果。即，例如在底部填充剂材料(成为图1的底部填充剂9的材料)的注入时能够将底部填充剂材料的溢出抑制在开口17g内，因此能够缩短从导电构件8的配置区域到扩展型半导体芯片31(具体来说是扩展部1)上的连接端子21(图示省略)的距离。因此，由于能够缩小扩展型半导体芯片31的面积，因而能够实现低成本的半导体装置制造。
此外，根据本变形例，因为能够将底部填充剂材料的溢出抑制在开口17g内，所以与第2～第5变形例相比，能够避免底部填充剂材料扩散到树脂基板7(参照图1)的状况。
(第7变形例)
本变形例所涉及的半导体装置，与图1～图3所示的前述实施方式所涉及的半导体装置的不同点在于，重新布线构造2的开口图案的形状。
即，在前述的实施方式所涉及的半导体装置中，如图3所示，重新布线构造2的开口17a设置在导电构件8的配置区域。
与此相对，在本变形例中，如图8(b)所示，虽然重新布线构造2在导电构件8的配置区域具有开口17h，但该开口17h设置为到达芯片5的外周中的2边的外侧。在此，图8(b)是示意性地表示本变形例的重新布线构造2的开口的俯视图，在图8(b)中，对与图1以及图2所示的半导体装置相同的构成要素附加了相同的符号。
根据如上的本变形例，除了与前述实施方式同样的效果之外，还能够获得如下效果。即，例如在底部填充剂材料(成为图1的底部填充剂9的材料)的注入时能够将底部填充剂材料的溢出抑制在开口17h内，因此能够缩短从导电构件8的配置区域到扩展型半导体芯片31(具体来说是扩展部1)上的连接端子21(省略图示)的距离。因此，由于能够缩短扩展型半导体芯片31的面积，因而能够实现低成本的半导体装置制造。
此外，根据本变形例，因为能够将底部填充剂材料的溢出抑制在开口17h内，所以与第2～第5变形例相比，能够避免底部填充剂材料扩散到树脂基板7(参照图1)的状况。
进而，根据本变形例，与第6变形例的开口17g相比，能够进一步增大开口17h，因此与第6变形例相比，能够更进一步抑制底部填充剂材料向树脂基板7的扩散。
(第8变形例)
本变形例所涉及的半导体装置，与图1～图3所示的前述实施方式所涉及的半导体装置的不同点在于，重新布线构造2的开口图案的形状。
即，在前述实施方式所涉及的半导体装置中，如图3所示，重新布线构造2的开口17a设置在导电构件8的配置区域。
与此相对，在本变形例中，如图8(c)所示，虽然重新布线构造2在导电构件8的配置区域具有开口17i，但该开口17i被设置为到达芯片5的外周中的3边的外侧。在此，图8(c)是示意性地表示本变形例的重新布线构造2的开口的俯视图，在图8(c)中，对与图1以及图2所示的半导体装置相同的构成要素附加相同的符号。
根据如上本变形例，除了与前述实施方式同样的效果之外，还能够获得如下效果。即，例如在底部填充剂材料(成为图1的底部填充剂9的材料)的注入时能够将底部填充剂材料的溢出抑制在开口17i内，因此能够缩短从导电构件8的配置区域到扩展型半导体芯片31(具体来说是扩展部1)上的连接端子21(图示省略)的距离。因此，由于能够缩小扩展型半导体芯片31的面积，因而能够实现低成本的半导体装置制造。
此外，根据本变形例，由于能够将底部填充剂材料的溢出抑制在开口17i内，因此与第2～第5变形例相比，能够避免底部填充剂材料扩散到树脂基板7(参照图1)的状况。
进而，根据本变形例，与第6变形例的开口17g以及第7变形例的开口17h相比，能够进一步增大开口17i，因此与第6变形例以及第7变形例相比，能够更进一步抑制底部填充剂材料向树脂基板7的扩散。
(第9变形例)
本变形例所涉及的半导体装置与图1～图3所示的前述实施方式所涉及的半导体装置的不同点在于，重新布线构造2的开口图案的形状。
即，在前述的实施方式所涉及的半导体装置中，如图3所示，重新布线构造2的开口17a设置在导电构件8的配置区域。
与此相对，在本变形例中，如图8(d)所示，虽然重新布线构造2在导电构件8的配置区域具有开口17j，但该开口17j设置为到达芯片5的外周中的4边的外侧。在此，图8(d)是示意性地表示本变形例的重新布线构造2的开口的俯视图，在图8(d)中，对与图1以及图2所示的半导体装置相同的构成要素附加相同的符号。
根据如上的本变形例，除了与前述实施方式同样的效果之外，还能够获得如下效果。即，例如在底部填充剂材料(成为图1的底部填充剂9的材料)的注入时能够将底部填充剂材料的溢出抑制在开口17j内，因此能够缩短从导电构件8的配置区域到扩展型半导体芯片31(具体来说是扩展部1)上的连接端子21(图示省略)的距离。因此，由于能够缩小扩展型半导体芯片31的面积，因而能够实现低成本的半导体装置制造。
此外，根据本变形例，能够将底部填充剂材料的溢出抑制在开口17j内，因此与第2～第5变形例相比，能够避免底部填充剂材料扩散到树脂基板7(参照图1)的状况。
进而，根据本变形例，与第6变形例的开口17g、第7变形例的开口17h以及第8变形例的开口17i相比，能够进一步增大开口17j，因此与第6变形例、第7变形例以及第8变形例相比，能够更进一步抑制底部填充剂材料向树脂基板7的扩散。
如上所述，根据本公开，在具有CoC构造的半导体封装中，在下侧的芯片(第1半导体芯片)的外缘设置扩展部而构成扩展型半导体芯片，因此即使在下侧的芯片比上侧的芯片(第2半导体芯片)小的情况下，也能够使扩展型半导体芯片比上侧的芯片更大。因此，无需使用特别的半导体工艺，换言之，利用引线接合等简易的连接方法，就能够从例如为了与安装基板的电连接而在扩展型半导体芯片的扩展部设置的连接端子引出导电构件。因此，能够不受上侧的芯片和下侧的芯片之间的尺寸的大小关系的制约地，层叠多个半导体芯片来构成具有CoC构造的半导体封装。
此外，根据本公开，在具有CoC构造的半导体封装中，在将上下的各芯片电连接的导电构件(CoC连接部)的配置区域的外侧，在扩展部上以及下侧的芯片上设置有重新布线构造，因此能够不经由重新布线构造地将上下的各芯片电连接。因此，即使在CoC连接部被微细间距化的情况下，也不需要相应地将重新布线构造微细化，所以能够不受重新布线工艺规则的制约地，层叠多个半导体芯片来构成具有CoC构造的半导体封装。
以上，对本公开所涉及的实施方式及其变形例进行了说明，但本公开并非仅限于这些说明的构造，在不脱离发明的主旨的范围内能够进行各种变更。例如，经由设置在扩展部1内的贯通电极(未图示)来进行扩展型半导体芯片31与树脂基板7的电连接的构造，或者，如图9所示的，经由凸起14将扩展型半导体芯片31以芯片倒装方式连接在树脂基板7的构造也包含在本公开中。
工业实用性
本公开所涉及的半导体装置，不取决于半导体芯片的尺寸以及工艺微细度，能够通过将半导体芯片自由组合并层叠而获得，且由于不采用微细工艺来形成下侧芯片的重新布线因此能够实现成本的大幅削减，因而适合作为CoC型的SiP。
符号说明
1  扩展部
2  重新布线构造
3  电极焊盘
4  引线
5  芯片
6  芯片
7  树脂基板
8  导电构件
8a、8b  凸起
9  底部填充剂
12 封装球
13 接合间隙
14 凸起
17a～17j  开口
18 重新布线层间膜
18A、18B   绝缘性树脂层
19 固晶
20a、20b、24  电极
21 连接端子
22 重新布线
23 重新布线种子层
31 扩展型半导体芯片
50 抗蚀剂
51、52、53  掩膜

Claims (21)

1.一种半导体装置，具备：
基台，其具有第1电极；
第1半导体芯片，其配置在所述基台上的形成有所述第1电极的面上，并且具有第2电极；
扩展部，其设置为从所述第1半导体芯片的外缘向外侧方延伸，并且与所述第1半导体芯片一起构成扩展型半导体芯片；
第2半导体芯片，其具有第3电极，并且配置在所述扩展型半导体芯片上，使得形成有所述第3电极的面与所述第1半导体芯片中的形成有所述第2电极的面相对置；
第1导电构件，其将所述第2电极与所述第3电极相连接；
重新布线构造，其从所述第1半导体芯片上的所述第1导电构件的配置区域的外侧遍及到所述扩展部上而形成；
连接端子，其设置在所述扩展部上，并且经由所述重新布线构造与所述第2电极中没有与所述第1导电构件连接的电极相连接；和
第2导电构件，其将所述第1电极与所述连接端子相连接。
2.根据权利要求1所述的半导体装置，其中，
所述重新布线构造，至少避开所述第1导电构件的配置区域而配置，由此，所述重新布线构造在述第1导电构件的配置区域具有开口。
3.根据权利要求2所述的半导体装置，其中，
所述重新布线构造的所述开口的中心与所述第1导电构件的配置区域的中心不一致。
4.根据权利要求2或3所述的半导体装置，其中，
所述重新布线构造的所述开口，被设置为到达所述扩展型半导体芯片的外周中的1边。
5.根据权利要求2或3所述的半导体装置，其中，
所述重新布线构造的所述开口，被设置为到达所述扩展型半导体芯片的外周中的2边。
6.根据权利要求2或3所述的半导体装置，其中，
所述重新布线构造的所述开口，被设置为到达所述扩展型半导体芯片的外周中的3边。
7.根据权利要求2或3所述的半导体装置，其中，
所述重新布线构造的所述开口，被设置为到达所述扩展型半导体芯片的外周中的4边。
8.根据权利要求2或3所述的半导体装置，其中，
所述重新布线构造的所述开口，被设置为到达所述第2半导体芯片的外周中的1边的外侧。
9.根据权利要求2或3所述的半导体装置，其中，
所述重新布线构造的所述开口，被设置为到达所述第2半导体芯片的外周中的2边的外侧。
10.根据权利要求2或3所述的半导体装置，其中，
所述重新布线构造的所述开口，被设置为到达所述第2半导体芯片的外周中的3边的外侧。
11.根据权利要求2或3所述的半导体装置，其中，
所述重新布线构造的所述开口，被设置为到达所述第2半导体芯片的外周中的4边的外侧。
12.根据权利要求1～11中任一项所述的半导体装置，其中，
所述第1导电构件是凸起。
13.根据权利要求1～12中任一项所述的半导体装置，其中，
所述连接端子是引线接合端子，
所述第2导电构件是引线。
14.根据权利要求1～13中任一项所述的半导体装置，其中，
所述重新布线构造具有将所述第1电极与所述连接端子相连接的重新布线、和覆盖所述重新布线的层间膜。
15.根据权利要求14所述的半导体装置，其中，
所述层间膜由覆盖所述扩展型半导体芯片的树脂材料构成。
16.根据权利要求15所述的半导体装置，其中，
所述树脂材料是感光性树脂材料，
所述感光性树脂材料的分辨率，比用于所述第2半导体芯片的其他感光性树脂材料的分辨率小。
17.根据权利要求14所述的半导体装置，其中，
所述层间膜的至少上部由阻焊剂构成。
18.根据权利要求1～17中任一项所述的半导体装置，其中，
所述重新布线构造的厚度，与所述扩展型半导体芯片和所述第2半导体芯片之间的接合间隙实质上相同或者小于该接合间隙。
19.根据权利要求1～18中任一项所述的半导体装置，其中，
所述重新布线的布线宽度以及布线间隔，分别大于在所述第2半导体芯片上形成的其他布线的布线宽度以及布线间隔。
20.根据权利要求1～19中任一项所述的半导体装置，其中，
所述第2半导体芯片的平面形状大于所述第1半导体芯片的平面形状，
所述扩展型半导体芯片的平面形状大于所述第2半导体芯片的平面形状。
21.一种半导体装置，具备：
第1半导体芯片，其具有第1电极；
扩展部，其被设置为从所述第1半导体芯片的外缘向外侧方延伸，并且与所述第1半导体芯片一起构成扩展型半导体芯片；
第2半导体芯片，其具有第2电极，并且配置在所述扩展型半导体芯片上，使得形成有所述第2电极的面与所述第1半导体芯片中的形成有所述第1电极的面相对置；
导电构件，其将所述第1电极与所述第2电极相连接；
重新布线构造，其从所述第1半导体芯片上的所述导电构件的配置区域的外侧遍及到所述扩展部上而形成；和
连接端子，其被设置在所述扩展部上，并且经由所述重新布线构造与所述第1电极中没有与所述导电构件连接的电极相连接。
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