CN103633098B - 显示装置及其制造方法 - Google Patents
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Abstract
本发明的显示装置及其制造方法的目的在于防止因入射光导致的可靠性降低以及绝缘耐压降低。栅极绝缘膜(30)随着栅电极(26)的表面形状而具有凸部(32),具有高度从栅电极的周缘沿着栅电极的表面而变化的层差部(34)。氧化物半导体层(40)以具有晶体管构成用区域(42)和覆盖区域(50)的方式设置在栅极绝缘膜上,晶体管构成用区域是连续一体地具有沟道区域、源极区域以及漏极区域的区域,覆盖区域是与晶体管构成用区域分离并覆盖栅极绝缘膜的层差部的区域。在氧化物半导体层的沟道区域上设置有沟道保护层。与氧化物半导体层的源极区域以及漏极区域接触地设置有源电极以及漏电极。在源电极以及漏电极上设置有钝化层。
Description
技术领域
本发明涉及显示装置及其制造方法。
背景技术
在平板显示器中,作为开关元件使用了薄膜晶体管(ThinFilmTransistor;TFT)。在底栅型的TFT中,在基板上设置有栅电极,以覆盖栅电极的方式在基板上形成栅极绝缘膜。由于栅电极的存在而在基板上形成凸部,栅极绝缘膜因其成膜工序的特性而具有与基底的凸部的表面形状相应的表面形状。也就是说,栅极绝缘膜具有高度从栅电极的周缘沿着栅电极的表面而变化的部分(层差)。换言之,栅极绝缘膜在栅电极的端部上方具有层差。
在专利文献1中,公开了具有沟道保护层,并将由无定形硅或多晶硅形成的半导体层配置在比栅电极的周缘更靠内侧的位置的构造。在该构造中,由于半导体层位于比栅电极的周缘更靠内侧的位置,因此在栅极绝缘膜的层差上不存在半导体层。
在专利文献2中,公开了具有沟道保护层,并将氧化物半导体层延长至栅电极的外侧的构造。在该构造中,由于半导体层位于栅电极的外侧,因此在栅极绝缘膜的层差上存在半导体层。
专利文献1:日本特开2010-278077号公报
专利文献2:日本特开2011-166135号公报
发明内容
在要由氧化物半导体实现专利文献1公开的构造的情况下,在加工沟道保护层时栅极绝缘膜也会被削减,栅极绝缘膜变薄,因此产生绝缘耐压降低这样的问题。
在专利文献2所公开的构造中,特别是在绝缘耐压的降低成为问题的部分、即在由于栅电极的厚度而产生的栅极绝缘膜的层差部上方也形成有半导体层。因此,在加工沟道保护层时,因为半导体层成为保护层,所以不会削减至栅极绝缘膜而发生绝缘耐压降低。
然而,在底栅型的TFT中,在与栅电极相比半导体层形成得更宽的情况下,发生如下这样的问题:背光照明的光入射到半导体层,使半导体层(沟道)的劣化加速,可靠性降低。
本发明的目的在于防止因入射光导致的可靠性降低以及绝缘耐压降低。
(1)本发明涉及的显示装置,其特征在于,具有:基板;栅电极,其设置在所述基板上;栅极绝缘膜,其以覆盖所述栅电极的方式设置在所述基板上,随着所述栅电极的表面形状而具有凸部,具有高度沿着从所述栅电极的周缘升起的形状而变化的层差部;氧化物半导体层,其以具有晶体管构成用区域和覆盖区域的方式设置在所述栅极绝缘膜上,所述晶体管构成用区域是连续一体地具有沟道区域、源极区域以及漏极区域的区域,所述覆盖区域是与所述晶体管构成用区域分离并覆盖所述栅极绝缘膜的所述层差部的区域;沟道保护层,其设置在所述氧化物半导体层的所述沟道区域上;源电极以及漏电极,其分别与所述氧化物半导体层的所述源极区域以及所述漏极区域接触地设置;以及钝化层,其设置在所述源电极以及所述漏电极上。根据本发明,因为栅极绝缘膜的层差部被氧化物半导体层的覆盖区域所覆盖,所以绝缘层变厚能防止绝缘耐压的降低。另外,因为氧化物半导体层的覆盖区域与晶体管构成用区域分离,所以不会因入射光导致可靠性降低。
(2)在(1)所示的显示装置中,其特征也可以在于,还具有:与所述栅电极连接的栅极布线;与所述源电极连接的源极布线;和与所述漏电极连接的漏极布线,所述栅极绝缘膜,以覆盖所述栅极布线的方式设置在所述基板上,随着所述栅极布线的表面形状而具有第2凸部,具有高度沿着从所述栅极布线的周缘升起的形状而变化的第2层差部,所述源极布线以及所述漏极布线的至少一方,隔着所述栅极绝缘膜与所述栅极布线立体地交叉,所述氧化物半导体层包含以覆盖所述第2层差部的与所述源极布线以及所述漏极布线的所述至少一方重叠的区域的方式、与所述晶体管构成用区域分离的第2覆盖区域。
(3)在(1)或(2)所述的显示装置中,其特征也可以在于,所述氧化物半导体层形成为所述晶体管构成用区域以及所述覆盖区域的厚度相同。
(4)在(2)所述的显示装置中,其特征也可以在于,所述氧化物半导体层形成为所述晶体管构成用区域、所述覆盖区域以及所述第2覆盖区域的厚度相同。
(5)在(1)~(4)中任一项所述的显示装置中,其特征也可以在于,所述氧化物半导体层由选自In-Ga-Zn-O系、In-Al-Zn-O系、In-Sn-Zn-O系、In-Zn-O系、In-Sn-O系、Zn-O系以及Sn-O系中的一种氧化物半导体形成。
(6)本发明涉及的显示装置的制造方法,其特征在于,包括:以如下方式在基板上形成栅极绝缘膜的工序:覆盖设置在所述基板上的栅电极、随着所述栅电极的表面形状而具有凸部、具有高度沿着从所述栅电极的周缘升起的形状而变化的层差部;以如下方式在所述栅极绝缘膜上形成氧化物半导体层的工序:具有晶体管构成用区域和覆盖区域,所述晶体管构成用区域是连续一体地具有沟道区域、源极区域以及漏极区域的区域,所述覆盖区域是与所述晶体管构成用区域分离并覆盖所述栅极绝缘膜的所述层差部的区域;在所述氧化物半导体层上形成保护层的工序;以如下方式使所述保护层图案化的工序:对所述保护层以及所述栅极绝缘膜进行蚀刻,通过所述氧化物半导体层作为阻止蚀刻层发挥作用的蚀刻,在所述氧化物半导体层的所述沟道区域上留下一部分作为沟道保护层;以如下方式形成源电极以及漏电极的工序:使所述源电极以及所述漏电极分别与所述氧化物半导体层的所述源极区域以及所述漏极区域接触;以及在所述源电极以及所述漏电极上形成钝化层的工序。根据本发明,由于氧化物半导体层的覆盖区域成为阻止蚀刻层,所以栅极绝缘膜的层差部不会被蚀刻。因此,层差部的栅极绝缘膜不会变薄,因此能够防止绝缘耐压的降低。另外,因为氧化物半导体层的覆盖区域与晶体管构成用区域分离,所以不会因入射光导致可靠性降低。
(7)在(6)所述的显示装置的制造方法中,其特征也可以在于,在所述基板上以与所述栅电极连接的方式形成栅极布线,所述栅极绝缘膜形成为覆盖所述栅极布线、随着所述栅极布线的表面形状而具有第2凸部,且具有高度沿着从所述栅极布线的周缘升起的形状而变化的第2层差部,在所述栅极绝缘膜上以与所述源电极连接的方式形成源极布线,在所述栅极绝缘膜上以与所述漏电极连接的方式形成漏极布线,所述源极布线以及所述漏极布线的至少一方形成为隔着所述栅极绝缘膜与所述栅极布线立体地交叉,所述氧化物半导体层形成为具有第2覆盖区域,所述第2覆盖区域以将所述第2层差部的与所述源极布线以及所述漏极布线的所述至少一方重叠的区域覆盖的方式与所述晶体管构成用区域分离。
(8)在(6)或(7)所述的显示装置的制造方法中,其特征也可以在于,所述氧化物半导体层形成为所述晶体管构成用区域以及所述覆盖区域的厚度相同。
(9)在(6)所述的显示装置的制造方法中,其特征也可以在于,所述氧化物半导体层形成为所述晶体管构成用区域、所述覆盖区域以及所述第2覆盖区域的厚度相同。
(10)在(6)~(9)中任一项所述的显示装置的制造方法中,其特征也可以在于,所述氧化物半导体层由选自In-Ga-Zn-O系、In-Al-Zn-O系、In-Sn-Zn-O系、In-Zn-O系、In-Sn-O系、Zn-O系以及Sn-O中的一种氧化物半导体形成。
附图说明
图1是表示本发明的实施方式的显示装置的剖面图。
图2是第2基板的层叠构造的俯视图。
图3是图2所示构造的III-III线剖面图。
图4是图2所示构造的IV-IV线剖面图。
图5A~图5D是说明本发明的实施方式的显示装置的制造方法的图。
图6A~图6C是说明本发明的实施方式的显示装置的制造方法的图。
附图标记的说明
10第1基板,12黑矩阵,14滤色片,16平坦化层,18第1取向膜,20第2取向膜,22液晶材料,24第2基板,26栅电极,28栅极布线,30栅极绝缘膜,32凸部,34层差部,36第2凸部,38第2层差部,40氧化物半导体层,42晶体管构成用区域,44沟道区域,46源极区域,48漏极区域,50覆盖区域,52第2覆盖区域,54沟道保护层,56源电极,58漏电极,60源极布线,62漏极布线,64像素电极,66钝化层,68保护层
具体实施方式
以下,参照附图对本发明的实施方式进行说明。
图1是表示本发明的实施方式的显示装置的剖面图。显示装置具有第1基板10。在第1基板10上层叠有黑矩阵(blackmatrix)12、滤色片14、平坦化层16以及第1取向膜18,构成滤色片基板。与第1取向膜18相对并隔着单元间隙(cellgap)地配置有第2取向膜20。在第1取向膜18与第2取向膜20之间配置有液晶材料22。
图1所示的显示装置,在本实施方式中为液晶显示装置,但也可以是除此以外的有机电致发光显示装置等。第2取向膜20为层叠于第2基板24的构造的最上层。第2基板24例如由玻璃形成。
图2是第2基板24的层叠构造的俯视图。在第2基板24上形成有晶体管的栅电极26。晶体管是底栅型的薄膜晶体管。形成有薄膜晶体管的第2基板24被称为TFT(ThinFilmTransistor)基板。栅电极26由选自铝、钼、铬、铜、钨、钛、锆、钽、银以及锰的元素或者组合这些元素而成的合金等来形成。另外,也可以采用在钛上层叠铝或者由铝的上层和下层夹着钛这样的层叠构造。显示装置如图2所示具有与栅电极26连接的栅极布线28。
显示装置具有栅极绝缘膜30。栅极绝缘膜30能够由氧化硅膜,氮化硅膜,氮氧化硅膜等的绝缘膜来形成,也可以是层叠这些绝缘膜而成的构造。但是,栅极绝缘膜30的最上层或由1层形成时的栅极绝缘膜30,因为在其上与后述的氧化物半导体层40接触,所以考虑对氧化物半导体层40产生的影响,优选为氧化硅膜。栅极绝缘膜30在膜厚为80nm以上且2000nm以下的范围内考虑绝缘耐压和/或电容以最佳膜厚构成即可。
栅极绝缘膜30以覆盖栅电极26的方式设置在第2基板24上。栅极绝缘膜30随着栅电极26的表面形状而具有凸部32。详细而言,由于栅电极26的表面从第2基板24的表面鼓起而形成凸部32。栅极绝缘膜30具有高度沿着从栅电极26的周缘升起的形状而变化的层差部34。即,在栅电极26的端部上方形成层差部34。
图3是图2所示构造的III-III线剖面图。图4是图2所示构造的IV-IV线剖面图。
栅极绝缘膜30以也覆盖栅极布线28的方式设置在第2基板24上。如图3所示,栅极绝缘膜30随着栅极布线28的表面形状而具有第2凸部36。详细而言,由于栅极布线28的表面从第2基板24的表面鼓起而形成第2凸部36。栅极绝缘膜30具有高度沿着从栅极布线28的周缘升起的形状而变化的第2层差部38。即,在栅极布线28的侧端部上方形成第2层差部38。
显示装置具有氧化物半导体层40。氧化物半导体层40例如是由以铟、钙、锌以及氧为主要成分的元素形成的In-Ga-Zn-O系的氧化物半导体,也将其记载为IGZO膜。氧化物半导体除此以外也可以使用In-Al-Zn-O系、In-Sn-Zn-O系、In-Zn-O系、In-Sn-O系、Zn-O系、Sn-O系等。氧化物半导体层40的膜厚在30nm以上且500nm以下的范围内,在需要大电流的器件中使用的情况下形成得较厚等,根据目的来调整膜厚即可。
氧化物半导体层40设置在栅极绝缘膜30上。如图1以及图2所示,氧化物半导体层40具有晶体管构成用区域42。晶体管构成用区域42连续一体地具有沟道区域44、源极区域46以及漏极区域48。
如图1所示,氧化物半导体层40包含将栅极绝缘膜30的层差部34覆盖的覆盖区域50。覆盖区域50与晶体管构成用区域42分离。覆盖区域50形成为厚度与晶体管构成用区域42的厚度相同。
根据本实施方式,因为栅极绝缘膜30的层差部34被氧化物半导体层40的覆盖区域50所覆盖,所以绝缘层变厚而能防止绝缘耐压降低。另外,因为氧化物半导体层40的覆盖区域50与晶体管构成用区域42分离,所以不会因入射光导致可靠性降低。
如图2所示,氧化物半导体层40包含第2覆盖区域52。第2覆盖区域52配置在第2层差部38上。第2覆盖区域52与晶体管构成用区域42分离。第2覆盖区域52形成为厚度与晶体管构成用区域42以及覆盖区域50的厚度相同。
根据本实施方式,因为栅极绝缘膜30的第2层差部38被氧化物半导体层40的第2覆盖区域52所覆盖,所以绝缘层变厚而能防止绝缘耐压降低。另外,因为氧化物半导体层40的第2覆盖区域52与晶体管构成用区域42分离,所以不会因入射光导致可靠性降低。
如图1以及图2所示,显示装置具有沟道保护层54。沟道保护层54由氧化硅膜形成。沟道保护层54设置在氧化物半导体层40的沟道区域44上。
显示装置具有源电极56以及漏电极58。源电极56以及漏电极58分别与氧化物半导体层40的源极区域46以及漏极区域48接触地设置。源电极56以及漏电极58由上述的作为栅电极26可选择的材料形成,可以由与栅电极26相同的材料形成。
如图2所示,在源电极56上连接有源极布线60,在漏电极58上连接有漏极布线62。源极布线60以及漏极布线62的至少一方(例如漏极布线62)隔着栅极绝缘膜30与栅极布线28立体地交叉。第2覆盖区域52覆盖第2层差部38的与源极布线60以及漏极布线62的至少一方重叠的区域。此外,源极布线60以及漏极布线62的另一方(例如源极布线60),在图2的例子中,与像素电极64连接。
显示装置具有钝化层66。钝化层66可以由氧化硅膜、氮化硅膜或氮氧化硅膜等的绝缘膜来形成,也可以层叠这些绝缘膜来形成。钝化层66设置在源电极56以及漏电极58上。在钝化层66上形成有第2取向膜20。
图5A~图6C是说明本发明的实施方式的显示装置的制造方法的图。
显示装置的制造方法包括栅极绝缘膜30的形成、氧化物半导体层40的形成、沟道保护层54的形成、源电极56以及漏电极58的形成以及钝化层66的形成。
首先,准备设置有栅电极26的第2基板24(参照图5A)。在栅电极26的形成工序中,例如通过溅射法成膜钼膜、铝膜等的金属导电膜。然后,在金属导电膜上涂覆了感光性树脂膜之后,通过使其曝光以及显影来图案化,形成抗蚀剂图案。然后,在将从抗蚀剂图案露出的金属导电膜通过湿式蚀刻或干式蚀刻除去之后,剥离抗蚀剂图案,形成栅电极26。在第2基板24由玻璃形成的情况下,为了防止来自玻璃的碱性离子等的混入,可以在第2基板24上形成氮化硅膜,并在该氮化硅膜上形成栅电极26。
如图5A所示,在第2基板24以覆盖栅电极26的方式形成栅极绝缘膜30。栅极绝缘膜30通过利用等离子体CVD(ChemicalVaporDeposition)法成膜氧化硅膜、氮化硅膜或氮氧化硅膜等来形成。在栅极绝缘膜30上随着栅电极26的表面形状形成凸部32。在栅极绝缘膜30,形成高度沿着从栅电极26的周缘升起的形状而变化的层差部34。
在第2基板24上,以与栅电极26连接的方式形成栅极布线28(参照图2)。栅极绝缘膜30形成为覆盖栅极布线28。栅极绝缘膜30形成为随着栅极布线28的表面形状而具有第2凸部36(参照图3)。栅极绝缘膜30形成为具有高度沿着从栅极布线28的周缘升起的形状而变化的第2层差部38(参照图3)。
如图5B所示,在栅极绝缘膜30上形成氧化物半导体层40。在氧化物半导体层40的形成工序中,通过溅射法,成膜In-Ga-Zn-O系、In-Al-Zn-O系、In-Sn-Zn-O系、In-Zn-O系、In-Sn-O系、Zn-O系、Sn-O系等的氧化物半导体。
如图5C所示,将氧化物半导体层40图案化成具有晶体管构成用区域42。详细而言,在氧化物半导体层40上涂覆了感光性树脂膜之后,通过使其曝光以及显影来图案化,形成抗蚀剂图案。抗蚀剂图案形成为将氧化物半导体层40的晶体管构成用区域42、覆盖区域50以及第2覆盖区域52覆盖(参照图2)。然后,在将从抗蚀剂图案露出的氧化物半导体层40通过湿式蚀刻除去之后,剥离抗蚀剂图案。通过对氧化物半导体层40实施使用了氧和/或一氧化二氮的等离子体处理,能够形成氧缺陷少的氧化物半导体层40。
晶体管构成用区域42连续一体地具有沟道区域44、源极区域46以及漏极区域48。氧化物半导体形成为具有覆盖区域50。覆盖区域50与晶体管构成用区域42分离并覆盖栅极绝缘膜30的层差部34。覆盖区域50形成为厚度与晶体管构成用区域42的厚度相同。
氧化物半导体层40形成为具有将栅极绝缘膜30的第2层差部38覆盖的第2覆盖区域52(参照图3)。第2覆盖区域52形成为与晶体管构成用区域42分离。第2覆盖区域52形成为厚度与晶体管构成用区域42以及覆盖区域50的厚度相同。
如图5D所示,在氧化物半导体层40上形成保护层68。通过等离子体CVD法等成膜氧化硅膜来形成保护层68。
如图6A所示,使保护层68图案化。详细而言,以在氧化物半导体层40的沟道区域44上留下一部分作为沟道保护层54的方式,使保护层68图案化。图案化通过蚀刻来进行。例如,在保护层68上涂覆感光性树脂膜,通过使其曝光以及显影来图案化,形成抗蚀剂图案。然后,将从抗蚀剂图案露出的保护层68通过干式蚀刻除去,形成沟道保护层54。
蚀刻是对保护层68以及栅极绝缘膜30进行蚀刻、且氧化物半导体层40作为阻止蚀刻层发挥作用的蚀刻。也就是说,在对保护层68进行干式蚀刻时,由于氧化物半导体层40起到阻止蚀刻层的作用,所以栅极绝缘膜30的被氧化物半导体层40覆盖的部分没有被蚀刻。例如在作为蚀刻剂使用了CF4等的蚀刻气体的情况下,虽然氧化硅膜由于因等离子体所发生的离子冲击而削减,但因为IGZO等的氧化物半导体耐离子冲击的耐性强而几乎没有削减,所以氧化物半导体层40起到阻止蚀刻层的作用。
主要构成保护层68以及栅极绝缘膜30的元素是SiOx,由于两者的蚀刻率大致同等,因此在保护层68的干式蚀刻加工时,从氧化物半导体层40露出的栅极绝缘膜30被削减。在大型基板的整个面上难以使蚀刻率均一,因位置不同所削减的量就不同。在形成了源电极56以及漏电极58之后,因为在栅电极26的端部上栅极绝缘膜30的匀镀力(coverage:覆盖度)不良,所以在此基础上栅极绝缘膜30削减的量变多,存在引起栅电极26与漏电极58的绝缘耐压低于100V这样的耐压降低的情况。
在本实施方式中,通过在栅电极26的端部上的栅极绝缘膜30的匀镀力不良的位置,形成氧化物半导体层40(覆盖区域50),在保护层68的干式蚀刻加工时,氧化物半导体层40成为阻止蚀刻层,能够防止栅极绝缘膜30被削减。由此,栅电极26的端部上的栅极绝缘膜30的匀镀力不良位置处的栅电极26与漏电极58的绝缘耐压不会低于200V,能够实现可靠性高的薄膜晶体管。
此外,在无定形硅TFT(ThinFilmTransistor)、多晶硅TFT(ThinFilmTransistor)中,即使与上述同样地将半导体层用作阻止蚀刻层,也由于无定形硅、多晶硅的蚀刻率与氧化硅膜或氮化硅膜的蚀刻率大致相同,因此难以作为阻止蚀刻层来使用。与此相对,如本实施方式所示,在晶体管中使用氧化物半导体时,在层差部形成氧化物半导体,能够将其用作干式蚀刻的阻止蚀刻层。
例如在形成了50nm的沟道层并形成了200nm的阻止蚀刻层的情况下,即使在层差部与沟道层相同地形成了50nm的无定形硅或多晶硅,但在对200nm的阻止蚀刻层进行干式蚀刻的期间,在层差部形成的50nm的无定形硅或多晶硅也全被削掉而到达栅极绝缘膜,被削减至栅极绝缘膜。另一方面,由于如上所述氧化物半导体对干式蚀刻具有耐性,所以不存在这样的问题。因此,本实施方式是将氧化物半导体用作沟道层的情况下的特征性的技术。
在对保护层68进行了干式蚀刻之后,剥离抗蚀剂图案。虽然没有图示,但可以在形成源电极56以及漏电极58之前,预先在栅极绝缘膜30形成与栅电极26接触的接触孔。
如图6B所示,形成源电极56以及漏电极58。在源电极56以及漏电极58的形成工序中,通过溅射法成膜钼膜或铝膜等的金属导电膜。接着,在金属导电膜上涂覆感光性树脂膜,通过使其曝光以及显影来图案化,形成抗蚀剂图案。然后,在将从抗蚀剂图案露出的金属导电膜通过湿式蚀刻除去之后,剥离抗蚀剂图案,形成源电极56以及漏电极58。源电极56以及漏电极58形成为分别与氧化物半导体层40的源极区域46以及漏极区域48接触。
在栅极绝缘膜30上以与源电极56连接的方式形成源极布线60(参照图2)。在栅极绝缘膜30上以与漏电极58连接的方式形成漏极布线62。源极布线60以及漏极布线62的至少一方形成为隔着栅极绝缘膜30与栅极布线28立体地交叉。在栅极绝缘膜30的第2层差部38,形成有氧化物半导体层40的第2覆盖区域52,与栅极布线28立体交叉的源极布线60以及漏极布线62的至少一方,形成为穿过第2覆盖区域52上。
如图6C所示,在源电极56以及漏电极58上形成钝化层66。钝化层66通过利用等离子体CVD法等成膜氧化硅膜、氮化硅膜或氮氧化硅膜等的绝缘膜来形成。然后,虽然没有图示,但在钝化层66形成与源电极56以及漏电极58接触的接触孔。如图1所示,在钝化层66上形成第2取向膜20。另外,然后,与第1基板10以及第2基板24相对地在两者之间配置液晶材料22。另外,本实施方式的制造方法包括制造液晶显示装置时的周知的工序。
根据本实施方式,由于氧化物半导体层40的覆盖区域50成为阻止蚀刻层,所以栅极绝缘膜30的层差部34不会被蚀刻。因此,层差部34处的栅极绝缘膜30不会变薄,所以能够防止绝缘耐压的降低。另外,因为氧化物半导体层40的覆盖区域50与晶体管构成用区域42分离,所以不会因入射光导致可靠性降低。
本发明并不限定于上述的实施方式而能够进行各种变形。例如,实施方式中说明的结构,能够由实质上相同的结构、能够起到相同作用效果的结构或达到相同目的的结构来替换。
Claims (10)
1.一种显示装置,其特征在于,具有:
基板;
栅电极,其设置在所述基板上;
栅极绝缘膜,其以覆盖所述栅电极的方式设置在所述基板上,随着所述栅电极的表面形状而具有凸部,具有高度沿着从所述栅电极的周缘升起的形状而变化的层差部;
氧化物半导体层,其以具有晶体管构成用区域和覆盖区域的方式设置在所述栅极绝缘膜上,所述晶体管构成用区域是连续一体地具有沟道区域、源极区域以及漏极区域的区域,所述覆盖区域是与所述晶体管构成用区域分离并覆盖所述栅极绝缘膜的所述层差部的区域;
沟道保护层,其设置在所述氧化物半导体层的所述沟道区域上;
源电极以及漏电极,其分别与所述氧化物半导体层的所述源极区域以及所述漏极区域接触地设置;以及
钝化层,其设置在所述源电极以及所述漏电极上。
2.根据权利要求1所述的显示装置,其特征在于,还具有:
与所述栅电极连接的栅极布线;
与所述源电极连接的源极布线;以及
与所述漏电极连接的漏极布线,
所述栅极绝缘膜,以覆盖所述栅极布线的方式设置在所述基板上,随着所述栅极布线的表面形状而具有第2凸部,具有高度沿着从所述栅极布线的周缘升起的形状而变化的第2层差部,
所述源极布线以及所述漏极布线的至少一方,隔着所述栅极绝缘膜与所述栅极布线立体地交叉,
所述氧化物半导体层包含第2覆盖区域,所述第2覆盖区域以覆盖所述第2层差部的与所述源极布线以及所述漏极布线的所述至少一方重叠的区域的方式形成、并且与所述晶体管构成用区域分离。
3.根据权利要求1所述的显示装置,其特征在于,
所述氧化物半导体层形成为所述晶体管构成用区域以及所述覆盖区域的厚度相同。
4.根据权利要求2所述的显示装置,其特征在于,
所述氧化物半导体层形成为所述晶体管构成用区域、所述覆盖区域以及所述第2覆盖区域的厚度相同。
5.根据权利要求1~4中任一项所述的显示装置,其特征在于,
所述氧化物半导体层由选自In-Ga-Zn-O系、In-Al-Zn-O系、In-Sn-Zn-O系、In-Zn-O系、In-Sn-O系、Zn-O系以及Sn-O系中的一种氧化物半导体形成。
6.一种显示装置的制造方法,其特征在于,包括:
以如下方式在基板上形成栅极绝缘膜的工序:覆盖设置在所述基板上的栅电极、随着所述栅电极的表面形状而具有凸部、具有高度沿着从所述栅电极的周缘升起的形状而变化的层差部;
以如下方式在所述栅极绝缘膜上形成氧化物半导体层的工序:具有晶体管构成用区域和覆盖区域,所述晶体管构成用区域是连续一体地具有沟道区域、源极区域以及漏极区域的区域,所述覆盖区域是与所述晶体管构成用区域分离并覆盖所述栅极绝缘膜的所述层差部的区域;
在所述氧化物半导体层上形成保护层的工序;
以如下方式使所述保护层图案化的工序:对所述保护层以及所述栅极绝缘膜进行蚀刻,通过所述氧化物半导体层作为阻止蚀刻层发挥作用的蚀刻,在所述氧化物半导体层的所述沟道区域上留下一部分作为沟道保护层;
以如下方式形成源电极以及漏电极的工序:使所述源电极以及所述漏电极分别与所述氧化物半导体层的所述源极区域以及所述漏极区域接触;以及
在所述源电极以及所述漏电极上形成钝化层的工序。
7.根据权利要求6所述的显示装置的制造方法,其特征在于,
在所述基板上以与所述栅电极连接的方式形成栅极布线,
所述栅极绝缘膜形成为覆盖所述栅极布线、随着所述栅极布线的表面形状而具有第2凸部,且具有高度沿着从所述栅极布线的周缘升起的形状而变化的第2层差部,
在所述栅极绝缘膜上以与所述源电极连接的方式形成源极布线,
在所述栅极绝缘膜上以与所述漏电极连接的方式形成漏极布线,
所述源极布线以及所述漏极布线的至少一方形成为隔着所述栅极绝缘膜与所述栅极布线立体地交叉,
所述氧化物半导体层形成为具有第2覆盖区域,所述第2覆盖区域以将所述第2层差部的与所述源极布线以及所述漏极布线的所述至少一方重叠的区域覆盖的方式形成、并且与所述晶体管构成用区域分离。
8.根据权利要求6所述的显示装置的制造方法,其特征在于,
所述氧化物半导体层形成为所述晶体管构成用区域以及所述覆盖区域的厚度相同。
9.根据权利要求7所述的显示装置的制造方法,其特征在于,
所述氧化物半导体层形成为所述晶体管构成用区域、所述覆盖区域以及所述第2覆盖区域的厚度相同。
10.根据权利要求6~9中任一项所述的显示装置的制造方法,其特征在于,
所述氧化物半导体层由选自In-Ga-Zn-O系、In-Al-Zn-O系、In-Sn-Zn-O系、In-Zn-O系、In-Sn-O系、Zn-O系以及Sn-O系中的一种氧化物半导体形成。
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