CN103594499A - 一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构 - Google Patents
一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构 Download PDFInfo
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Abstract
本发明公开了一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，在已经成形的纵向NPN管发射极的复合栅结构多晶硅表面，注入N+扩散区的掺杂杂质，注入区的尺寸大于等于BiCMOS工艺的光刻特征尺寸。本发明在不增加制造成本和牺牲器件性能的前提下，大大减小多晶硅发射极纵向NPN三极管的发射极电阻，且能够让发射极电阻随着发射区面积的增加而呈线性降低。本发明可以有效的起到简化模拟电路设计，提高电路性能，提高产品竞争力的作用。
Description
技术领域
本发明公开了一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，涉及半导体制造技术领域。
背景技术
目前在主流的高速高性能BiCMOS工艺中，广泛使用了多晶硅发射极纵向NPN三极管，以满足对高工作频率、高增益、低噪声特性的器件需求。在这些BiCMOS工艺中，多晶硅不仅仅做纵向NPN三极管的发射极，也做为CMOS器件的栅极。多晶硅通常采用多晶硅--硅化物--多晶硅的复合栅结构，以实现更小的多晶连线电阻。
多晶硅发射极纵向NPN三极管相对于常规注入发射极纵向NPN三极管，在提高工作频率、增益、噪声特性的同时，由于其发射区多晶硅和单晶硅界面间薄自然氧化层和多晶硅--硅化物--多晶硅间界面态的存在，使其发射极电阻相比常规注入发射极结构会有1~2倍的增加。例如当发射区面积为2 um ×2um时，常规注入发射极纵向NPN三极管的发射极电阻约为20~50欧姆，而典型的0.5um BiCMOS工艺中多晶硅发射极纵向NPN三极管的发射极电阻约为200~300欧姆，且当发射区面积增加时，发射极电阻并不减小，这将给电路设计带来极大的困难。
发明内容
本发明所要解决的技术问题是：针对现有技术的缺陷，提供一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，对NPN三极管结构稍作改动，通过对已经成形的纵向NPN管发射极的复合栅结构多晶硅表面，用N+扩散区的掺杂杂质注入的方式，将发射极电阻减小到原来的的1/4左右，且发射极电阻随着发射区面积的增加而呈线性降低。
本发明为解决上述技术问题采用以下技术方案：
一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，最底层为P衬底片，P衬底片上端为N埋层和P埋层，P埋层设置于N埋层的左右两端，P埋层的上端为P阱，N埋层的上端为NPN三极管区域，P阱的上端与NPN三极管区域之间设置为场区；
在NPN三极管区域上，N sinker扩散区、第一N+扩散区、第一接触孔依次连接，作为NPN三极管集电极的引出端；在NPN三极管区域上还设置有作为NPN三极管基区的P base扩散区，P base扩散区的一端设置有P+扩散区，P+扩散区和第二接触孔相连作为NPN三极管基极的引出端；P base扩散区上端还设置有复合栅结构的N型掺杂多晶硅，N型掺杂多晶硅的两端为SPACE侧墙，所述N型掺杂多晶硅由下至上依次包括重掺杂多晶硅、钨硅、多晶硅，在重掺杂多晶硅的下端和Pbase扩散区之间设置有发射区窗口，在复合栅结构的N型掺杂多晶硅的上端注入N型杂质，形成一层第二N+扩散区，复合栅结构的N型掺杂多晶硅和第三接触孔相连，作为NPN三极管发射极的引出端。
作为本发明的进一步优选方案，所述第二N+扩散区被复合栅结构的N型掺杂多晶硅的上表面所包裹。
作为本发明的进一步优选方案，所述第二N+扩散区的面积尺寸大于或等于BiCMOS工艺的光刻特征尺寸。
作为本发明的进一步优选方案，所述第一、第二、第三接触孔内均设置金属布线，集电极、基极、发射极的引出端与金属布线形成欧姆接触。
作为本发明的进一步优选方案，所述NPN三极管区域的外形结构为隔离的N型外延岛。
本发明采用以上技术方案与现有技术相比，具有以下技术效果：在不增加制造成本和牺牲器件性能的前提下，使用本发明所公开的结构可以大大减小多晶硅发射极纵向NPN三极管的发射极电阻，简化模拟电路设计，提高电路性能，提高产品竞争力。
附图说明
图1是本发明所公开的多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构的示意图，
其中：1.P衬底片，2.N埋层，3.P埋层，4.P阱，5.场区，6.N sinker扩散区，7.P base扩散区，8.发射区窗口，9-1.重掺杂多晶硅，9-2.钨硅，9-3.多晶硅，10.SPACE侧墙，11.第一N+扩散区，12.P+扩散区，13.接触孔，14.复合栅结构N型掺杂多晶硅表面的第二N+扩散区。
具体实施方式
本发明实施例之一的具体结构为：在P衬底片上表面的NPN三极管区域是一个隔离的N型外延岛，外延岛下面是N型埋层，一起构成NPN三极管的集电极。N型外延上表面有两个有源区：一个由N sinker扩散区、N+扩散区和N型埋层相连，N+扩散区通过接触孔和金属布线形成欧姆接触，做为集电极的引出端。另外一个有源区包括一层很淡的P base扩散区，形成NPN三极管的基区。第二有源区内部有一小块区域（发射区窗口）表面的二氧化硅是被去掉的，并被复合栅结构N型掺杂多晶硅包围。复合栅结构N型掺杂多晶硅中所掺杂的N型杂质透过薄的多晶硅自然氧化层扩散到下面的有源区中形成很薄的N+扩散区，复合栅结构N型掺杂多晶硅、薄的多晶硅自然氧化层和很薄的N+扩散区共同组成NPN三极管的发射区；复合栅结构N型掺杂多晶硅通过接触孔和金属布线形成欧姆接触，做为发射极的引出端。在P base扩散区的一端设置P+扩散区，P+扩散区通过接触孔和金属布线形成欧姆接触，做为基极的引出端。
本发明中，P+扩散区同时形成了BiCMOS工艺中PMOS器件的源、漏。N+扩散区同时形成了BiCMOS工艺中NMOS器件的源、漏和纵向NPN三极管集电极所需要的N+扩散区。复合栅结构N型掺杂多晶硅的上表面区域注入N型杂质的面积越大，发射极电阻减小的效果越大，基极一端的P+扩散区注入到复合栅结构N型掺杂多晶硅表面的区域需要尽量小。
下面结合附图对本发明的技术方案做进一步的详细说明：
本发明的结构示意图如图1所示，一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，最底层为P衬底片，P衬底片上端为N埋层和P埋层，P埋层设置于N埋层的左右两端，P埋层的上端为P阱，N埋层的上端为NPN三极管区域，P阱的上端与NPN三极管区域之间设置为场区；在NPN三极管区域上，N sinker扩散区、第一N+扩散区、第一接触孔依次连接，作为集电极的引出端；在NPN三极管区域上还设置有P base扩散区，P base扩散区作为NPN三极管的基区，P base扩散区的一端设置有P+扩散区，P+扩散区和第二接触孔相连作为基极的引出端；P base扩散区上端还设置有复合栅结构的N型掺杂多晶硅，复合栅结构的N型掺杂多晶硅的两端为SPACE侧墙，复合栅结构的N型掺杂多晶硅由下至上依次包括重掺杂多晶硅、钨硅、多晶硅，重掺杂多晶硅的下端和Pbase扩散区之间设置发射区窗口，多晶硅的上端部分区域注入N型杂质，形成一层第二N+扩散区，复合栅结构的N型掺杂多晶硅和第三接触孔相连，作为发射极的引出端。
在实际的制造过程中，为了使本发明所公开的NPN三极管结构不影响现有的纵向NPN三极管器件性能，所述第二N+扩散区被复合栅结构的N型掺杂多晶硅的上表面所包裹。所述第二N+扩散区的面积尺寸大于或等于BiCMOS工艺的光刻特征尺寸，N型掺杂多晶硅包住第二N+扩散区的尺寸大于或等于光刻套准精度。
经过实际数据测试，本发明可以将发射极电阻减小到原来的的1/4左右。例如，对一发射区面积为0.6 um× 0.6um多晶硅发射极纵向NPN，采用本发明可以使发射极电阻从原来的约200~300欧姆减小到50~80欧姆。
Claims (5)
1.一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，最底层为P衬底片，P衬底片上端为N埋层和P埋层，P埋层设置于N埋层的左右两端，P埋层的上端为P阱，N埋层的上端为NPN三极管区域，P阱的上端与NPN三极管区域之间设置为场区；
在NPN三极管区域上，N sinker扩散区、第一N+扩散区、第一接触孔依次连接，作为NPN三极管集电极的引出端；在NPN三极管区域上还设置有作为NPN三极管基区的P base扩散区，P base扩散区的一端设置有P+扩散区，P+扩散区和第二接触孔相连作为NPN三极管基极的引出端；P base扩散区上端还设置有复合栅结构的N型掺杂多晶硅，N型掺杂多晶硅的两端为SPACE侧墙，所述N型掺杂多晶硅由下至上依次包括重掺杂多晶硅、钨硅、多晶硅，在重掺杂多晶硅的下端和Pbase扩散区之间设置有发射区窗口，其特征在于：在复合栅结构的N型掺杂多晶硅的上端注入N型杂质，形成一层第二N+扩散区，复合栅结构的N型掺杂多晶硅和第三接触孔相连，作为NPN三极管发射极的引出端。
2.如权利要求1所述的一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，其特征在于：所述第二N+扩散区被复合栅结构的N型掺杂多晶硅的上表面所包裹。
3.如权利要求1所述的一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，其特征在于：所述第二N+扩散区的面积尺寸大于或等于BiCMOS工艺的光刻特征尺寸。
4.如权利要求1所述的一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，其特征在于：所述第一、第二、第三接触孔内均设置金属布线，集电极、基极、发射极的引出端与金属布线形成欧姆接触。
5.如权利要求1所述的一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构，其特征在于：所述NPN三极管区域的外形结构为隔离的N型外延岛。
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| CN101114671A (zh) * | 2006-07-28 | 2008-01-30 | 三洋电机株式会社 | 半导体装置及其制造方法 |
| CN203589039U (zh) * | 2013-10-16 | 2014-05-07 | 无锡市晶源微电子有限公司 | 一种多晶硅发射极BiCMOS工艺中减小发射极电阻的NPN管结构 |
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