CN103516235A - 整流电路 - Google Patents

整流电路 Download PDF

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CN103516235A
CN103516235A CN201310071378.6A CN201310071378A CN103516235A CN 103516235 A CN103516235 A CN 103516235A CN 201310071378 A CN201310071378 A CN 201310071378A CN 103516235 A CN103516235 A CN 103516235A
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electrode
effect transistor
rectifier cell
terminal
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CN103516235B (zh
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西胁达也
吉冈启
齐藤泰伸
新井雅俊
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Toshiba Corp
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Abstract

一种不使用碳化硅等高价半导体材料也能实现反向恢复时间短、高耐压且高可靠性的整流电路。整流电路具备在第1端子及第2端子间串联连接的整流元件及单极场效应晶体管。整流元件具有第1电极及第2电极。在进行直流动作时，当反向偏置时流过整流元件的第1漏电流大于当在场效应晶体管的栅电极及源电极间施加了阈值以下的电压时流过源电极及漏电极的第2漏电流，并且第2漏电流与漏电极及源电极间的电压之间的关系处在场效应晶体管的安全工作区内，在进行交流动作时，当整流元件切换为反向偏置时，在反向偏置的期间内向整流元件的结电容的充电完成，并且充电过程中从整流元件流过场效应晶体管的电流处在场效应晶体管的安全工作区内。

Description

整流电路
本申请要求以日本专利申请第2012－140874号（申请日：2012年6月22日）为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明涉及发挥整流作用的整流电路。
背景技术
提出了将硅的肖特基势垒二极管和常导通（normally on）型的GaN-HEMT（以下简称为HEMT）组合而制作整流电路的技术。利用该技术能够制作与一般的硅的PIN（P-Intrinsic-N）二极管相比反向恢复时间短且高耐压的整流电路。
然而，这种整流电路，当反向偏置时在肖特基势垒二极管中流过反向的漏电流，因此HEMT在弱导通状态下动作，在对HEMT的漏极－源极间施加了高电压的状态下在HEMT中流过漏电流。因此，在肖特基势垒二极管的漏电流大的情况下，会使HEMT在从HEMT的安全工作区（SOA：SafeOperating Area）偏离的区域动作，结果，存在HEMT击穿的问题。
此外，在使上述整流电路进行交流（动态（dynamic））动作的情况下，当整流电路从正向偏置切换为反向偏置时，用于将肖特基势垒二极管的结电容充电的电流会流入到HEMT的漏极－源极间。此时，由于在HEMT的漏极－源极间施加了高电压，所以仍然会使HEMT在从HEMT的安全工作区偏离的区域动作，存在HEMT击穿的问题。
为了应对这些问题，在采用反向漏电流小的肖特基势垒二极管的情况下，对肖特基势垒二极管施加的电压变得过高，肖特基势垒二极管可能会击穿。
发明内容
本发明提供一种即使不使用碳化硅等高价半导体材料也能够实现反向恢复时间较短、高耐压且可靠性高的整流电路。
根据本实施方式，提供一种整流电路，其特征在于，具备在第1端子与第2端子之间串联连接的整流元件以及单极场效应晶体管；上述整流元件具有沿着从上述第1端子朝向上述第2端子流过正向电流的方向配置的第1电极以及第2电极；上述场效应晶体管具有：设定为与上述第1电极相同电位的栅电极；以及与上述整流元件串联连接、流过与上述栅电极的电位相对应的电流的源电极及漏电极；在上述第2端子的电位高于上述第1端子的电位的反向偏置时的上述场效应晶体管的栅电极与漏电极之间的耐压被设定得高于上述整流元件的耐压；上述整流元件及上述场效应晶体管形成为，在进行直流动作的情况下，当上述第2电极的电位变得高于上述第1电极的电位的反向偏置时流过上述整流元件的第1漏电流大于当在上述场效应晶体管的栅电极与源电极之间施加了阈值以下的电压时流过源电极及漏电极的第2漏电流，并且上述第2漏电流与漏电极与源电极间的电压之间的关系处在上述场效应晶体管的安全工作区内；在进行交流动作的情况下，当上述整流元件切换为反向偏置时，在上述反向偏置的期间内向上述整流元件的结电容的充电完成，并且在上述结电容的充电过程中从上述整流元件流向上述场效应晶体管的源电极及漏电极的电流处在上述场效应晶体管的安全工作区内。
附图说明
图1是第一实施方式的整流电路1的电路图。
图2的（a）～（c）是表示采用GaN－FET作为图1的整流电路1内的FET3、采用硅的肖特基势垒二极管作为整流元件2的情况下的电压－电流特性的图。
图3的（a）是将图2（a）所示的FET3的特性曲线和图2（c）所示的整流元件2的特性曲线重叠后的图，图3的（b）是表示动作点偏离了的状态的图。
图4是对图1的整流电路1的端子T1、T2连接了交流电压源4后的电路图。
图5的（a）～（c）是在连接了图4的交流电压源的情况下的图1的整流电路1的各部的波形图。
图6是表示采用GaN－FET3作为FET3的情况下的安全工作区（SOA）的一例的图。
图7的（a）是在图1的整流电路1内的FET3的漏极与端子T2之间连接了电感元件5后的图，（b）是在FET3的源极与整流元件2的阴极之间连接了电感元件5后的图。
图8是将由JBS结构的肖特基势垒二极管2构成的整流元件2和由MIS型的GaN－FET3构成的FET3用分别不同的分立部件构成的整流电路1的剖视图。
图9是表示在同一硅基板上形成了与图8相同结构的肖特基势垒二极管2和GaN－FET3的整流电路1的剖面结构的图。
图10是表示不进行引线键合（wire bonding）工序、利用共通的金属层进行肖特基势垒二极管2与GaN－FET3的布线的情况下的剖面结构的图。
图11是采用了TMBS（Trench MOS Barrier Schottky）结构的肖特基势垒二极管2的整流电路1的剖视图。
图12的（a）～（c）是表示FET3的变形例的剖面结构的图。
图13是第二实施方式的整流电路1的电路图。
图14是将图13的电路图更具体化了的电路图。
图15是表示第二实施方式的整流电路1的动作点的图。
图16的（a）及（b）是表示图14的FET6的第1具体例的图。
图17的（a）及（b）是表示图14的FET6的第2具体例的图。
图18的（a）及（b）是表示图14的FET6的第3具体例的图。
图19是表示第二实施方式的整流电路1内的FET5和FET6的布局配置的俯视图。
具体实施方式
以下，参照附图说明本发明的实施方式。
（第一实施方式）
图1是第一实施方式的整流电路1的电路图。图1的整流电路1在两个端子T1、T2间具备串联连接的整流元件2和单极场效应晶体管（以下称为FET3）。图1的整流电路1中，从端子T1向端子T2的方向是正向偏置方向，从端子T2向端子T1的方向是反向偏置方向。
整流元件2的阳极连接于端子T1，整流元件2的阴极连接于FET3的源极。FET3的漏极连接于端子T2，FET3的栅极连接于整流元件2的阳极和端子T1。
FET3是在不对栅极施加电压的状态下在源极－漏极间流过电流的所谓的常导通型的FET3，作为FET3的具体例，例如能够应用HEMT（HighElectron Mobility Transistor：高电子迁移率晶体管）、MESFET（MetalSemiconductor Field-Effect Transistor：金属半导体场效应晶体管）、MOSFET（Metal-Oxide-Semiconductor Field-Effect Transistor：金属氧化物半导体场效应晶体管）或SIT（Static Induction Transistor：静电感应晶体管）等。
由于对FET3要求高速性，所以作为FET3内的半导体层的材料，采用氮化物半导体、碳化硅、或与硅相比带隙（band gap）大的半导体。本实施方式中，作为FET3，主要说明采用HEMT的例子，而且该HEMT具备含有GaN的半导体层。HEMT由于在结构上没有源极和漏极的区别，所以能够根据需要切换源极和漏极间的电流方向。本说明书中，为了方便，无论FET3的源极－漏极间的电流方向如何，都将FET3的端子T1侧的电极称为源极，将FET3的端子T2侧的电极称为漏极。
本实施方式的FET3以例如GaN作为半导体层的材料的理由是，GaN与硅相比能带大且载流子迁移率高，并且与碳化硅相比价格低。
整流元件2优选结电容小、漏电流也小的整流元件。此外，优选以作为价格低的材料的硅为母材。因此，优选硅的肖特基势垒二极管、硅的PN结二极管、或硅的PIN二极管等。本实施方式中主要说明采用硅的肖特基势垒二极管（SBD）的例子。采用肖特基势垒二极管的理由在于，从原理上讲不发生因少数载流子的累积而引起的反向恢复时间的延迟。
接着，说明本实施方式的整流电路1的动作。图1的整流电路1，在正向偏置时，端子T1的电压比端子T2的电压高，整流元件2的阳极－阴极间流过正向电压，阳极－阴极间的电压以正向电压Vf被限幅（clip）。此外，在FET3的栅极上，由于施加比源极高Vf的电压，所以FET3也成为导通状态，在源极－漏极间流过电流。
由此，图1的整流电路1，在正向偏置时，从端子T1朝向端子T2流过电流，流过的电流量依赖于流过FET3的源极－漏极间的电流。
另一方面，图1的整流电路1，在反向偏置时，由于整流元件2的阴极电位比阳极电位高，所以FET3的源极电位比栅极电位高，FET3向进行截止的方向动作。并且，整流元件2在反向偏置时从阴极朝向阳极流过漏电流。由于该漏电流，FET3的栅极电压被抬升，从FET3的漏极朝向源极流过漏电流，FET3被反馈控制以维持弱导通状态。
优选在反向偏置时流过图1的整流电路1的漏电流尽可能小。因此，需要采用反向偏置时的漏电流小的整流元件2。
图2示出了采用GaN－FET作为图1的整流电路1内的FET3、采用硅的肖特基势垒二极管作为整流元件2的情况下的电压－电流特性。图2中，将端子T1、T2间的电压设为V，将FET3的源极－漏极间的电压设为VDS，将肖特基势垒二极管的阳极－阴极间的电压设为VDi（＝VR），将FET3的栅极电流设为IG，将从端子T2流向FET3的漏极的电流设为ID，将从肖特基势垒二极管的阴极流向阳极的漏电流设为IR。
图2（a）是GaN的FET3的VDS－ID特性曲线图。如图所示，端子T2、T1间的反向偏置电压V越大，漏极电流ID越小。另外，图2（a）记载的Vt是图1的端子T2－T1间的电压。
图2（b）是肖特基势垒二极管的VR－IR特性曲线图。如图所示，若反向电压VR达到电压VB，则成为击穿状态而反向电流IR急剧增大。
图2（c）是将图2（b）的横轴设为VDS＝（V－VDi）的特性曲线图。图2（c）的特性曲线具有将图2（b）的特性曲线以Y轴为对称轴翻转后的形状。
图3（a）将图2（a）所示的FET3的特性曲线和图2（c）所示的整流元件2的特性曲线重叠后的图，这两种特性曲线的交点c成为图1的整流电路1的动作点。
若由于FET3的制造偏差等导致FET3的特性曲线向Y轴的正向偏离，则动作点c偏离到图3（b）那样的位置。该图3（b）的动作点表示出，FET3的漏电流大于整流元件2的反向漏电流。该情况下，在整流元件2的阳极－阴极间施加超过耐压的高电压，整流元件2有可能击穿。
为了防止这样的整流元件2的击穿，在图1的整流电路1的反向偏置时，需要使FET3的漏电流小于流过整流元件2的漏电流。在FET3的漏电流小于流过整流元件2的漏电流的情况下，超过整流元件2的击穿电流的漏电流不会流过FET3，所以不会有在整流元件2的阳极－阴极间施加超过耐压的电压的担忧，能够防止整流元件2的击穿。
此外，流过FET3的漏电流和漏极－源极间电压的关系是，不能超出FET3的安全工作区（SOA）。这是因为，在超出FET3的安全工作区（SOA）的量的漏电流流过FET3的情况下，FET3有可能击穿。
综上，图1的整流电路1作为直流动作而稳定地动作的条件是以下的（1）和（2）。这两个条件都必须满足。
（1）FET3的源极－漏极间的漏电流小于流过整流元件2的漏电流。更具体而言，流过整流元件2的漏电流大于当在FET3的栅极－源极间施加阈值以下的电压时的源极－漏极间的漏电流。
（2）在图1的整流电路1的动作点流过FET3的漏电流与漏极－源极间电压之间的关系不超出FET3的安全工作区（SOA）。
另外，除了上述（1）和（2）的条件以外，当然需要使反向偏置时的整流元件2的耐压（例如30V）小于FET3的栅极－漏极间电压。这是因为，整流元件2的耐压大于FET3的栅极－漏极间电压的情况下，得不到与整流元件2单体相比耐压高的整流电路1。
另一方面，优选为，FET3的栅极－源极间的击穿电压高于反向偏置时的整流元件2的耐压。这是因为，即使假设浪涌（surge）电压等被施加在FET3的栅极－源极间，也能够以整流元件2的反向耐压将FET3的栅极－源极间钳位而进行保护。但是，在噪声少的环境下，不需要一定具备该条件。
在将图1的整流电路1组装入电源电路而使用的情况下，图1的整流电路1交替重复正向偏置动作和反向偏置动作。在进行这样的交流动作（动态动作）的情况下图1的整流电路1稳定动作的条件是以下的（3）和（4）。该（3）和（4）的条件都必须满足。
（3）在反向偏置期间内，向整流元件2的结电容的充电完成。
（4）在向整流元件2的结电容的充电过程中，FET3在安全工作区（SOA）内动作。
以下，说明该（3）和（4）的条件。图4是将交流电压源4连接于图1的整流电路1的端子T1、T2后的电路图，图5是连接了图4的交流电压源的情况下的图1的整流电路1的各部的波形图。图5（a）示出了端子T1、T2间的电压V的波形，图5（b）示出了整流元件2的阳极－阴极间的电压VDi的波形，图5（c）示出了流过整流元件2的电流ID的波形。
图5（a）中，以正的脉冲表示对图1的整流电路1施加反向偏置的情况。若整流电路1从正向偏置切换为反向偏置，则必须将整流元件2的结电容充电，所以整流元件2的阳极－阴极间的电压缓慢上升。此外，由于在整流电路1从正向偏置切换为反向偏置的瞬间在结电容中累积电荷，从整流元件2的阴极朝向阳极流过反向的冲击电流。
若在整流电路1的反向偏置期间内向整流元件2的结电容的充电未完成，则整流元件2无法以重复反向偏置和正向偏置的动作频率进行动作，所以上述的（3）成为必须的要件。此外，在整流电路1刚刚从正向偏置切换为反向偏置后，如图5（c）所示地流过反向的冲击电流，由于该冲击电流还在FET3的漏极－源极间流过，所以必须使偏离FET3的安全工作区（SOA）的电流不流过FET3。因此，上述的（4）也成为必须的要件。
图6是表示采用GaN－FET3作为FET3的情况下的安全工作区（SOA）的一例的图。为了使FET3稳定动作，FET3的动作点必须位于图示的折线所围的范围所示的安全工作区（SOA）的内部。图6中，图示出使FET3进行DC动作的情况下的安全工作区SOA1、和对FET3施加单一脉冲的情况下的安全工作区SOA2，但优选的是，在作为更严格的条件的安全工作区SOA1内设置动作点。图6的图示op示出了动作点存在于从安全工作区偏离了的位置的例子。在该例的情况下，不能保证FET3的动作，FET3有可能击穿。
另外，安全工作区（SOA）由FET3的额定恒流、额定电压以及工作温度等参数决定，所以需要设定FET3和整流元件2的元件参数，使得根据这些参数检测FET3的安全工作区（SOA），使FET3的动作点位于检测出的安全工作区（SOA）内。
这样，图1的整流电路1在直流动作方面需要满足上述（1）和（2）的条件中的任一个，在交流动作方面需要满足上述（3）和（4）的条件中的任一个。
上述的（4）是用来防止由于在图1的整流电路1反向偏置时流过整流元件2的结电容的冲击电流而在FET3中流过安全工作区（SOA）外的漏电流这一情况的条件，用来满足该条件的一个有效的对策是，如图7（a）所示那样在图1的整流电路1内的FET3的漏极和端子T2之间连接电感元件5，或者如图7（b）所示那样在FET3的源极和整流元件2的阴极之间连接电感元件5。
通过在FET3的漏极或源极上连接电感元件5，在FET3的漏极－源极间电流变得难以流动，所以能够抑制冲击电流。
但是，若连接电感元件5，则发生寄生振荡的可能性变高，所以需要优化电感元件5的L值以使得不发生寄生振荡。
如上所述，图1的整流电路1内的FET3和整流元件2所采用的具体的元件的种类并不一定是一种组合，而是可以考虑各种组合。此外，图1的整流电路1内的FET3和整流元件2可以形成在同一半导体基板上，也可以将FET3和整流元件2分别用独立的分立部件构成并安装在例如印刷基板上。
图8是将由JBS（Junction Barrier Schottky：结势垒肖特基）结构的肖特基势垒二极管2构成的整流元件2和由MIS型的GaN－FET3构成的FET3分别用独立的分立部件构成的整流电路1的剖视图。
图8的肖特基势垒二极管2具有：在ｎ＋型硅基板10上形成的n型硅层11，在该n型硅层11的表面以规定间隔形成的多个p型表面层12，由与n型硅层11进行肖特基接触的金属材料构成的阳极电极层13，在阳极电极层13周围形成的绝缘层14，在与阳极电极层13相反的一侧的ｎ＋型硅基板10上形成的阴极电极层15。
图8的GaN－FET3具有：在基板20上形成的缓冲层21，在缓冲层21上形成的GaN层22，在GaN层22上形成的AlGaN层23，在AlGaN层23上隔着绝缘膜24而形成的栅电极层25，在AlGaN层23上在栅电极层25的周围形成的源电极层26以及漏电极层27。
基板20的材料例如是硅、蓝宝石或GaN等。缓冲层21的材料例如是AlGaN／GaN的超晶格异质结构造等。
图8的肖特基势垒二极管2的阳极电极层13用GaN－FET3的栅电极层25和布线图案等连接，肖特基势垒二极管2的阴极电极层15用GaN－FET3的源电极层26和布线图案等连接。
图8的肖特基势垒二极管2在反向偏置时，耗尽层在邻接的p型表面层12的间隔的方向上延伸而容易夹断（pinch off），因此能够使结电容减小，并且能够抑制漏电流。
图9是表示将与图8相同结构的肖特基势垒二极管2和GaN－FET3形成在同一硅基板上的整流电路1的剖面结构的图。图9的整流电路1具备ｎ＋型硅基板10和在该基板10上形成的n型硅层11，在该n型硅层11的表面，以一定间隔形成肖特基势垒二极管2用的p型表面层12，并且形成GaN－FET3用的缓冲层21。
此外，在n型硅层11上形成的氧化膜14与肖特基势垒二极管2用的阳极电极层13接触，并且覆盖GaN－FET3的化合物半导体层21～23的侧壁。
图9的整流电路1能够芯片化，在进行芯片化时，肖特基势垒二极管2的阳极电极层13和GaN－FET3的栅电极层25之间的连接需要通过引线键合进行，肖特基势垒二极管2的阴极电极层15和GaN－FET3的源电极层26之间的连接也需要通过引线键合进行。
相对于此，也可以是，图10的整流电路1不进行引线键合工序，而是通过共通的金属层进行肖特基势垒二极管2和GaN－FET3的布线。
图10的整流电路1的肖特基势垒二极管2和GaN－FET3的基本构造与图8、图9所示的相同，但布线层（电极层）和氧化层（绝缘层14）的配置及形状不同。
更具体而言，在图8和图9的整流电路1中，阴极电极层15夹持ｎ＋型硅基板配置在与阳极电极层13相反的一侧，而在图10的整流电路1中，阴极电极层15配置在阳极电极层13侧。为了实现该配置，在ｎ＋型硅基板10上的n型硅层11中形成接触孔30，在该接触孔30内形成作为阴极电极层而发挥作用的第1布线层31。在该接触孔30的侧壁，分别设置有肖特基势垒二极管2用的氧化层14和用来将GaN－FET3的化合物半导体层的侧壁覆盖的绝缘膜32。
第1布线层31由于经由接触孔30而与ｎ＋型硅基板10接触，所以被用作肖特基势垒二极管2的阴极电极层，并且兼做GaN－FET3的源电极层。
在该第1布线层31之上形成层间绝缘膜33，在该层间绝缘膜33之上形成第2布线层34。该第2布线层34与肖特基势垒二极管2的阳极电极层13连接，并且还与GaN－FET3的栅极连接。
这样，由于图10的整流电路1具备与肖特基势垒二极管2和GaN－FET3这双方连接的第1布线层31和第2布线层34，所以能够省略引线键合的工序，能够简化整流电路1的半导体芯片化工序。
在上述的图8～图10中，示出了采用JBS结构的肖特基势垒二极管2的例子，而以下说明的图11是采用了TMBS（Trench MOS Barrier Schottky：沟道MOS势垒肖特基）结构的肖特基势垒二极管2的整流电路1的剖视图。图11的GaN－FET3的剖面结构与图8～图10的FET3相同。图11的肖特基势垒二极管2与图8的结构的不同点在于，在以一定间隔形成于n型硅层10的表面的沟槽40内，隔着绝缘层41形成电极层42。在TMBS结构的肖特基势垒二极管2中，能够降低n型硅层10与阳极电极层13之间的肖特基结的电场强度，所以能够抑制肖特基势垒二极管2的反向偏置时的漏电流。此外，由于耗尽层容易延伸，所以能够减小结电容。
如上所述，关于用来使图1的整流电路1稳定动作的条件，在直流动作中需要满足上述的（1）和（2）的条件，在交流动作中需要满足上述的（3）和（4）的条件。为了满足这些条件，优选的是，整流元件2的反向偏置时的漏电流在大于在FET3的栅极－源极间施加阈值电压以下的电压时的FET3的漏极－源极间的漏电流的范围内尽可能小。更具体而言，例如，优选成为几μ安培以下的漏电流。因此，上述的JBS结构、TMBS结构的肖特基势垒二极管2是有效的。
此外，优选使整流元件2的结电容尽可能小。更具体而言，优选使结电容例如为100pF以下。但是，若为了降低结电容而减小元件面积则导通时的电阻增大，电路的损失增加。因此，对于上述的导通时的电阻，能够减小结电容的JBS结构、TMBS结构的肖特基势垒二极管2是有效的。
此外，关于FET3，也优选漏极－源极间的漏电流尽可能小。为此，可以考虑在图8～图10所示的FET3内形成用来阻挡（block）漏电流的AlGaN层，或通过向缓冲层内注入杂质离子而进行高电阻化来抑制漏电流的对策。
例如，图12（a）是在图8～图10所示的FET3内的缓冲层21和GaN层22之间插入AlGaN层28、由该AlGaN层28、GaN层22以及AlGaN层23形成AlGaN／GaN／AlGaN双异质结结构的FET3的剖视图。新插入的AlGaN层28发挥将漏电流阻挡的作用，所以能够抑制漏极－源极间的漏电流。
图12（b）是具有GaN层21a的FET3的剖视图，该GaN层21a是在作为图8～图10所示的FET3内的缓冲层21的材料的非掺杂的n型GaN中注入Mg、C、Fe等对传导载流子进行了补偿的、或通过注入的掺杂剂形成深能级而被高电阻化了的GaN层。
此外，图12（c）是图12（b）的变形例，是将缓冲层21做成AlGaN／GaN／掺杂GaN的异质结结构层21b的FET3的剖视图。
上述的图8～图10的FET3能够采用图12（a）～图12（c）中任一个的剖面结构。
这样，在第一实施方式中，在将整流元件2和FET3串联连接形成整流电路1时，设计整流元件2和FET3以使得在直流动作方面满足上述的（1）和（2）的条件、在交流动作方面满足上述的（3）和（4）的条件，因此能够防止反向偏置时在整流元件2的阳极－阴极间施加过度的电压及FET3从其安全工作区（SOA）偏离而动作这样的情况，整流元件2及FET3难以击穿，并且整流元件2的结电容的充电也能够高速化。因此，根据本实施方式，能够制作反向恢复时间短、高耐压且耐久性良好的整流电路1。
特别是，在本实施方式中，采用比碳化硅廉价的半导体材料（例如GaN）由FET3和采用硅的整流元件2（例如硅的肖特基二极管）构成整流电路1，因此与采用碳化硅那样的高价半导体材料构成整流电路1的情况相比，能够大幅消减部件成本。此外，与采用碳化硅构成的整流电路1相比，反向恢复时间、耐压及耐久性等电特性也不差。
（第二实施方式）
以下说明的第二实施方式是使整流元件2和FET3的动作更加稳定化的实施方式。
图1的整流电路1在反向偏置状态时，在整流元件2中流过反向漏电流，所以FET3的栅极电压成为阈值电压附近而以弱导通状态动作。因此，在对该FET3的漏极－源极间施加了高电压的状态下，如图2（a）所示那样在漏极－源极间流过漏电流。
由于这样的理由，如图3所示那样，对FET3的漏极－源极间和整流元件2施加的电压的动作点原本就容易变得不稳定。若动作点变动，则如图3（b）所示那样对整流元件2施加过大电压而发生击穿，或在FET3中流过超出安全工作区的程度的过大电流而发生击穿。
在上述的第一实施方式中，为了防止上述不良，说明了对整流元件2和FET3进行设计以使得在直流动作方面满足上述（1）和（2）的条件、在交流动作方面满足上述（3）和（4）的条件的例子。
相对于此，第二实施方式在电路结构方面进行研究，从而使得满足上述（1）～（4）的条件。
图13是第二实施方式的整流电路1的电路图。图13的整流电路1在图1的整流电路1中追加了恒流源6。该恒流源6并联连接在FET3的漏极－源极间。
图14是表示将图13的恒流源6更具体化了的一例的整流电路1的电路图。图14的恒流源6通过将常导通型的FET6的栅极连接到源极而构成。或者，恒流源6也可以是沟道的一部分狭窄的常导通型的FET。本实施方式中，流过恒流源6的电流、即FET6的漏极－源极间电流在不超出整流元件2的漏电流的范围内设定为尽可能接近漏电流的值。此外，构成恒流源6的FET6的漏极－源极间耐压设定得与FET3相同或在其以上。
图13的整流电路1中，在反向偏置状态时，流过整流元件2的漏电流由于从恒流源6供给，所以FET3基本成为截止状态。因而，FET3的动作不会偏离安全工作区。
此外，由于恒流源6的电流值是一定的，所以动作点不会变动，能够防止因动作点的移动导致的整流元件2的击穿。
图15是表示本实施方式的整流电路1的动作点的图。如图所示，恒流源6的电流值总是一定的，作为恒流源6与整流元件2之间的交点的动作点不变化。
另外，在图13及图14中，将恒流源6的一端连接到FET3的漏极，但恒流源6的一端不需要一定连接到FET3的漏极，例如也可以将该一端设定为规定的电压。
图16是表示图14的FET6的第1具体例的图，图16（a）是剖视图，图16（b）是俯视图。图16的FET6是常导通型的GaN－HEMT。该FET6是在由硅、蓝宝石、GaN等构成的基板51上将缓冲层52、GaN层53、二维电子气层54以及AlGaN层55依次层叠而成的结构。在AlGaN层55之上，形成绝缘膜56、栅极G、源极S以及漏极D。通过将在AlGaN层55之上形成的栅极G和源极S电连接，FET6的漏极电流不依赖于漏极电压而示出饱和的特性，所以作为恒流源6进行动作。
与恒流源6的恒流相当的FET6的漏极电流的电流值能够通过调整沟道宽度来控制。沟道宽度能够通过向沟道57的杂质离子的注入量及蚀刻等来调整。
另外，取代GaN－HEMT，FET6也可以是GaN－MOSFET、SiC－JFET或Si－JFET等。
图17是表示图14的FET6的第2具体例的图，图17（a）是剖视图，图17（b）是俯视图。图17的FET6中，AlGaN层55的结构与图16不同，AlGaN层55下侧的层叠结构与图16相同。
图17的AlGaN层55的一部分在幅宽度方向上通过凹陷（recess）蚀刻形成凹部58。通过该凹部58来调制二维电子气层54的密度。通过调整凹部58的尺寸、形状，能够控制与恒流源6的恒流相当的FET6的漏极电流。凹部58可以将AlGaN层55蚀刻得完全穿透来形成，也可以不蚀刻得穿透来形成。FET6的漏极电流不仅能够根据AlGaN层55的蚀刻量来调整，也能够通过改变在AlGaN层55之上形成的绝缘膜56的膜厚来调整。在图17的例子中，FET6用的栅极可以形成，也可以不形成。
图18是表示图14的FET6的第3具体例的图，图18（a）是剖视图，图18（b）是俯视图。图18的FET6具备将上述的第1具体例和第2具体例组合的结构。即，图18的FET6中，在形成于AlGaN层55的一部分的凹部58上，形成栅极G。图18的FET6中，通过进行沟道宽度的调整和形成于AlGaN层55的凹部58的尺寸、形状的调整，能够控制与恒流源6的恒流相当的FET6的漏极电流。
图17所示的第2具体例的FET6的栅极不是必须的，但图18的FET6中栅极是必须的。栅极在AlGaN层55内的凹部58之上隔着绝缘膜56形成。
图19是表示本实施方式的整流电路1内的FET5和FET6的布局配置的俯视图。该图的FET6可以是上述的第1～第3具体例中的任一个。如图所示，FET5和FET6在一个方向上排列形成。由此，能够共用源极，并且还能够共用漏极，能够以较少的布局面积形成。这样，在第二实施方式中，在第一实施方式的整流电路1中新追加恒流源6，反向偏置时流过整流元件2的漏电流基本从恒流源6供给，所以动作点不移动，能够更可靠地防止FET3和整流元件2的击穿。
本发明的实施方式不限于上述各个实施方式，还包含本领域技术人员能想到的各种变形，本发明的效果也不限于上述内容。即，在不脱离从权利要求的范围所规定的内容及其等同物导出的本发明的概念性思想和主旨的范围内，能够进行各种追加、变更以及部分的删除。

Claims (13)

1.一种整流电路，其特征在于，
具备在第1端子与第2端子之间串联连接的整流元件以及单极场效应晶体管；
上述整流元件具有沿着从上述第1端子朝向上述第2端子流过正向电流的方向配置的第1电极以及第2电极；
上述场效应晶体管具有：
设定为与上述第1电极相同电位的栅电极；以及
与上述整流元件串联连接、流过与上述栅电极的电位相对应的电流的源电极及漏电极；
在上述第2端子的电位高于上述第1端子的电位的反向偏置时的上述场效应晶体管的栅电极与漏电极之间的耐压被设定得高于上述整流元件的耐压；
上述整流元件及上述场效应晶体管形成为，
在进行直流动作的情况下，当上述第2电极的电位变得高于上述第1电极的电位的反向偏置时流过上述整流元件的第1漏电流大于当在上述场效应晶体管的栅电极与源电极之间施加了阈值以下的电压时流过源电极及漏电极的第2漏电流，并且上述第2漏电流与漏电极和源电极间的电压之间的关系处在上述场效应晶体管的安全工作区内；
在进行交流动作的情况下，当上述整流元件切换为反向偏置时，在上述反向偏置的期间内向上述整流元件的结电容的充电完成，并且在上述结电容的充电过程中从上述整流元件流向上述场效应晶体管的源电极及漏电极的电流处在上述场效应晶体管的安全工作区内。
2.一种整流电路，其特征在于，
具备在第1端子与第2端子之间串联连接的整流元件以及单极场效应晶体管；
上述整流元件具有沿着从上述第1端子朝向上述第2端子流过正向电流的方向配置的第1电极以及第2电极；
上述场效应晶体管具有：
设定为与上述第1电极相同电位的栅电极；以及
与上述整流元件串联连接、流过与上述栅电极的电位相对应的电流的源电极及漏电极；
在上述第2端子的电位高于上述第1端子的电位的反向偏置时的上述场效应晶体管的栅电极与漏电极之间的耐压被设定得高于上述整流元件的耐压；
上述整流元件及上述场效应晶体管形成为，当上述反向偏置时流过上述整流元件的第1漏电流大于当在上述场效应晶体管的栅电极与源电极之间施加了阈值以下的电压时流过源电极及漏电极的第2漏电流，并且上述第2漏电流与漏电极和源电极间的电压之间的关系处在上述场效应晶体管的安全工作区内。
3.一种整流电路，其特征在于，
具备在第1端子与第2端子之间串联连接的整流元件以及单极场效应晶体管；
上述整流元件具有沿着从上述第1端子朝向上述第2端子流过正向电流的方向配置的第1电极以及第2电极；
上述场效应晶体管具有：
设定为与上述第1电极相同电位的栅电极；以及
与上述整流元件串联连接、流过与上述栅电极的电位相对应的电流的源电极及漏电极；
在上述第2端子的电位高于上述第1端子的电位的反向偏置时的上述场效应晶体管的栅电极与漏电极之间的耐压被设定得高于上述整流元件的耐压；
上述整流元件及上述场效应晶体管形成为，当上述整流元件切换为反向偏置时，在上述反向偏置的期间中向上述整流元件的结电容的充电完成，并且在上述结电容的充电过程中从上述整流元件流过上述场效应晶体管的源电极及漏电极的电流处在上述场效应晶体管的安全工作区内。
4.一种整流电路，其特征在于，
具备：
在第1端子与第2端子之间串联连接的整流元件以及单极场效应晶体管；以及
恒流源，能够在上述第2端子的电位高于上述第1端子的电位的反向偏置的期间内提供流过上述整流元件的漏电流；
上述整流元件具有沿着从上述第1端子朝向上述第2端子流过正向电流的方向配置的第1电极及第2电极；
上述场效应晶体管具有：
设定为与上述第1电极相同电位的栅电极；以及
与上述整流元件串联连接、流过与上述栅电极的电位相对应的电流的源电极及漏电极；
当上述第2端子的电位高于上述第1端子的电位的反向偏置时上述场效应晶体管的栅电极与漏电极之间的耐压设定得高于上述整流元件的耐压；
对于上述整流元件及上述场效应晶体管，当上述反向偏置时流过上述整流元件的第1漏电流大于当在上述场效应晶体管的栅电极与源电极之间施加了阈值以下的电压时流过源电极及漏电极的第2漏电流。
5.如权利要求4记载的整流电路，其特征在于，
上述恒流源并联连接在上述单极场效应晶体管的漏极与源极之间。
6.如权利要求4或5记载的整流电路，其特征在于，
上述恒流源是源极及栅极被连接的常导通型的场效应晶体管。
7.如权利要求4或5记载的整流电路，其特征在于，
上述恒流源是沟道的一部分狭窄的常导通型的场效应晶体管。
8.如权利要求1～5中任一项记载的整流电路，其特征在于，
当上述第2端子的电位高于上述第1端子的电位的反向偏置时的上述场效应晶体管的栅电极与源电极之间的击穿电压被设定得高于上述整流元件的耐压。
9.如权利要求1～5中任一项记载的整流电路，其特征在于，
具备电感元件，该电感元件沿着流过反向电流的路径与上述场效应晶体管的漏电极及源电极中的至少一个连接。
10.如权利要求1～5中任一项记载的整流电路，其特征在于，
上述整流元件是硅的肖特基势垒二极管、硅的PN结二极管、或硅的PIN二极管。
11.如权利要求5记载的整流电路，其特征在于，
上述肖特基势垒二极管是JBS结构或TMBS结构。
12.如权利要求1～5中任一项记载的整流电路，其特征在于，
上述场效应晶体管是常导通型的HEMT、MESFET、MOSFET或SIT。
13.如权利要求1～5中任一项记载的整流电路，其特征在于，
上述场效应晶体管采用带隙比氮化物半导体、碳化硅或硅大的半导体形成。
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