CN103392234B - 硅纳米管mosfet - Google Patents
硅纳米管mosfet Download PDFInfo
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Abstract
一种纳米管MOSFET器件及其制作方法用来延伸器件缩减规划而又维持良好短沟道效应并且提供有竞争力的驱动电流。纳米管MOSFET器件包括:同心管形内(61)和外栅极(50),被管形成形的外延生长的硅层相互分离;以及源极(35)和漏极(31),分别被包围管形内和外栅极的间隔物(51,41)分离。形成纳米管MOSFET器件的方法包括:在衬底上形成圆柱形成形的Si层(30);形成包围圆柱形Si层(30)并且在底部间隔物(41)与顶部间隔物(51)之间定位的外栅极;在顶部间隔物上生长与圆柱形成形的Si层的部分相邻的硅外延层;蚀刻圆柱形成形的Si的内部分从而形成空心圆柱体;在内圆柱体的底部形成内间隔物;通过填充空心圆柱体的部分来形成内栅极;形成与内栅极相邻的侧壁间隔物;并且蚀刻用于接入和接触外栅极和漏极的深沟槽。
Description
技术领域
本发明涉及金属氧化物半导体管形场效应晶体管(MOSFET)结构,并且更具体地涉及一种Si纳米管MOSFET器件及其制造方法。
背景技术
基于硅的金属氧化物半导体场效应晶体管(MOSFET)的连续缩减已经有助于半导体技术的不断发展。随着器件标度逼近纳米范围,半导体器件的进一步升级面临各种挑战。一些挑战源于在原子尺度的材料性质诸如的量子机械性质,诸如栅极隧道电流。一些其它挑战源于材料性质的随机性质,诸如在微观标度的掺杂物浓度波动以及在半导体结的所得阈值电压和漏电流展开。半导体技术这些挑战和其它挑战已经恢复对具有非常规几何形状的半导体器件的兴趣。
为了增强互补金属氧化物半导体(CMOS)器件的性能而开发的并且在高级半导体器件中广泛使用的一种技术解决方案是绝缘体上硅(SOI)技术。尽管SOI MOSFET通常赋予较具有可比较尺度并且通过在本体与其它MOSFET部件之间提供更高接通电流和更低寄生电容在体衬底上构建的MOSFET而言的优点,但是SOI MOSFET往往由于“历史效应”或者“浮置本体效应”而在器件操作中具有更少一致性,在该效应中,本体的电势并且可能SOIMOSFET的接通定时和接通电流依赖于SOI-MOSFET的以往历史。另外,漏电流电平也依赖于浮置本体的电压,这在低功率SOI MOSFET的设计中带来挑战。
SOI MOSFET的本体存储依赖于器件历史的电荷,因此变成“浮置”本体。这样,SOIMOSFET表现难以预期和控制并且随时间变化的阈值电压。本体电荷存储效应造成动态亚阈值电压(亚Vt)泄漏和在几何形状相同的相邻器件之间的阈值电压(Vt)未匹配。
在诸如静态随机存取存储器(SRAM)单元之类的应用中尤为关注SOI MOSFET中的浮置本体效应,在这些应用中,阈值电压(Vt)匹配随着操作电压继续下降而极为重要。浮置本体也带来传输门器件的泄漏问题。其中关注复制本体效应的另一示例半导体器件是如在逻辑门中使用的侵蚀型SOI MOSFET结构,在这些结构中,在堆叠中向上更高的SOI MOSFET器件的传导状态受存储的本体电荷强烈地影响从而造成减少可用于这些器件的栅极到源极电压过驱动。其中浮置本体控制至关重要的更多其它示例实施例是用于电流监视电路中的SRAM电路和电流驱动的感测放大器。
与SOI MOSFET关联的另一问题涉及高电流流量由于I2R定律而引起的自加热。由于BOX具有更低导热率,所以SOI中的热量继续增长从而引起载流子到载流子散射,这又导致驱动电流下降。
鉴于上文,存在对能够最小化浮置本体效应、自加热效应以便提供一致性能的半导体器件的需要。另外,存在对一种有利地运用浮置本体效应以执行有用功能的半导体结构及其新制造方法的需要。此外,在业内存在对一种较现有半导体器件而言能够通过例如增加每单位器件面积的接通电流来提高性能的半导体器件的需要。
附图说明
将结合附图最好地理解以下具体描述,通过示例给出而未旨在于使本发明限于该具体描述,在附图中:
图1示出纳米管FET器件的初始制造过程步骤的侧视图的截面,该图示出SOI衬底;
图2是在SOI衬底的顶表面上沉积的覆盖硬掩模层的侧视图的截面图;
图3描绘向下竖直蚀刻顶部层的一部分从而留下台面结构,该台面结构具有由上述覆盖层的二维形状预定的结构的形状;
图4示出通过沉积氧化物并且蚀刻背面来创建的牺牲氧化硅层;
图5图示形成管的外侧;
图6示出在半导体结构的表面上和在覆盖台面的顶部上形成的外栅极氧化物电介质;
图7描绘在电介质层上沉积外栅极电极;
图8示出部分地去除外栅极电极和栅极氧化物电介质层、继而沉积电介质层以形成间隔物;
图9描绘牺牲层包围上述电介质层,继而平坦化;
图10图示部分地去除上述电介质从而暴露覆盖物;
图11图示去除剩余牺牲层,继而通过横向外生长来生长单硅层;
图12示出部署和平坦化TEOS层;
图13示出所有层暴露台面;
图14描绘通过若干层挖掘沟槽以形成空心管;
图15图示在沟槽的竖直壁上沉积栅极电介质层而在沟槽的水平底表面上形成电介质层;
图16图示通过用传导材料填充沟槽来形成的内栅极;
图17示出在准备形成接触时部署电介质层、形成包围内栅极的侧壁间隔物;
图18和图19示出其中已经形成接触的最终Si纳米管器件的侧视图,该Si纳米管器件包括填充在接触之间的空间的电介质层,其中图18示出沿着标注为A-A’的切割线(见图20)的侧视图,而图19示出沿着标注为B-B’的切割线(见图20)的侧视图;
图20示出俯视图,该俯视图描绘本发明的最终结构的一个实施例,该图示出源极、漏极、内栅极和外栅极以及在它们之间用电介质填充的空间;
图21是完成的纳米管MOSFET的3D透视图,该图图示内和外栅极,示出后者分别被间隔物从FET的漏极和源极分离;并且
图22示出纳米管MOSFET的又一3D透视图,其中内栅极由管形内栅极氧化物包围,该内栅极氧化物又由管形Si层包围。为了清楚起见,去除源极层。
发明内容
在本发明的一个实施例的一个方面中,在具有内栅极和外栅极的管形配置中提供一种金属半导体场效应晶体管(MOSFET)。在一个实施例中,该方法包括形成具有高掺杂的材料层的竖直管形的硅上硅。高掺杂的区域有利地用作管形晶体管的漏极侧延伸区域。沉积硬掩模以限定管的内区域。使用反应离子蚀刻(RIE)和选择性蚀刻的序列来形成由栅极电介质(常规SiO2或者高K)和栅极材料(多晶硅或者金属栅极)构成的外栅极堆叠。使用RIE来形成管的内区域。继而离子注入以形成源极或者漏极延伸。在内管中,沉积电介质和栅极材料以形成内栅极堆叠。通过使用自对准来外延生长Si以形成源极区域。最后使用自对准和深沟槽蚀刻来使内栅极、外栅极、源极和漏极硅化物化并且形成接触。
在一个实施例的一个方面中,内栅极电极和外栅极电极可以相对于管形半导体结构的本体用相同电压极性操作,以在管的两侧上产生反转层并且减少浮置本体效应并且实现更严密沟道控制。备选地,内栅极电极和外栅极电极可以相对于管形半导体结构的源极用相反极性操作,以在管形半导体结构的一侧上产生反转层而在另一侧上产生累积层,从而放大浮置本体效应并且纳米管晶体管可以作为存储器器件存储电荷。
在又一方面中,本发明的一个实施例提供一种纳米管MOSFET器件,该纳米管MOSFET器件包括:管形Si层包围的管形内栅极;包围Si层的管形外栅极;以及源极和漏极,分别被包围管形内栅极和外栅极的间隔物分离。
在又一方面中,一个实施例提供一种形成纳米管MOSFET器件的方法,该方法包括:在衬底上形成圆柱形的Si层;形成包围圆柱形Si层并且在底部间隔物与顶部间隔物之间定位的外栅极;在顶部间隔物上生长与圆柱形的Si层的部分相邻的硅外延层;蚀刻圆柱形成形的Si的内部分从而形成空心圆柱体;在内圆柱形的底部形成内间隔物;通过填充空心圆柱体的部分来形成内栅极;形成与内栅极相邻的侧壁间隔物;并且蚀刻用于取用和接触外栅极和漏极的深沟槽。
具体实施方式
这里公开本发明的具体实施例;然而将理解,公开的实施例仅举例说明可以在各种形式中体现的本发明。此外,结合本发明的各种实施例给出的示例中的每个示例旨在于示例而非限制。另外,附图未必按比例,可以夸大一些特征以示出特定部件的细节。因此,将不解释这里公开的具体结构和功能细节为限制而仅为用于教导本领域技术人员不同地运用本发明的有代表的基础。
参照图1,图示侧视图,该图在一个实施例中示出限定、图案化和蚀刻绝缘体上半导体(SOI)部分以形成本MOSFET器件的SOI衬底。SOI衬底优选地包括操纵衬底10、绝缘体层20、‘掩埋’半导体层31和‘本体’半导体层30。使用半导体材料、金属材料或者绝缘材料来形成操纵衬底10。绝缘体层20优选地由材料(诸如电介质氧化物和/或电介质氮化物)制成。掩埋层31是充当传导电介质层的高掺杂(即传导)的单晶半导体材料。层30和31为结晶兼容材料,例如硅和硅锗、Si和SiGe或者III-V族兼容材料,诸如GaAs-InGaAs。构思不同结晶取向。可以按照已知工艺使层31自对准多晶硅化。
提供SOI部分的SOI层可以包括任何半传导材料,该半传导材料包括但不限于Si、应变Si、SiC、SiGe、SiGeC、Si合金、Ge、Ge合金、GaAs、InAs和InP或者其任何组合。可以通过平坦化、研磨、湿法蚀刻、干法蚀刻或者其任何组合将SOI层减薄成所需厚度。一种减薄SOI层的方法是通过热干法或者湿法蚀刻工艺、然后使用氢氟酸混合物来湿法蚀刻氧化物层。可以重复这一工艺以实现所需厚度。
在一个实施例中,SOI层具有范围从1.0nm至20.0nm的厚度。在另一实施例中,SOI层具有范围从2.0nm至10.0nm的厚度。在又一实施例中,SOI层具有范围从3.0nm至5.0nm的厚度。注意仅出于示例的目的而提供用于SOI层的上述厚度,因为已经构思并且可以在本方法和结构中运用用于SOI层的厚度。
半传导层30可以是包括但不限于以下各项的半传导材料:Si、应变Si、SiC、SiGe、SiGeC、Si合金、Ge、Ge合金、GaAs、InAs、InP以及其它III/V和II/VI化合物半导体。
可以通过向SOI衬底中注入高能掺杂物并且然后使结构退火以形成高掺杂的区域来形成可以在SOI层下面和在电介质层20上面存在的半导体层31。如以上描述的那样,通过使用热退火经过半导体层30的离子注入或者气相掺杂向半导体材料引入掺杂物。在另一实施例中,可以在半导体层30上面沉积或者生长半导体层31。在又一实施例中,可以使用晶片键合技术来形成SOI衬底10,其中利用胶合、粘合聚合物或者直接键合来形成键合的晶片对。
可以使用沉积、光刻和选择性蚀刻工艺从SOI层形成SOI部分。具体而言,通过向待蚀刻的表面涂敷光致抗蚀剂、使光致抗蚀剂暴露于辐射图案、然后利用抗蚀剂显影剂向光致抗蚀剂中显影图案来创建图案。图案具有选择性蚀刻工艺的所需最终结构的几何形状。一旦完成光致抗蚀剂的图案化,保护光致抗蚀剂覆盖的节段而使用去除未保护区域的选择性蚀刻工艺来去除暴露的区域。
参照图2,在层30上面形成覆盖层40。覆盖材料可以是氮化物、氮化硅、氮氧化硅等。向部分40中光刻图案化并且化学处理层40,该部分具有圆形的二维形状和竖直侧壁。其它二维形状(诸如椭圆形、方形、矩形和多面形)是可能的。假设层40优选地采用也称为圆形/管形点阵的圆形形状。层40的厚度优选地约为50nm。层40充当保护层和如下锚固层二者,将从锚固层限定并且在自对准制作工艺中在该锚固层上对准器件。
参照图3,在形成层40之后,竖直向下蚀刻层30的部分,从而形成包括层30、32和40的台面结构,其中层30和32由相同材料(优选为单晶硅)制成。结构的形状由40的二维形状预限定。用于执行竖直蚀刻的方法包括RIE、组合的湿法蚀刻和干法蚀刻以及其它各向异性蚀刻工艺。可以执行附加处理步骤(例如氢退火)以调和竖直半导体壁并且减少它的粗糙。
参照图4,在氮化物点阵层40和层32周围构建覆盖它们的圆形牺牲侧壁21,该侧壁优选地由在层30邻接的单晶硅制成。使用电介质材料(诸如氧化物或者氮化物)来形成层21。用于构建高密度侧壁的方法在本领域中公知,例如使用氧化物沉积、平坦化以及使用湿法和干法(RIE)蚀刻组合的回蚀工艺。层21的厚度优选地为约5至10nm级。
参照图5,在形成结构21之后,通过沿着层30的侧面蚀刻并且通过在与图3中描述的工艺相似的工艺中部分地蚀刻掉层310的未被层21覆盖的部分来形成管的外侧。层31被蚀刻的深度是用于优化器件性能的关键参数。关键的是执行调和工艺(诸如氢退火)以保证平滑而均匀的竖直壁。值得注意的是半导体层31是与半导体层30比较的高掺杂物浓度区域。
参照图6,在半导体结构30和31的表面上以及在层21和40上面形成外栅极氧化物电介质22、24和41。栅极电介质在结构30和31的竖直壁处邻接。在结构31的水平表面上形成栅极到漏极隔离层41。层22和41可以是相同电介质材料。层22的厚度约为1至10nm,优选地从1.0至3nm。层41的厚度近似为1nm至30nm,优选地3nm至10nm。可以使用热氧化和/或热氮化工艺来同时形成层22和41。类似地,优选地也与层22和41并行地沉积层24。此外,可以使用本领域已知的各向异性沉积技术(诸如CVD、高密度等离子体辅助沉积(HPD)、原子层沉积(ALD)、液体源雾化化学沉积(LSMCD)等之一)来增加41的厚度。
参照图7,在层21、22、41和24上面沉积外栅极电极50。使用的材料包括半导体材料、传导合金或者金属。使用的优选材料是多晶硅,但是也构思其它传导材料。前述层的形成包括已知技术,诸如LPCVD、ALD等。材料全覆盖结构,从而可以在下一步骤中安全地应用平坦化过程。
参照图8,首先使用平坦化过程并且其次使用干法蚀刻工艺、诸如RIE来部分地去除层50。可以执行附加退火以控制作为器件的外栅极来工作的剩余层50的厚度。然后沉积电介质材料(层51)、诸如氮化物、氮氧化硅或者氧化硅。层51旨在于充当间隔物。
现在参照图9,使用与层510比较具有不同蚀刻速率的多晶硅锗合金作为优选材料以选择性地蚀刻层51来沉积、继而平坦化包围覆盖层51的牺牲材料层60。
参照图10,优选地首先通过暴露层40的化学机械抛光(CMP)工艺来部分地去除层51。接着使用例如湿法蚀刻或者RIE来蚀刻电介质材料51,从而部分地暴露硅层30和32。然后对暴露的层30和32执行离子注入。注入的目的是形成源极延伸区域并且形成延伸物和栅极的良好重叠。
参照图11,通过选择性RIE蚀刻工艺去除剩余层60。然后优选地通过原位掺杂工艺通过横向外生长来生长单硅层35。高掺杂该层以减少寄生电阻。掺杂浓度在1e19与1e21cm-3、优选地从1e20到5e20cm-3之间变化。
参照图12,沉积并且通过CMP平坦化并且化学清理电介质层27,优选为TEOS。电介质层与层40和42比较可以具有不同蚀刻速率以允许选择性蚀刻。暴露层40以便在下一步骤中被去除。
参照图13,使用标准选择性蚀刻工艺来去除层40,继而去除层32。
参照图14,通过层30并且部分地通过层31挖掘沟槽。在这一阶段,以空心圆柱形或者管的形状形成独特半导体拓扑。用外栅极氧化物(层22)和外栅极材料(层50)包围管的外侧。
参照图15,在沟槽内的层30的竖直壁上沉积栅极电介质层25。在沟槽内的层31的水平(底)表面上形成电介质层26。两层25和26可以由相同电介质材料制成。层25的厚度范围从1nm至10nm、优选地从1.5nm至3nm,而层26的厚度范围在1nm至30nm并且优选地10nm至20nm之间。可以使用热氧化和/或热氮化过程来同时部署层25和26。此外,可以使用本领域已知的各向异性沉积技术(诸如CVD、高密度等离子体辅助沉积(HPD)、原子层沉积(ALD)、液体源雾化化学沉积(LSMCD)等之一)来增加氧化物厚度25。
参照图16,通过用传导材料。诸如多晶硅或者其它金属填充沟槽来形成内栅极61。如果需要,则可以在填充沟槽之前部署栅极盖层。有利地通过CMP抛光该结构、继而部分地回蚀氧化物层25以形成所需拓扑结构。在这一阶段,形成预计的空心圆柱形半导体,并且它被内和外栅极堆叠夹在中间。这一独特拓扑结构形成管形形状。这样形成的(即具有陈述的形状的)MOSFET称为半导体纳米管MOSFET。在半导体是硅的特殊情况下,将它称为Si纳米管MOSFET。
在图17中,在准备形成接触时部署电介质层28。在各向同性蚀刻之后,侧壁间隔物包围内栅极61。参照图18和19,描绘根据标准自对准过程形成的接触。
图20是图示本发明的一个实施例的最终结构的俯视图,该图示出与源极35、漏极31、内栅极61和外栅极50产生的接触以及用电介质填充的空间70。
图21是完成的纳米管MOSFET的部分的3D透视图,该图部分地示出定位于30与35之间的层、即41、50和51。图21示出基于图18的透视图,其中为了清除而省略接触。
图22基于图21,该图示出纳米管MOSFET器件的另一3D透视图,其中省略层35以便显示内栅极电介质及其邻接层。
尽管已经结合简单示例实施例具体描述本发明,但是将理解本领域普通技术人员可以用许多明显方式延伸和应用本发明。本发明的其它实施例可以与之适应。不言而喻,许多备选、修改和变化将鉴于本说明书而为本领域技术人员所清除。因此构思所附权利要求将涵盖如落入本发明的真实范围和精神实质内的任何这样的备选、修改和变化。
工业实用性
本发明发现在集成电路芯片中并入的硅金属氧化物半导体场效应晶体管(MOSFET)器件的设计和制作中的工业实用性,这些集成电路发现在大量多种电子和电气装置中的应用并且特别好地适合于移动电话。
Claims (24)
1.一种纳米管MOSFET器件,包括:
圆柱形的内栅极和管形的外栅极(61,50),被Si层(30)相互分离,所述外栅极在底部间隔物(41)与顶部间隔物(51)之间定位;
源极(35)和漏极(31),分别被包围所述内栅极和外栅极的顶部间隔物(51)和底部间隔物(41)分离;
所述源极是在所述顶部间隔物(51)上形成的与所述Si层(30)的部分相邻的硅外延层;
在所述圆柱形的内栅极的底部形成的内间隔物。
2.如权利要求1所述的纳米管MOSFET器件,还包括与所述内栅极和外栅极以及所述源极和漏极一体的硅衬底。
3.如权利要求2所述的纳米管MOSFET器件,其中所述衬底是SOI衬底。
4.如权利要求2所述的纳米管MOSFET器件,其中所述衬底由体硅制成。
5.如权利要求1所述的纳米管MOSFET器件,其中所述Si层具有管形形状。
6.如权利要求3所述的纳米管MOSFET器件,其中所述SOI衬底包括具有范围从1.0nm至20nm的厚度的层。
7.如权利要求1所述的纳米管MOSFET器件,其中所述外栅极具有管形形状,并且其中所述管的外侧由氧化物层包围。
8.如权利要求7所述的纳米管MOSFET器件,其中所述外栅极包括栅极电介质和栅极材料,并且其中所述栅极电介质由氧化物或者氮氧化物制成。
9.如权利要求1所述的纳米管MOSFET器件,还包括形成由电介质和栅极材料制成的堆叠的内栅极。
10.如权利要求1所述的纳米管MOSFET器件,其中所述源极由自对准的外延生长硅制成。
11.一种形成纳米管MOSFET器件的方法,包括:
在衬底上形成圆柱形成形的Si层(30);
形成在底部间隔物(41)与顶部间隔物(51)之间定位的包围所述圆柱形Si层(30)的外栅极(50);
在所述顶部间隔物(51)上生长与所述圆柱形成形的Si层(30)的部分相邻的硅外延层;
蚀刻所述圆柱形成形的Si(30)的内部分,从而形成空心圆柱体;
在所述空心圆柱体的底部形成内间隔物(41);
通过填充所述空心圆柱体的部分来形成内栅极(61);
形成与所述内栅极(61)相邻的侧壁间隔物;并且
蚀刻用于接入和接触所述外栅极(50)和漏极(31)的深沟槽。
12.如权利要求11所述的方法,还包括在同心管形配置中形成所述内栅极和外栅极。
13.如权利要求12所述的方法,还包括在所述硅外延层中形成源极。
14.如权利要求11所述的方法,还包括使用硬掩模以限定所述圆柱形成形的Si层。
15.如权利要求11所述的方法,还包括使用反应离子蚀刻(RIE)和选择性蚀刻的序列从而形成外栅极堆叠。
16.如权利要求15所述的方法,其中形成所述外栅极堆叠使用栅极电介质和栅极材料。
17.如权利要求16所述的方法,其中用栅极电介质材料形成所述外栅极堆叠包括使用SiO2或者高K材料,并且所述栅极材料由多晶硅或者金属制成。
18.如权利要求15所述的方法,还包括通过沉积栅极电介质材料来形成所述空心圆柱体。
19.如权利要求11所述的方法,其中在形成与所述内栅极相邻的所述侧壁间隔物之后使内栅极硅化物化。
20.如权利要求13所述的方法,还包括使所述源极和所述硅外延层硅化物化。
21.如权利要求13所述的方法,还包括用电介质材料填充位于所述内栅极、所述源极和所述侧壁间隔物之间的空间。
22.如权利要求11所述的方法,还包括通过接入所述外栅极的深沟槽来形成接触。
23.如权利要求11所述的方法,还包括接入所述衬底,还包括接入所述漏极。
24.如权利要求11所述的方法,还包括形成被内栅极氧化物包围的所述内栅极,所述内栅极氧化物由所述圆柱形成形的Si层包围。
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