CN103380488A - 边缘圆化的场效应晶体管及制造方法 - Google Patents
边缘圆化的场效应晶体管及制造方法 Download PDFInfo
- Publication number
- CN103380488A CN103380488A CN2011800678955A CN201180067895A CN103380488A CN 103380488 A CN103380488 A CN 103380488A CN 2011800678955 A CN2011800678955 A CN 2011800678955A CN 201180067895 A CN201180067895 A CN 201180067895A CN 103380488 A CN103380488 A CN 103380488A
- Authority
- CN
- China
- Prior art keywords
- gate regions
- dielectric regime
- electric charge
- district
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000005669 field effect Effects 0.000 title abstract description 5
- 238000004519 manufacturing process Methods 0.000 title description 7
- 230000015572 biosynthetic process Effects 0.000 claims abstract 3
- 230000015654 memory Effects 0.000 claims description 47
- 150000004767 nitrides Chemical class 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 230000008901 benefit Effects 0.000 claims description 11
- 230000003628 erosive effect Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- -1 silicon-oxygen nitride Chemical class 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims 5
- 239000000956 alloy Substances 0.000 claims 5
- 239000007943 implant Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000001590 oxidative effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明的实施例是直接涉及场效应晶体管的栅极侧壁工程。该技术包含区块介电区的形成及其表面的氮化。在该区块介电区的氮化后，在其上形成栅极区且氧化该栅极区的侧壁以圆化栅极尖角及减少在该栅极角的电场。
Description
背景技术
数据存储器件是多种电子器件(诸如计算机、智能手机、数字内容播放器(如，MP3播放器)、游戏机、控制系统等)中的重要部分。许多电子器件包含非挥发固态存储器器件，诸如快闪存储器(flash memory)。一种常见的快闪存储器器件类型是电荷补获(charge trapping，CT)与非(NAND)集成电路(IC)。图1显示例示性CT-与非系快闪存储器IC。快闪存储器IC100包含制造在单块半导体衬底上的CT-与非存储器单元阵列110、控制电路120、列译码器(column decoder)130、行译码器(rowdecoder)140、输入/输出(I/0)缓冲器150等。根据多种由快闪存储器IC100内部及/或从快闪存储器IC100输出所接收的控制信号180，在存储器单元阵列110中的地址170、175操作控制电路120、列译码器130、行译码器140、I/O缓冲器150等以读及写数据160。快闪存储器IC100的电路是本技术领域中现有的，因此那些快闪存储器IC100中不特别于本发明实施例的态样将不会被进一步讨论。
现在参考图2，显示例示性存储器单元阵列。CT-与非存储器单元阵列110包含多个CT场效应晶体管(FET)210、多个漏极选择栅220、多个源极选择栅230、多个位线(bit line)240、多个字线250、多个漏极选择信号线260及多个源极选择信号线270。阵列110的各个列包含漏极选择栅220、多个CT-FET210及在相对的位线240及接地电位(groundpotential)280之间串联连接源极至漏极的源极选择栅230。各个多个CT-FET210的栅极在阵列110的各个行中耦接至对应字线250。各个漏极选择栅220的栅极连接至对应的漏极选择信号线260。各个源极选择栅230的栅极连接至对应漏极选择信号线270。在一个实例中，CT-FET可为硅-氧化物-氮化物-氧化物-硅(SONOS)FET等。CT-与非存储器单元阵列110是本技术领域中现有的，因此那些CT-与非存储器单元阵列110中不特别于本发明实施例的态样将不会被进一步讨论。
在CT-与非存储器单元阵列110中给定的存储器单元是由注入(inject)电荷至横跨CT-FET210的穿隧介电层的电荷补获层(chargetrapping layer)而编程(program)。给定存储器单元借由移除横跨穿隧介电层的电荷补获层的电荷而擦除(erase)。在一个实例中，使用富尔-诺罕(Fowler-Nordheim，F-N)隧道将CT-FET210编程及擦除。编程及擦除CT-FET存储器单元210的工艺伤害了穿隧介电层，而导致可表现在快闪存储器IC100上的有限次数的编程-擦除循环。因此，CT-FET存储器单元210等仍有需要改善。
发明内容
参考下列用于说明直接涉及场效应晶体管栅极工程的本发明的实施例的说明及附图可良好地知道本发明。
于一个实施例中，一种制造方法包含在衬底上形成穿隧介电区(tunneling dielectric region)。在穿隧介电区上形成电荷补获区。在电荷补获区上形成区块介电区(blocking dielectric region)。氮化区块介电区的表面且之后在被氮化的区块介电区的表面上形成栅极区。之后氧化栅极区，其中，圆化栅极区的边缘且借由被氮化的区块介电区而抑制区块介电区侵蚀进该栅极区。
附图说明
本发明的实施例由范例图示说明，且不因此而受限，随附的附图及相似的符号代表相似的组件，其中：
图1显示根据传统技术的例示性CT-与非系快闪存储器IC的方块图；
图2显示根据传统技术的例示性存储器单元阵列的方块图；
图3显示根据本发明的一个实施例的存储器单元阵列结构的方块图；
图4显示根据本发明的实施例的CT-FET的放大剖面图的方块图；
图5A及图5B显示根据传统技术的CT-FET的方块图；
图6A及图6B显示根据本发明一个实施例的制造存储器单元阵列的方法的流程图；以及
图7A至图7E显示根据本发明一个实施例的制造存储器单元阵列的方块图。
具体实施方式
以下为参照随附图式说明的范例详述合乎本发明的实施例。然而本发明将以下述实施例而说明，将了解本发明不以下列实施例为限。相反地，本发明想要包含于借由随附的权利要求所定义的本发明的取代、修改及等效的范畴。而且，于本发明下列的详述说明中，说明多数具体细节用以了解本发明。然而，应了解本发明无需具体细节也可实行。换句话说，未详述揭露现有的方法、程序、组件及电路以免模糊本发明的态样。
于本申请中，「分离性(disjunctive)」的使用想要包含「结合性(conjunctive)」。「定冠词」或「不定冠词」的使用不想要指基数(cardinality)。具体而言，参考「该」物或「一」物想要标示多个所述可能的物中的一者。
参考图3，其显示根据本发明的一个实施例的存储器单元阵列结构。于一实例中，存储器单元阵列可为CT-与非存储器单元阵列110。然而，所欲为本发明的实施例可应用至任何场效应晶体管器件。于一实例中，各个CT-FET的列可由浅沟槽隔(STI)区305隔开。各个CT-FET可包含漏极区310、源极区315、信道区320、穿隧介电区325(也通常意指底介电区)、电荷补获区330、区块介电区335(也通常意指顶介电区)及栅极区340。源极及漏极区310、315可为衬底345中具有第一类型杂质重掺杂浓度的半导体区。于一实例中，源极及漏极区310、315可为以磷或砷重掺杂的硅。信道区320可为置(dispose)在横向源极及漏极区310、315之间，于衬底345中具有第二类型杂质适当掺杂浓度的半导体区。于一实例中，信道区320可为适当经硼掺杂的硅。穿隧介电区325可为置在信道区320及源极及漏极区310、315邻接部分上方的介电层。于一实例中，穿隧介电区325可为硅氧化物、氧氮化物、硅氧氮化物等层。电荷补获区330可为置在穿隧介电区325及区块介电区335之间的介电层、半导体层等层。于一实例中，电荷补获区330可为氮化物、富硅氮化物(silicon-rich-nitride)等层。区块介电区335可为置在电荷补获区330及栅极区340之间的介电层。于一实例中，区块介电区335可为硅氧化物、氧氮化物、硅氧氮化物等层。栅极区340可为半导体或置在相对于电荷补获区330的区块介电区335上的导电层。于一实例中，栅极区340可为具有第一类型杂质重掺杂浓度的多晶硅层。
区块介电区335的表面在栅极区340形成前被氮化。区块介电区335的表面的氮化物抑制在区块介电区335接口氧化侵蚀入栅极区340。因此，当栅极边缘在下列氧化步骤圆化时，区块介电335的厚度在栅极区340在中心及边缘为实质相同。
现在参考图4，显示根据本发明的实施例的CT-FET的放大剖面图。区块介电区335的氮化物410减少氧化侵蚀至栅极区340。减少的侵蚀导致在边缘的区块介电厚度420是实质与在栅极区340中心的有效介电厚度425相同，其增加了编程-擦除容受力(endurance)。相比之下，图5A显示根据传统技术的栅极区340不具有明显圆化的边缘510的CT-FET。当CT-FET的栅极区340不具有任何明显圆化的边缘510，擦除时在栅极区340边缘的电场实质较高。因为来自栅极边缘的电子注入，在边缘实质上较高的电场减少了CT-FET编程-擦除容受力。在图5B中，说明借由根据传统技术氧化而制造具有栅极区圆化边缘520的CT-FET。栅极侧壁氧化至圆栅极角520制造使得成在栅极边缘的区块介电530比在栅极中心的区块介电540的厚的侵蚀。起因于氧化的区块介电区335侵蚀至栅极区340，减少了有效的电场横跨区块介电区335。因为区块介电区335侵蚀至栅极区340减少了快闪存储器IC的编程-擦除速度，区块介电335的有效厚度增加。因此，使用区块介电氮化物抑制在栅极区边缘的氧化侵蚀的栅极侧壁工程相较于传统技术改善了快闪存储器IC中CT-FET的性能。也可以使用区块介电氮化物抑制在栅极区边缘的氧化侵蚀的栅极侧壁工程可施用以改善其它集成电路(包含FET)的性能。
现在参考图6A-6B，显示根据本发明的一个实施例的制造存储器单元阵列的方法。制造存储器单元阵列的方法将进一步参考图7A-7E来说明，其说明根据本发明的一个实施例的存储器单元阵列的制造。如图6A及图7A所描绘，在605的工艺于半导体晶圆衬底702上以多种初始工艺，诸如清洁、沉积、掺杂、蚀刻及/或其它等开始。衬底702可为以第一掺杂类型于第一浓度掺杂的半导体。于一实例中，衬底702可为适当掺杂硼(P)的硅。
在610，穿隧介电区706形成在衬底702上。于一实例中，穿隧介电区706可借由在存储器单元阵列区中的衬底702的经氧化曝露的表面以任何现有热干式氧化工艺而形成。于其它实例中，穿隧介电区706可借由由任何现有化学气相沉积工艺沉积硅氧氮化物薄膜而形成。于一实例中，可形成厚度约3至8纳米的穿隧介电区706。
现在参考图7B，在615，电荷补获区708形成在穿隧介电区706上。在620，区块介电区710形成在电荷补获区708上。于一实例中，电荷补获区及区块介电区可由任何现有工艺如化学气相沉积(CVD)或原子层沉积(ALD)，在穿隧介电区706上由第一沉积氮化物层708而形成。氮化物层可包含具有硅对氮的原子比约为3：4或更大的富硅氮化物。电荷补获区可借由沉积多层，例如在富硅氮化物层上的氮化物层而形成。此外，一或多层可具有实质上固定及/或分级的浓度轮廓。之后可由任何现有工艺将牺牲氧化物形成在硅氮化物层上。之后在部分的剩余氮化物层氧化形成氧氮化物或硅氧氮化物层710前可回蚀刻(etch back)牺牲氧化物及部分的氮化物层。于一实例中，所得电荷补获区708可形成约4至15纳米的厚度及所得区块介电区710可形成约3至8纳米的厚度。
在625，经曝露的区块介电区710的表面是被氮化的氮化物712。于一实例中，氧氮化物或硅氧氮化物层710经曝露的表面是在炉退火(furnace anneal)中等工艺曝露于氮。
现在参考图7C，在630，栅极区714形成在区块介电区710上。于一实例中，多晶硅层714借由任何现有工艺诸如化学气相沉积在氮化氧氮化物层712、710上而沉积。将光刻胶(photo resist)沉积在多晶硅层714上及由任何现有光刻工艺图案化以形成栅极/电荷补获掩模716。现在参考图7D，多晶硅层714、被氮化氧氮化物层712、710及透过栅极/电荷补获掩模716曝照的氮化物层708之后由任何现有各向异性蚀刻工艺选择性蚀刻。栅极/电荷补获掩模716之后可由任何现有工艺诸如刻胶剥除或刻胶灰化所移除。
现在参考图6B及图7E，在635，将栅极区714及视需要的电荷补获区708氧化，其中，在借由氮化区块介电区712、710而抑制侵蚀时，完成栅极区714中的栅极角圆化边缘718。于一实例中，栅极区714的侧壁及视需要的电荷补获区708，被氧化以形成栅极区712，以及视需要具有被抑制侵蚀的经抑制的圆化边缘718及侧壁介电层720的电荷补获区708。
在640，该工艺接着多种接续工艺，诸如植入、掺杂、蚀刻、清洁及/或其它等，以形成一或多个额外区，诸如源极、漏极及信道区、栅极、源极及漏极接触、周围电路、互连、通孔、钝化层及/或其它等。源极/漏极区704可为部分以第二掺杂类型经第二浓度掺杂的衬底702。于一实例中，源极/漏极区704可为经磷或砷(N+)重掺杂的硅。较佳为上述制造存储器单元阵列的方法也可包含其它额外工艺且可从上述顺序改变工艺顺序。
本发明的实施例于圆化栅极区的尖边缘及角时借由区块介电区至栅极区而有利地抑制侵蚀。借由区块介电区的氮化有利地抑制侵蚀。因为于氧化圆化栅极边缘及角的期间边缘侵蚀(edge encroachment)被抑制，使得栅极区及信道区之间在栅极区的中心及边缘的电子氧化物厚度(EOT)是实质相同的。更进一步，编程-擦除速度及容受度借由栅极区抑制的边缘侵蚀及/或在栅极区及信道区之间在栅极区的中心及边缘实质上相同的EOT而明显地增加。
本发明的特定实施例的前述描述是提供图解及说明的目的。其并非想要限制本发明为所揭露的特定形式，且明显地，经由上述教示而作出许多修改及改变是可能的。选用的实施例及说明想要最佳说明本发明的原理及其特殊应用，借以使本技术领域中的人士可最佳化使用本发明及多种经多种修改的实施例以企图适合于特殊用途。本发明的范畴是由随附的权利要求及其等效所定义。
Claims (20)
1.一种方法，其特征在于，包括：
在衬底上形成穿隧介电区；
在该穿隧介电区上形成电荷补获区；
在该电荷补获区上形成区块介电区；
氮化该区块介电区的表面；
在该被氮化区块介电区上形成栅极区；以及
氧化该栅极区，其中，借由该被氮化区块介电区而抑制该栅极区的边缘侵蚀。
2.根据权利要求1所述的方法，进一步包括：沿着该栅极区氧化该电荷补获区。
3.根据权利要求1所述的方法，其特征在于，形成该电荷补获区包括沉积富硅氮化物层。
4.根据权利要求3所述的方法，其特征在于，形成该电荷补获区包括从该富硅氮化物层的部分形成硅氧氮化物层。
5.一种方法，其特征在于，包括：
在电荷补获区上形成区块介电区；
氮化该区块介电区的表面；
在该被氮化区块介电区上形成栅极区；以及
氧化该栅极区及电荷补获区的侧壁。
6.根据权利要求5所述的方法，其特征在于，形成该电荷补获区包括沉积富硅氮化物层。
7.根据权利要求6所述的方法，其特征在于，形成该区块介电区包括从该富硅氮化物层的部分形成硅氧氮化物层。
8.根据权利要求7所述的方法，其特征在于，氮化该区块介电区的表面包括在炉退火中将该区块介电区的表面曝露于氮。
9.根据权利要求5所述的方法，其特征在于，借由该区块介电区的氮化而抑制该栅极区的边缘侵蚀。
10.根据权利要求5所述的方法，其特征在于，借由氧化物植入该栅极区的该侧壁而抑制该栅极区的边缘侵蚀。
11.一种集成电路存储器单元，其特征在于，包括：
漏极区；
源极区；
信道区，其置在该源极及漏极区之间；
穿隧介电区，其置在该信道区及电荷补获区之间；
区块介电区，其置在该电荷补获区及栅极区之间，其中，该区块介电区邻接该栅极区的表面被氮化；
氧化物，其置在该电荷补获区及该栅极区的侧壁上，其中，借由该被氮化的区块介电区的表面而抑制从该氧化物边缘侵蚀进该栅极区。
12.根据权利要求11所述的集成电路存储器单元，其特征在于：
该漏极区包括经第一类型掺杂物重掺杂的硅；
该源极区包括经该第一类型掺杂物重掺杂的硅；以及
该信道区包括经第二类型掺杂物适当掺杂的硅。
13.根据权利要求12所述的集成电路存储器单元，其特征在于：
该第一类型掺杂物包括磷或砷；以及
该第二类型掺杂物包括硼。
14.根据权利要求11所述的集成电路存储器单元，其特征在于，该穿隧介电区包括硅氧化物。
15.根据权利要求14所述的集成电路存储器单元，其特征在于，该电荷补获区包括富硅氮化物。
16.根据权利要求15所述的集成电路存储器单元，其特征在于，该区块介电区包括硅氧氮化物。
17.根据权利要求16所述的集成电路存储器单元，其特征在于，该栅极区包括多晶硅。
18.根据权利要求11所述的集成电路存储器单元，其特征在于，该栅极区及该信道区之间的等效介电厚度在该栅极区的中心及边缘是实质相同的。
19.根据权利要求18所述的集成电路存储器单元，其特征在于，该集成电路存储器单元的编程-擦除速度借由该栅极区抑制的边缘侵蚀及在该栅极区及该信道区之间在该栅极区的中心及边缘实质上相同的该等效介电厚度而增加。
20.根据权利要求18所述的集成电路存储器单元，其特征在于，该集成电路存储器单元的容受力借由该栅极区抑制的边缘侵蚀及在该栅极区及该信道区之间在该栅极区的中心及边缘实质上相同的该等效介电厚度而增加。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710028767.9A CN106847686B (zh) | 2010-12-20 | 2011-12-19 | 边缘圆化的场效应晶体管及制造方法 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/973,756 | 2010-12-20 | ||
| US12/973,756 US9412598B2 (en) | 2010-12-20 | 2010-12-20 | Edge rounded field effect transistors and methods of manufacturing |
| PCT/US2011/065930 WO2012087978A2 (en) | 2010-12-20 | 2011-12-19 | Edge rounded field effect transistors and methods of manufacturing |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710028767.9A Division CN106847686B (zh) | 2010-12-20 | 2011-12-19 | 边缘圆化的场效应晶体管及制造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103380488A true CN103380488A (zh) | 2013-10-30 |
| CN103380488B CN103380488B (zh) | 2017-02-08 |
Family
ID=46233256
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201180067895.5A Active CN103380488B (zh) | 2010-12-20 | 2011-12-19 | 边缘圆化的场效应晶体管及制造方法 |
| CN201710028767.9A Active CN106847686B (zh) | 2010-12-20 | 2011-12-19 | 边缘圆化的场效应晶体管及制造方法 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710028767.9A Active CN106847686B (zh) | 2010-12-20 | 2011-12-19 | 边缘圆化的场效应晶体管及制造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US9412598B2 (zh) |
| EP (1) | EP2656381A4 (zh) |
| JP (2) | JP5774720B2 (zh) |
| KR (1) | KR101983682B1 (zh) |
| CN (2) | CN103380488B (zh) |
| WO (1) | WO2012087978A2 (zh) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9614105B2 (en) | 2013-04-22 | 2017-04-04 | Cypress Semiconductor Corporation | Charge-trap NOR with silicon-rich nitride as a charge trap layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6187633B1 (en) * | 1998-10-09 | 2001-02-13 | Chartered Semiconductor Manufacturing, Ltd. | Method of manufacturing a gate structure for a semiconductor memory device with improved breakdown voltage and leakage rate |
| US20080142874A1 (en) * | 2006-12-16 | 2008-06-19 | Spansion Llc | Integrated circuit system with implant oxide |
| US20090253244A1 (en) * | 2002-07-05 | 2009-10-08 | Chang-Hyun Lee | Nonvolatile Memory Devices Having Gate Structures Doped by Nitrogen and Methods of Fabricating the Same |
Family Cites Families (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847427A (en) * | 1995-12-21 | 1998-12-08 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device utilizing an oxidation suppressing substance to prevent the formation of bird's breaks |
| JPH09232454A (ja) * | 1995-12-21 | 1997-09-05 | Toshiba Corp | 不揮発性半導体装置及びその製造方法 |
| JP2001015619A (ja) * | 1999-06-30 | 2001-01-19 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法 |
| TW546840B (en) * | 2001-07-27 | 2003-08-11 | Hitachi Ltd | Non-volatile semiconductor memory device |
| US6974995B1 (en) | 2001-12-27 | 2005-12-13 | Advanced Micro Devices, Inc. | Method and system for forming dual gate structures in a nonvolatile memory using a protective layer |
| US6808992B1 (en) | 2002-05-15 | 2004-10-26 | Spansion Llc | Method and system for tailoring core and periphery cells in a nonvolatile memory |
| DE10240408A1 (de) * | 2002-09-02 | 2004-03-25 | Advanced Micro Devices, Inc., Sunnyvale | Transistorelement mit einem Anisotropen Gate-Dielektrikum MI großem ε |
| US6943401B1 (en) | 2003-09-11 | 2005-09-13 | Advanced Micro Devices, Inc. | Flash memory cell with drain and source formed by diffusion of a dopant from a silicide |
| US7301193B2 (en) | 2004-01-22 | 2007-11-27 | Spansion Llc | Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell |
| TWI244166B (en) | 2004-03-11 | 2005-11-21 | Ememory Technology Inc | A non-volatile memory cell and fabricating method thereof |
| US6927129B1 (en) | 2004-04-08 | 2005-08-09 | Advanced Micro Devices | Narrow wide spacer |
| US7029975B1 (en) | 2004-05-04 | 2006-04-18 | Advanced Mirco Devices, Inc. | Method and apparatus for eliminating word line bending by source side implantation |
| US6987696B1 (en) | 2004-07-06 | 2006-01-17 | Advanced Micro Devices, Inc. | Method of improving erase voltage distribution for a flash memory array having dummy wordlines |
| US7170130B2 (en) | 2004-08-11 | 2007-01-30 | Spansion Llc | Memory cell with reduced DIBL and Vss resistance |
| US7151028B1 (en) | 2004-11-04 | 2006-12-19 | Spansion Llc | Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability |
| US7488657B2 (en) | 2005-06-17 | 2009-02-10 | Spansion Llc | Method and system for forming straight word lines in a flash memory array |
| US20070037371A1 (en) | 2005-08-10 | 2007-02-15 | Zhigang Wang | Method of forming gate electrode structures |
| US7317222B2 (en) | 2006-01-27 | 2008-01-08 | Freescale Semiconductor, Inc. | Memory cell using a dielectric having non-uniform thickness |
| JP5032145B2 (ja) * | 2006-04-14 | 2012-09-26 | 株式会社東芝 | 半導体装置 |
| US8809936B2 (en) | 2006-07-31 | 2014-08-19 | Globalfoundries Inc. | Memory cell system with multiple nitride layers |
| US7675104B2 (en) | 2006-07-31 | 2010-03-09 | Spansion Llc | Integrated circuit memory system employing silicon rich layers |
| KR100852236B1 (ko) * | 2006-09-05 | 2008-08-13 | 삼성전자주식회사 | 이이피롬 장치 및 그 제조 방법 |
| CN100561690C (zh) * | 2006-09-30 | 2009-11-18 | 中芯国际集成电路制造(上海)有限公司 | 非挥发性半导体存储器及其制作方法 |
| US8143661B2 (en) | 2006-10-10 | 2012-03-27 | Spansion Llc | Memory cell system with charge trap |
| US20080153224A1 (en) | 2006-12-21 | 2008-06-26 | Spansion Llc | Integrated circuit system with memory system |
| US20080149990A1 (en) | 2006-12-21 | 2008-06-26 | Spansion Llc | Memory system with poly metal gate |
| US20080150011A1 (en) | 2006-12-21 | 2008-06-26 | Spansion Llc | Integrated circuit system with memory system |
| US20080150000A1 (en) | 2006-12-21 | 2008-06-26 | Spansion Llc | Memory system with select gate erase |
| US7803680B2 (en) | 2007-01-12 | 2010-09-28 | Spansion Llc | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications |
| KR20080072461A (ko) * | 2007-02-02 | 2008-08-06 | 삼성전자주식회사 | 전하 트랩형 메모리 소자 |
| US7732276B2 (en) | 2007-04-26 | 2010-06-08 | Spansion Llc | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications |
| US8367537B2 (en) | 2007-05-10 | 2013-02-05 | Spansion Llc | Flash memory cell with a flair gate |
| CN101364615B (zh) * | 2007-08-08 | 2011-05-25 | 旺宏电子股份有限公司 | 非易失性存储器与非易失性存储器的形成方法 |
| US7670905B2 (en) * | 2007-09-07 | 2010-03-02 | Micron Technology, Inc. | Semiconductor processing methods, and methods of forming flash memory structures |
| US7829936B2 (en) | 2007-10-17 | 2010-11-09 | Spansion Llc | Split charge storage node inner spacer process |
| JP5348898B2 (ja) * | 2008-01-22 | 2013-11-20 | 株式会社東芝 | 半導体装置およびその製造方法 |
| JP2009252774A (ja) * | 2008-04-01 | 2009-10-29 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
| US20090261406A1 (en) | 2008-04-17 | 2009-10-22 | Suh Youseok | Use of silicon-rich nitride in a flash memory device |
| US8987092B2 (en) | 2008-04-28 | 2015-03-24 | Spansion Llc | Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges |
| US7867899B2 (en) | 2008-04-29 | 2011-01-11 | Spansion, Llc | Wordline resistance reduction method and structure in an integrated circuit memory device |
| US8669597B2 (en) | 2008-05-06 | 2014-03-11 | Spansion Llc | Memory device interconnects and method of manufacturing |
| US7951704B2 (en) | 2008-05-06 | 2011-05-31 | Spansion Llc | Memory device peripheral interconnects and method of manufacturing |
| US7998846B2 (en) | 2008-09-12 | 2011-08-16 | Spansion Llc | 3-D integrated circuit system and method |
| US20100078814A1 (en) | 2008-09-29 | 2010-04-01 | Roy Alok Nandini | System and method for using porous low dielectric films |
| US7907448B2 (en) | 2008-10-07 | 2011-03-15 | Spansion Llc | Scaled down select gates of NAND flash memory cell strings and method of forming same |
| US8076199B2 (en) | 2009-02-13 | 2011-12-13 | Spansion Llc | Method and device employing polysilicon scaling |
| US8487373B2 (en) | 2009-04-29 | 2013-07-16 | Spanion Llc | SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same |
| US8551858B2 (en) | 2010-02-03 | 2013-10-08 | Spansion Llc | Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory |
-
2010
- 2010-12-20 US US12/973,756 patent/US9412598B2/en active Active
-
2011
- 2011-12-19 CN CN201180067895.5A patent/CN103380488B/zh active Active
- 2011-12-19 WO PCT/US2011/065930 patent/WO2012087978A2/en active Application Filing
- 2011-12-19 EP EP11850857.1A patent/EP2656381A4/en not_active Withdrawn
- 2011-12-19 CN CN201710028767.9A patent/CN106847686B/zh active Active
- 2011-12-19 KR KR1020137019143A patent/KR101983682B1/ko active IP Right Grant
- 2011-12-19 JP JP2013544874A patent/JP5774720B2/ja active Active
-
2015
- 2015-07-01 JP JP2015132867A patent/JP6039757B2/ja active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6187633B1 (en) * | 1998-10-09 | 2001-02-13 | Chartered Semiconductor Manufacturing, Ltd. | Method of manufacturing a gate structure for a semiconductor memory device with improved breakdown voltage and leakage rate |
| US20090253244A1 (en) * | 2002-07-05 | 2009-10-08 | Chang-Hyun Lee | Nonvolatile Memory Devices Having Gate Structures Doped by Nitrogen and Methods of Fabricating the Same |
| US20080142874A1 (en) * | 2006-12-16 | 2008-06-19 | Spansion Llc | Integrated circuit system with implant oxide |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5774720B2 (ja) | 2015-09-09 |
| CN106847686A (zh) | 2017-06-13 |
| JP2015173298A (ja) | 2015-10-01 |
| KR101983682B1 (ko) | 2019-05-29 |
| EP2656381A2 (en) | 2013-10-30 |
| JP6039757B2 (ja) | 2016-12-07 |
| WO2012087978A2 (en) | 2012-06-28 |
| US9412598B2 (en) | 2016-08-09 |
| US20120153377A1 (en) | 2012-06-21 |
| EP2656381A4 (en) | 2017-11-01 |
| JP2013546206A (ja) | 2013-12-26 |
| CN106847686B (zh) | 2020-04-24 |
| WO2012087978A3 (en) | 2012-09-27 |
| CN103380488B (zh) | 2017-02-08 |
| KR20140003492A (ko) | 2014-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4659527B2 (ja) | 半導体装置の製造方法 | |
| JP5116987B2 (ja) | 集積半導体不揮発性記憶装置 | |
| US9231115B2 (en) | Semiconductor device and manufacturing method thereof | |
| TW525170B (en) | Nonvolatile semiconductor memory device and its fabricating method | |
| US20090050956A1 (en) | Semiconductor memory device and method of manufacturing the same | |
| TWI413261B (zh) | 半導體裝置 | |
| JP2008251826A (ja) | 半導体装置の製造方法 | |
| CN107452747B (zh) | 制造半导体器件的方法 | |
| JP2010282987A (ja) | 半導体装置およびその製造方法 | |
| JP2010245160A (ja) | 半導体装置の製造方法 | |
| JP2006019373A (ja) | 不揮発性半導体記憶装置の製造方法および不揮発性半導体記憶装置 | |
| CN105448843A (zh) | 制造半导体器件的方法 | |
| US6720219B2 (en) | Split gate flash memory and formation method thereof | |
| JP2018110141A (ja) | 半導体装置およびその製造方法 | |
| JP4810330B2 (ja) | 半導体記憶装置 | |
| US20230067382A1 (en) | Integrated chip with a gate structure disposed within a trench | |
| US20060183284A1 (en) | Non-volatile semiconductor storage device and the manufacturing method thereof | |
| CN103380488A (zh) | 边缘圆化的场效应晶体管及制造方法 | |
| JP2005064178A (ja) | 半導体装置およびその製造方法 | |
| JP2005116582A (ja) | 半導体装置およびその製造方法 | |
| US6207502B1 (en) | Method of using source/drain nitride for periphery field oxide and bit-line oxide | |
| JP2006041227A (ja) | 半導体装置およびその製造方法 | |
| JP5236910B2 (ja) | 不揮発性半導体記憶装置 | |
| JP2011096727A (ja) | 半導体装置の製造方法 | |
| JP2010212506A (ja) | 半導体記憶装置及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20160323 Address after: American California Applicant after: Cypress Semiconductor Corp. Address before: American California Applicant before: Spansion LLC N. D. Ges D. Staates |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |