CN103222050B - 用于ic器件的止裂通孔 - Google Patents

用于ic器件的止裂通孔 Download PDF

Info

Publication number
CN103222050B
CN103222050B CN201180056162.1A CN201180056162A CN103222050B CN 103222050 B CN103222050 B CN 103222050B CN 201180056162 A CN201180056162 A CN 201180056162A CN 103222050 B CN103222050 B CN 103222050B
Authority
CN
China
Prior art keywords
hole
dielectric
rdl
pad
crack arrest
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201180056162.1A
Other languages
English (en)
Chinese (zh)
Other versions
CN103222050A (zh
Inventor
R·F·麦卡锡
S·C·贝汀菲儿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN103222050A publication Critical patent/CN103222050A/zh
Application granted granted Critical
Publication of CN103222050B publication Critical patent/CN103222050B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/228—Multiple bumps having different structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/927—Multiple bond pads having different structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/936—Multiple bond pads having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201180056162.1A 2010-11-01 2011-11-01 用于ic器件的止裂通孔 Active CN103222050B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/917,144 2010-11-01
US12/917,144 US8304867B2 (en) 2010-11-01 2010-11-01 Crack arrest vias for IC devices
PCT/US2011/058779 WO2012061381A2 (en) 2010-11-01 2011-11-01 Crack arrest vias for ic devices

Publications (2)

Publication Number Publication Date
CN103222050A CN103222050A (zh) 2013-07-24
CN103222050B true CN103222050B (zh) 2016-03-02

Family

ID=45995781

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180056162.1A Active CN103222050B (zh) 2010-11-01 2011-11-01 用于ic器件的止裂通孔

Country Status (4)

Country Link
US (1) US8304867B2 (https=)
JP (1) JP6008431B2 (https=)
CN (1) CN103222050B (https=)
WO (1) WO2012061381A2 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569886B2 (en) 2011-11-22 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of under bump metallization in packaging semiconductor devices
US9412689B2 (en) * 2012-01-24 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging structure and method
US10141202B2 (en) 2013-05-20 2018-11-27 Qualcomm Incorporated Semiconductor device comprising mold for top side and sidewall protection
US9048149B2 (en) * 2013-07-12 2015-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Self-alignment structure for wafer level chip scale package
JP6253439B2 (ja) * 2014-02-17 2017-12-27 ルネサスエレクトロニクス株式会社 半導体装置
KR102109569B1 (ko) 2015-12-08 2020-05-12 삼성전자주식회사 전자부품 패키지 및 이를 포함하는 전자기기
CN106898589B (zh) 2015-12-18 2020-03-17 联华电子股份有限公司 集成电路
JP6672820B2 (ja) * 2016-01-18 2020-03-25 株式会社村田製作所 電子部品
CN105575935A (zh) * 2016-02-25 2016-05-11 中国电子科技集团公司第十三研究所 Cmos驱动器晶圆级封装及其制作方法
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
KR102028715B1 (ko) * 2017-12-19 2019-10-07 삼성전자주식회사 반도체 패키지
US12125811B2 (en) * 2018-06-15 2024-10-22 Texas Instruments Incorporated Semiconductor structure and method for wafer scale chip package
KR102073295B1 (ko) 2018-06-22 2020-02-04 삼성전자주식회사 반도체 패키지
US11063146B2 (en) 2019-01-10 2021-07-13 Texas Instruments Incorporated Back-to-back power field-effect transistors with associated current sensors
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US10825789B1 (en) 2019-08-26 2020-11-03 Nxp B.V. Underbump metallization dimension variation with improved reliability
CN114651322A (zh) * 2019-11-12 2022-06-21 华为技术有限公司 芯片堆叠封装结构、电子设备
US20210210462A1 (en) * 2020-01-06 2021-07-08 Texas Instruments Incorporated Chip scale package with redistribution layer interrupts
KR102815754B1 (ko) * 2020-10-27 2025-06-05 삼성전자주식회사 반도체 패키지
US11308257B1 (en) * 2020-12-15 2022-04-19 International Business Machines Corporation Stacked via rivets in chip hotspots
US11862576B2 (en) * 2021-10-28 2024-01-02 Texas Instruments Incorporated IC having electrically isolated warpage prevention structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020185721A1 (en) * 1999-09-30 2002-12-12 Chan Seung Hwang Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same
CN101241889A (zh) * 2007-01-12 2008-08-13 硅存储技术公司 封装的凸点下金属层结构及其制造方法
US20090283903A1 (en) * 2005-12-02 2009-11-19 Nepes Corporation Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same
CN101587873A (zh) * 2008-05-21 2009-11-25 福葆电子股份有限公司 降低应力的介电层结构及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462414B1 (en) * 1999-03-05 2002-10-08 Altera Corporation Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad
JP3989152B2 (ja) * 2000-02-08 2007-10-10 株式会社リコー 半導体装置パッケージ
JP2003243569A (ja) * 2002-02-18 2003-08-29 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP3863161B2 (ja) * 2004-01-20 2006-12-27 松下電器産業株式会社 半導体装置
TWI268564B (en) * 2005-04-11 2006-12-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
KR100790527B1 (ko) 2006-07-27 2008-01-02 주식회사 네패스 웨이퍼레벨 패키지 및 그 제조 방법
JP2009010260A (ja) * 2007-06-29 2009-01-15 Fujikura Ltd 半導体装置
US20090278263A1 (en) 2008-05-09 2009-11-12 Texas Instruments Incorporated Reliability wcsp layouts
US8076786B2 (en) * 2008-07-11 2011-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for packaging a semiconductor package
JP2010092930A (ja) * 2008-10-03 2010-04-22 Fujikura Ltd 半導体装置およびその製造方法
KR20100093357A (ko) 2009-02-16 2010-08-25 삼성전자주식회사 웨이퍼 레벨 칩스케일 패키지
US8084871B2 (en) * 2009-11-10 2011-12-27 Maxim Integrated Products, Inc. Redistribution layer enhancement to improve reliability of wafer level packaging

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020185721A1 (en) * 1999-09-30 2002-12-12 Chan Seung Hwang Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same
US20090283903A1 (en) * 2005-12-02 2009-11-19 Nepes Corporation Bump with multiple vias for semiconductor package and fabrication method thereof, and semiconductor package utilizing the same
CN101241889A (zh) * 2007-01-12 2008-08-13 硅存储技术公司 封装的凸点下金属层结构及其制造方法
CN101587873A (zh) * 2008-05-21 2009-11-25 福葆电子股份有限公司 降低应力的介电层结构及其制造方法

Also Published As

Publication number Publication date
JP2013543272A (ja) 2013-11-28
WO2012061381A2 (en) 2012-05-10
US20120104604A1 (en) 2012-05-03
JP6008431B2 (ja) 2016-10-19
CN103222050A (zh) 2013-07-24
US8304867B2 (en) 2012-11-06
WO2012061381A3 (en) 2012-07-12
WO2012061381A8 (en) 2014-12-04

Similar Documents

Publication Publication Date Title
CN103222050B (zh) 用于ic器件的止裂通孔
US11195804B2 (en) Semiconductor structure
US9478443B2 (en) Semiconductor package and method of forming the same
US10371717B2 (en) 3D chip testing through micro-C4 interface
TWI710085B (zh) 半導體結構及其製造方法
KR101611684B1 (ko) 반도체 디바이스를 위한 패키징 방법, 패키징된 반도체 디바이스, 및 이의 설계 방법
US8575493B1 (en) Integrated circuit device having extended under ball metallization
CN103378037B (zh) 用于焊料连接的方法和装置
US12021051B2 (en) Semiconductor package and method of forming the same
TW201503303A (zh) 半導體裝置
CN108063094A (zh) 基于基板的扇出型晶圆级封装
CN103748679A (zh) 具有取决于在裸片上的位置的定向或几何形状或在支柱与裸片垫片之间形成有图案化结构以用于减少热应力的顺应互连支柱
KR20220033655A (ko) 반도체 패키지
US10267847B2 (en) Probe head structure of probe card and testing method
JP2014179364A (ja) 半導体チップ及びこれを備える半導体装置
JP5414219B2 (ja) ウエハレベルｃｓｐにおける絶縁性テスト方法及びこれに用いるｔｅｇパターン
CN206628463U (zh) 一种芯片及移动终端
CN203774294U (zh) 一种封装结构
TW201543635A (zh) 封裝結構、晶片結構及其製法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant