CN103208433A - 半导体器件制造系统以及半导体器件制造方法 - Google Patents
半导体器件制造系统以及半导体器件制造方法 Download PDFInfo
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Abstract
本发明提供一种半导体器件制造系统,其不需要过剩的防腐蚀措施能够防止半导体器件制造中生产率的降低,从叠层芯片(13)制造半导体器件的半导体器件制造系统(10)具备:芯片还原装置(14)和芯片接合装置(15),芯片还原装置(14)具有还原室(24),在该还原室(24)内还原各芯片(11)的端子(27)表面的氧化膜,芯片接合装置(15)具有与还原室(24)分开的回流焊室(25),在该回流焊室(25)内进行焊接凸块(26)与各芯片(11)的端子(27)的接合,芯片接合装置(15)与芯片还原装置(14)分别设置。
Description
技术领域
本发明涉及制造在端子接合焊接凸块(solder bump)的半导体器件的半导体器件制造系统和半导体器件制造方法。
背景技术
在制造半导体器件时,在由半导体晶片形成的IC基板(芯片)中,进行将焊接凸块接合至由金属形成的端子的工序。端子在通过蒸镀等形成以后,接触大气中的氧气等,在表面上形成氧化膜,该氧化膜阻碍端子和焊接凸块的接合。
因而,现有技术中在将焊接凸块接合至端子之前,进行用焊剂去除端子表面的氧化膜的工序。具体地讲,焊剂将端子表面活性化,去除(还原)氧化膜,并且覆盖该表面,防止新的氧化,维持端子表面的活性化状态。然而,焊剂有时作为残渣残留在端子的表面以及焊接凸块之间。
另外,在熔融焊接凸块并接合到端子时,从被加热的焊剂产生的气体有时作为气孔残留在焊接凸块中。
与此对应,利用在减压气氛中向芯片供给羧酸例如甲酸的蒸汽,并且将芯片加热的方法(例如,参照专利文献1)。在该方法中,甲酸不发生残渣地还原芯片的端子表面的氧化膜,另外,甲酸即使被加热也不发生气体,而且由于减少气氛气体的压力,因此即使产生气体也从焊接凸块排出。被加热了的焊接凸块熔融后接合于端子。
近年来,为了减少半导体器件的占地面积,开发了叠层多个芯片制造半导体器件的三维安装方法。在该三维安装方法中,在各芯片中,形成由在厚度方向贯通该芯片的导体形成的配线,例如,TSV(ThroughSilicon Via:硅通孔技术),在1个芯片的配线端部形成的电极垫盘(端子)与形成在另一个芯片的配线端部的焊接凸块接合,三维地形成电路。在上述三维安装方法的1个芯片中的电极垫盘与其它芯片中的焊接凸块的接合中也适用在专利文献1中记载的方法。
现有技术文献
专利文献1:日本特许3378852号
发明内容
发明想要解决的问题
然而,在专利文献1中记载的方法中,由于在相同处理室内进行由甲酸实施的还原端子表面的氧化膜和通过加热实施的焊接凸块的熔融接合,因此在进行端子表面还原的期间,不能进行焊接凸块的熔融接合,存在半导体器件的制造的生产率低下这样的问题。
本发明的目的是提供能够防止半导体器件制造的生产率低下的半导体器件制造系统和半导体器件制造方法。
用于解决课题的方法
为了达到上述目的,本发明第一方面记载的半导体器件制造系统,其制造在端子接合有焊接凸块的半导体器件,该半导体器件制造系统的特征在于,包括:还原装置,其具有第一处理室,在该第一处理室内将上述端子的表面的氧化膜还原;和接合装置,其与上述还原装置分别设置,并且具有与上述第一处理室隔离的第二处理室,在该第二处理室中进行将上述焊接凸块与上述端子的接合。
本发明第二方面记载的半导体器件制造系统在本发明第一方面记载的半导体器件制造系统中,特征是,上述还原装置和上述接合装置相互连接。
本发明第三方面记载的半导体器件制造系统在本发明第一或第二方面记载的半导体器件制造系统中,特征是,上述还原装置具有向上述第一处理室内供给氮的第一氮供给装置,上述接合装置具有向上述第二处理室内供给氮的第二氮供给装置。
本发明第四方面记载的半导体器件制造系统在本发明第一或第二方面记载的半导体器件制造系统中,特征是,上述还原装置具有:对上述第一处理室内进行减压的减压装置;配置在上述第一处理室内,载置上述半导体器件的载置台;和以与该载置台相对的方式向上述第一处理室内突出的按压装置,该按压装置具有:筒状部,其内部向大气开放,并将上述内部与上述第一处理室内分隔,并且朝向上述载置台自由地伸缩;和抵接部,其设置于该筒状部的上述载置台侧的前端,当上述筒状部伸长时,与载置于上述载置台的半导体器件抵接。
本发明第五方面记载的半导体器件制造系统在方案本发明第一或第二方面记载的半导体器件制造系统中,特征是,上述还原装置具备向上述第一处理室内供给羧酸的羧酸供给装置。
本发明第六方面记载的半导体器件制造系统在本发明第五方面记载的半导体器件制造系统中,特征是,上述羧酸是甲酸(蚁酸)。
为了达到上述目的,本发明第七方面记载的半导体器件制造方法其为在半导体器件制造系统中执行的半导体器件制造方法,其特征在于:上述半导体器件制造系统制造在端子接合有焊接凸块的半导体器件,上述半导体器件制造系统具备:具有第一处理室,在该第一处理室内将上述端子的表面的氧化膜还原的还原装置;和与该还原装置分别设置并具有与上述第一处理室隔离的第二处理室,在该第二处理室内进行将上述焊接凸块与上述端子接合的接合装置,在上述还原装置中对一个半导体器件的上述端子的表面的氧化膜进行还原期间,在上述接合装置中将另一个半导体器件的上述端子和上述焊接凸块进行接合。
本发明第八方面记载的半导体器件制造方法在本发明第七方面的记载的半导体器件制造方法中,特征是,在将上述半导体器件从上述还原装置向上述接合装置移送时,将上述第一处理室内和上述第二处理室内用氮充填。
本发明第九方面记载的半导体器件制造方法在本发明第七或第八方面记载的半导体器件制造方法中,特征是,在上述还原装置中,在对搬入有上述半导体器件的上述第一处理室内进行减压后,向该第一处理室内供给羧酸。
本发明第十方面记载的半导体器件制造方法在本发明第九方面记载的半导体器件制造方法中,特征是,上述羧酸为甲酸。
本发明第十一方面记载的半导体器件制造方法在本发明第七或第八方面记载的半导体器件制造方法中,特征是,在上述接合装置中,在将搬入到上述第二处理室内的上述半导体器件的上述焊接凸块熔融并接合至上述端子时,对上述第二处理室内进行减压。
发明效果
依据本发明,由于将进行焊接凸块接合至端子的接合装置和还原端子表面的氧化膜的氧化装置分别设置,因此在还原装置中进行一个半导体器件中的端子表面的氧化膜的还原期间,在接合装置中能够进行另一个半导体器件中的端子和焊接凸块的接合,由此,能够防止半导体器件的制造的生产率的降低。
附图说明
图1是概略地表示本发明的实施形态的半导体器件制造系统的结构的水平剖面图。
图2是概略地表示图1中的叠层芯片的结构的剖面图,图2(A)表示实施还原处理和回流(焊)处理(reflow process)之前的结构,图2(B)表示实施了还原处理和回流焊处理以后的结构。
图3是沿着图1中的线III-III的剖面图,是概略地表示图1中的芯片还原装置的结构的剖面图。
图4是沿着图1中的线IV-IV的剖面图,是概略地表示图1中的芯片接合装置的结构的剖面图。
图5是用于说明在图1的半导体器件制造系统中执行的还原处理以及回流焊处理的工艺图。
图6是用于说明在图1的半导体器件制造系统中执行的还原处理以及回流焊处理的工艺图。
图7是用于说明在图1的半导体器件制造系统中执行的还原处理以及回流焊处理的工艺图。
具体实施方式
以下,参照附图说明本发明的实施形态。
图1是概略地表示本实施形态的半导体器件制造系统的结构的水平剖面图。另外,图1中,为了使说明简单,表示除去了半导体器件制造系统具备的各种装置的上部机构以外的状态的水平剖面图。
图1中,半导体器件制造系统10具备叠层了多个IC电路(芯片)11的芯片叠层装置12、对叠层了多个芯片11的芯片的组(以下,称为「叠层芯片」)13实施还原处理的芯片还原装置14、对叠层芯片13实施回流焊处理的芯片接合装置15、跨越芯片叠层装置12、芯片还原装置14和芯片接合装置15架设的导轨16。
芯片叠层装置12、芯片还原装置14和芯片接合装置15配置成一列,特别是,芯片还原装置14和芯片接合装置15相互连接地配置。
芯片叠层装置12具备载置排列了多个芯片11的切割薄膜(dicingfilm)17的芯片放置地18、支承于导轨16的输送托盘19、使芯片11移动的拾取单元20、填充焊膏(solder paste)的浸渍单元21、拍摄由拾取单元20拾取的芯片11的下表面的照相机单元22、载置按芯片11的种类交换的拾取单元20的各种拾取头工具的工具交换单元23。
在芯片叠层装置12中,拾取单元20从芯片放置地18拾取1个芯片11,使其向浸渍单元21移动,使芯片11的下表面浸渍于焊膏,在该下表面附着焊膏,进而,使芯片11向照相机单元22移动,拍摄芯片11的下表面,确认附着在该下表面的焊膏的状态。然后,使芯片11向输送托盘19移动,重叠到已经配置在该输送托盘19上的其它芯片11上。由此,在输送托盘19上,构成叠层了多个芯片11的叠层芯片13。在本实施形态中,在输送托盘19上构成8个叠层芯片13。
输送托盘19具有由导轨16支承的矩形平板状的支承托盘19a、装卸自由地载置在该支承托盘19a的2个芯片托盘19b。在本实施形态中,在芯片托盘19b的每一个,上述的叠层芯片13每4个配置为一列。另外,导轨16将载置叠层芯片13的输送托盘19从芯片叠层装置12向芯片还原装置14输送,进而从芯片还原装置14向芯片接合装置15输送。
从芯片叠层装置12向芯片还原装置14输送的输送托盘19中的2个芯片托盘19b收容在芯片还原装置14的还原室24内,在该还原室24内,对各叠层芯片13实施还原处理。另外,从芯片还原装置14向芯片接合装置15输送的输送托盘19中的2个芯片托盘19b收容在芯片接合装置15的回流焊室25内,在该回流焊室25内,对各叠层芯片13实施回流焊处理。关于芯片还原装置14以及芯片接合装置15的结构、作用的详细情况在后面叙述。
图2是概略地表示图1中的叠层芯片的结构的剖面图,图2(A)表示实施还原处理以及回流焊处理前的结构,图2(B)表示实施了还原处理以及回流焊处理以后的结构。
如图2(A)所示,叠层芯片13在配置在最下方的基底芯片28上叠层多个芯片11而构成。在基底芯片28的上表面上形成多个电极垫盘29,在各芯片11的下表面上形成多个焊接凸块26,并且以避开该焊接凸块26的方式形成绝缘层30,另一方面,在芯片11的上表面上形成有多个端子27。芯片11的下表面的焊接凸块26由在浸渍单元21中附着到芯片11的下表面的焊膏形成。在各芯片11中,下表面的焊接凸块26与上表面的端子27通过在厚度方向贯通该芯片11的配线,例如TSV(未图示)连接。
在构成叠层芯片13时,在芯片叠层装置12中,以使基底芯片28的上表面的各端子27与芯片11的下表面的各焊接凸块26抵接的方式,向基底芯片28叠放芯片11,进而,使得在芯片11的上表面的各端子27与另一个芯片11的下表面的各焊接凸块26抵接的方式,向基底芯片28叠放芯片11,以后,反复进行芯片11的重叠。这时,由于端子27以及焊接凸块26的厚度的总合比绝缘层30的厚度大,因此在向叠层芯片13实施回流焊处理之前,在下面的芯片11的上表面不与上面的芯片11的绝缘层30抵接。
另一方面,如果向叠层芯片13实施回流焊处理,则上面的芯片11的焊接凸块26熔融,与下面的芯片11的端子27接合,而这时由于焊接凸块26的形状破坏,因此上面的芯片11向下面的芯片11下沉,上面的芯片11的绝缘层30与下面的芯片11的上表面抵接(图2(B))。
在本实施形态中,在芯片叠层装置12中构成的各叠层芯片13与输送托盘19一起被输送向芯片还原装置14,该芯片还原装置14用羧酸例如甲酸,将各叠层芯片13中的芯片11的各个端子27的表面的氧化膜进行还原(还原处理),芯片接合装置15将实施了还原处理的叠层芯片13中的某个芯片11的焊接凸块26热熔融,与从其它芯片11的表面去除了氧化膜的端子27接合(回流焊处理)。由此,从叠层芯片13制造半导体器件。
图3是沿着图1中的III-III线的剖面图,是概略地表示图1中的芯片还原装置的结构的剖面图。
图3中,芯片还原装置14具备收容输送托盘19中的2个芯片托盘19b的筐体状的还原室24(第一处理室)、在还原室24内配置在底部的下部载物台31(载置台)、在还原室24的顶部向还原室24内突出的按压气缸32(按压装置)、向还原室24内供给作为还原剂的羧酸的蒸汽,例如甲酸蒸汽的还原剂供给装置33(羧酸供给装置)、将还原室24内减压的干式真空泵34(减压装置)、向还原室24内供给氮气的氮气供给管35、将还原室24内的气氛进行加热的加热器(未图示)。
下部载物台31在与搬入到还原室24内的输送托盘19的2个芯片托盘19b相对应的部分中有2个突出部31a。按压气缸32具有伸缩部32b(筒状部),其由内部32a与还原室24的外部连通,在大气中开放并从还原室24内分隔内部32a的筒状的伸缩自由的波纹管构成;和板状的抵接部32c,其设置在伸缩部32b的下部载物台31侧的顶端,配置成与下部放载物台31的突出部31a相对。在芯片还原装置14中,配置与载置在输送托盘19的叠层芯片13的数量相同的数量,即配置8个按压汽缸32。
还原室24能够划分成上部24a和下部24b,还原室24划分成上部24a和下部24b时,通过导轨16,输送托盘19搬入到上部24a以及下部24b之间,搬入的输送托盘19调整位置,使得芯片托盘19b与下部载物台31相对。输送托盘19的与垂直于基于导轨16的输送方向的方向(以下,称为「宽度方向」。)的长度比与宽度方向的还原室24的长度长,由此,在输送托盘19搬入到上部24a以及下部24b之间时,在上部24a的侧壁部以及下部24b的侧壁部之间,存在输送托盘19的一部分,具体地讲,存在支承托盘19a的一部分。另外,下部载物台31的与各突出部31a的宽度方向有关的长设定为比与各芯片托盘19b的宽度方向有关的长度小。
还原剂供给装置33作为羧酸不仅供给甲酸,还可以供给乙酸、丙烯酸、丙酸、丁酸、己酸、乙二酸、丁二酸、水杨酸、丙二酸、庚酸、辛酸、壬酸、乳酸、癸酸等。
在还原室24中,在输送托盘19被搬入到被划分的上部24a以及下部24b之间以后,上部24a以及下部24b将支承托盘19a的一部分夹在中间而结合。由此,将各芯片托盘19b与还原室24的外部隔断。
另外,如果将还原室24内减压,使压力比大气压低,则按压汽缸32被拉入到还原室24内,伸缩部32b伸长,抵接部32c如后述那样,与载置在下部载物台31的突出部31a的芯片托盘19b的叠层芯片13抵接。
图4是沿着图1中的线IV-IV的剖面图,是概略地表示图1中的芯片接合装置的结构的剖面图。
图4中,芯片接合装置15具备收容输送托盘19中的2个芯片托盘19b的筐体状的回流焊室25(第二处理室)、在回流焊室25内配置在底部的下部载物台36、在回流焊室25的顶部向回流焊室25内突出的按压活塞37、向回流焊室25内导入大气的大气导入管38、向回流焊室25内供给氮气的氮气供给管39、将回流焊室25内减压的干式真空泵40。另外,由于芯片接合装置15与芯片还原装置14分别设置,因此回流焊室25离开还原室24。
在芯片接合装置15中,配置与载置在输送托盘19的叠层芯片13的数量相同的数量,即8个按压活塞37,与输送托盘19中的2个芯片托盘19b相对应,设置2个下部载物台36。各按压活塞37配置成与下部载物台36相对,通过电机(未图示)等,构成为向下部载物台36自由移动。在各按压活塞37的设置在下部载物台36侧的前端的按压部37a以及各下部载物台36中埋设有加热器以及冷却机构,例如珀耳帖元件(都没有图示)。
回流焊室25也与还原室24相同,能够划分成上部25a和下部25b,在回流焊室25划分成上部25a和下部25b时,通过导轨16,输送托盘19被搬入到上部25a和下部25b之间,被搬入的输送托盘19调整位置,使得各芯片托盘19b与各下部载物台36相对。输送托盘19的与宽度方向有关的长度比与宽度方向有关的回流焊室25的长度长,由此,在输送托盘19被搬入到上部25a以及下部25b之间时,在上部25a的侧壁部以及下部25b的侧壁部之间,存在输送托盘19的一部分,具体地讲,存在支承托盘19a的一部分。另外,各下部载物台36的与宽度方向有关的长度设定为比各芯片托盘19b的与宽度方向有关的长度小。
在回流焊室25中,在输送托盘19被搬入到被划分成上部25a以及下部25b之间以后,上部25a以及下部25b将支承托盘19a的一部分夹在中间而结合。由此,将各芯片托盘19b与回流焊室25的外部隔断。这时,如后述那样,各下部载物台36载置芯片托盘19b,各按压活塞37的按压部37a按压载置在芯片托盘19b上的各叠层芯片13。
接着,说明在半导体器件制造系统10中执行的还原处理以及回流焊处理。
图5至图7是用于说明在图1的半导体器件制造系统中执行的还原处理以及回流焊处理的工艺图。
首先,如图5(A)所示,在芯片还原装置14中,还原室24被划分成上部24a和下部24b,输送托盘19被搬入到上部24a和下部24b之间,调整输送托盘19的位置,使得各芯片托盘19b与下部载物台31的各突出部31a相对。
接着,如图5(B)所示,上部24a和下部24b结合,将各芯片托盘19b与还原室24的外部隔断,而这时,各突出部31a与下部24b一起上升,抬起芯片托盘19b,使该芯片托盘19b从支承托盘19a脱离。
接着,干式真空泵34将还原室24内减压。这时,由于还原室24内的压力比大气压低,因此按压气缸32被拉入到还原室24内,抵接部32c抵接到芯片托盘19b上的叠层芯片13(图5(C))。
然后,还原剂供给装置33向还原室24内供给甲酸的蒸汽。由此,还原各叠层芯片13中的芯片11的各个端子27表面上的氧化膜,去除该氧化膜。进而,经过一定时间以后,干式真空泵34将还原室24内减压,排除该还原室24内存在的甲酸蒸汽。在去除氧化膜以及排出甲酸蒸汽的期间,由于各叠层芯片13被各按压气缸32的抵接部32c按压,因此在各叠层芯片13中,各芯片11不会上浮,另外,各芯片11的位置不会偏移。
接着,氮气供给管35向还原室24内供给氮气,将该还原室24内用氮气填充。这时,还原室24内的压力由于成为大于等于大气压,因此按压汽缸32移动,从还原室24内返回,抵接部32c脱离叠层芯片13(图6(A))。另外,由于还原室24内被氮气填充,在还原室24内没有残留的甲酸蒸汽,因此在还原室24再次划分成上部24a以及下部24b时,能够防止甲酸的蒸汽排放到大气中。
接着,还原室24划分成上部24a以及下部24b。这时,由于与下部24b一起,突出部31a也下降,因此芯片托盘19b也下降到支承托盘19a,再次载置到该支承托盘19a(图6的(B))。
接着,载置有图5(A)至图6(B)表示的实施了还原处理的叠层芯片13的输送托盘19,通过导轨16从上部24a以及下部24b之间被搬出,被搬向芯片接合装置15的回流焊室25。具体地讲,如图6(C)所示,在芯片接合装置15中,回流焊室25划分成上部25a和下部25b,输送托盘19被搬入到上部25a和下部25b之间,调整输送托盘19的位置,使各芯片托盘19b与各下部载物台36相对。这时,在输送托盘19的搬入之前,氮气供给管39向回流焊室25内供给氮气,将回流焊室25内用氮气填充。从而,输送托盘19在每一个都用氮气填充的还原室24内和回流焊室25内移动。
接着,如图7(A)所示,上部25a和下部25b结合,将各芯片托盘19b与回流焊室25的外部隔断,而这时,各下部载物台36与下部25b一起上升,抬起芯片托盘19b,使该芯片托盘19b从支承托盘19a脱离。
接着,各按压活塞37向载置在下部载物台36的芯片托盘19b下降,各按压部37a以规定值的荷载按压各芯片托盘19b上的各叠层芯片13(图7(B))。这时,按压部37a以及各下部载物台36的加热器将各叠层芯片13加热,将某个芯片11的焊接凸块26热熔融,使得与其它芯片11的端子27接合。
接着,在由按压部37a以及各下部载物台36的加热器将各叠层芯片13加热一定时间后,按压部37a以及各下部载物台36的冷却机构迅速地将各叠层芯片13冷却,使熔融的焊接凸块26硬化(图7(B))。
另外,在图6(C)的工艺(输送托盘19的搬入)至图7(B)的工艺(叠层芯片13的冷却)中,将回流焊室25内用氮气充填,压力维持为大气压。即,回流焊室25内与回流焊室25的外部不存在压力差,按压活塞37的按压部37a向叠层芯片13施加的规定值的荷载不会由于该压力差发生变化。从而,能够稳定地进行焊接凸块26以及端子27的接合,由此,能够制造稳定品质的半导体器件。
接着,干式真空泵40将回流焊室25内减压,从回流焊室25内去除氮气,接着,大气导入管38向回流焊室25内导入大气(图7(B))。由此,在为了搬出输送托盘19而将回流焊室25划分成上部25a以及下部25b时,氮气不会排放到大气中。
接着,回流焊室25划分成上部25a以及下部25b。这时,由于下部载物台36也与下部25b一起下降,因此芯片托盘19b也下降到支承托盘19a,再次载置到该支承托盘19a。
然后,通过导轨16,从上部25a以及下部25b之间搬出输送托盘19,结束还原处理以及回流焊处理。
依据本发明的实施形态的半导体器件制造系统10,由于芯片接合装置15与芯片还原装置14分别设置,因此在芯片还原装置14中,在还原1个叠层面芯片13中的端子27的表面上的氧化膜的期间,在芯片接合装置15中,能够接合其它叠层芯片13中的端子27以及焊接凸块26。即,能够同时执行图6(A)至图6(B)表示的还原处理和图6(C)至图7(C)表示的回流焊处理。其结果,能够防止与半导体器件的制造有关的生产率的降低。另外,由于芯片接合装置15的回流焊室25与芯片还原装置14的还原室24隔开,因此在回流焊室25的各种装置中不需要实施防腐蚀措施,由此,能够不需要进行过剩的防腐蚀措施。
在上述的半导体器件制造系统10中,由于芯片还原装置14以及芯片接合装置15相互连接,能够立即将在芯片还原装置14中去除了端子27表面的氧化膜的叠层芯片13向芯片接合装置15输送,由此,能够减少端子27的表面接触大气的时间。更具体地讲,在将输送托盘19从芯片还原装置14向芯片接合装置15移送时,通过将还原室24内以及回流焊室25内用氮气充填,能够防止端子27的表面接触大气。由此,能够防止去除了氧化膜的端子27的表面再次形成自然氧化膜。
另外,在上述的半导体器件制造系统10中,由于在还原处理中将还原室24内减压了以后,向该还原室24内供给甲酸的蒸汽,因此能够提高甲酸的相对浓度,由此,能够迅速地进行端子27表面的氧化膜的去除,同时,在叠层芯片13中,能够从相互抵接的焊接凸块26以及端子27之间去除气体,由此,能够防止在焊接凸块26以及端子27之间发生气孔。
进而,在上述的半导体器件制造系统10中,由于在回流焊处理中,在将叠层芯片13中的焊接凸块26熔融并向端子27接合时,将回流焊室25内减压,因此能够去除在焊接凸块26中发生的气体,由此,由此能够防止在焊接凸块26中残留气孔。
以上使用上述实施形态说明了本发明,但是本发明不限定于上述实施形态。
上述的芯片还原装置14具备按压气缸32,而由于在还原反应中不需要叠层芯片13的按压,因此只要能够达到芯片11不会从叠层芯片13飞散的程度,缓慢地进行甲酸蒸汽的供给和氧气的供给,则芯片还原装置14也不一定必须具备按压气缸32。
在上述的半导体器件制造系统10中,在叠层芯片13中实施了还原处理以及回流焊处理,而在没有将芯片叠层,在1个芯片中将焊接凸块向端子接合时,也可以使用半导体器件制造系统10,执行图5至图7表示的还原处理和回流焊处理。进而,输送托盘19通过导轨16输送,但输送托盘19的输送机构不限于此,例如也能够使用传送带。
符号说明
10:半导体器件制造系统
11:芯片
13:叠层芯片
14:芯片还原装置
15:芯片接合装置
24:还原室
25:回流焊室
26:焊接凸块
27:端子
31、36:下部载物台
31a:突出部
32:按压气缸
33:还原剂供给装置
34、40:干式真空泵
35、39:氮气供给管
37:按压活塞
Claims (11)
1.一种半导体器件制造系统,其制造在端子接合有焊接凸块的半导体器件,该半导体器件制造系统的特征在于,包括:
还原装置,其具有第一处理室,在该第一处理室内将所述端子的表面的氧化膜还原;和
接合装置,其与所述还原装置分别设置,并且具有与所述第一处理室隔离的第二处理室,在该第二处理室中进行将所述焊接凸块与所述端子的接合。
2.如权利要求1所述的半导体器件制造系统,其特征在于:
所述还原装置和所述接合装置相互连接。
3.如权利要求1或2所述的半导体器件制造系统,其特征在于:
所述还原装置具有向所述第一处理室内供给氮的第一氮供给装置,所述接合装置具有向所述第二处理室内供给氮的第二氮供给装置。
4.如权利要求1或2所述的半导体器件制造系统,其特征在于:
所述还原装置具有:对所述第一处理室内进行减压的减压装置;配置在所述第一处理室内,载置所述半导体器件的载置台;和以与该载置台相对的方式向所述第一处理室内突出的按压装置,
该按压装置具有:
筒状部,其内部向大气开放,并将所述内部与所述第一处理室内分隔,并且朝向所述载置台自由地伸缩;和
抵接部,其设置于该筒状部的所述载置台侧的前端,当所述筒状部伸长时,与载置于所述载置台的半导体器件抵接。
5.如权利要求1或2所述的半导体器件制造系统,其特征在于:
所述还原装置具备向所述第一处理室内供给羧酸的羧酸供给装置。
6.如权利要求5所述的半导体器件制造系统,其特征在于:
所述羧酸为甲酸。
7.一种半导体器件制造方法,其为在半导体器件制造系统中执行的半导体器件制造方法,其特征在于:
所述半导体器件制造系统制造在端子接合有焊接凸块的半导体器件,所述半导体器件制造系统具备:具有第一处理室,在该第一处理室内将所述端子的表面的氧化膜还原的还原装置;和与该还原装置分别设置并具有与所述第一处理室隔离的第二处理室,在该第二处理室内进行将所述焊接凸块与所述端子接合的接合装置,
在所述还原装置中对一个半导体器件的所述端子的表面的氧化膜进行还原期间,在所述接合装置中将另一个半导体器件的所述端子和所述焊接凸块进行接合。
8.如权利要求7所述的半导体器件制造方法,其特征在于:
在将所述半导体器件从所述还原装置向所述接合装置移送时,将所述第一处理室内和所述第二处理室内用氮充填。
9.如权利要求7或8所述的半导体器件制造方法,其特征在于:
在所述还原装置中,在对搬入有所述半导体器件的所述第一处理室内进行减压后,向该第一处理室内供给羧酸。
10.如权利要求9所述的半导体器件制造方法,其特征在于:
所述羧酸为甲酸。
11.如权利要求7或8所述的半导体器件制造方法,其特征在于:
在所述接合装置中,在将搬入到所述第二处理室内的所述半导体器件的所述焊接凸块熔融并接合至所述端子时,对所述第二处理室内进行减压。
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CN104701220A (zh) * | 2013-12-09 | 2015-06-10 | 贝思瑞士股份公司 | 用于将基板的基板位置压紧的压紧器 |
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CN113348545A (zh) * | 2019-01-09 | 2021-09-03 | 库利克和索夫工业公司 | 将半导体元件焊接至基板的方法及相关焊接系统 |
CN113348545B (zh) * | 2019-01-09 | 2024-06-04 | 库利克和索夫工业公司 | 将半导体元件焊接至基板的方法及相关焊接系统 |
Also Published As
Publication number | Publication date |
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JP2013143542A (ja) | 2013-07-22 |
KR20130083400A (ko) | 2013-07-22 |
US20130181040A1 (en) | 2013-07-18 |
TW201342493A (zh) | 2013-10-16 |
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