TWI523121B - 鍵合方法及裝置 - Google Patents

鍵合方法及裝置 Download PDF

Info

Publication number
TWI523121B
TWI523121B TW102149205A TW102149205A TWI523121B TW I523121 B TWI523121 B TW I523121B TW 102149205 A TW102149205 A TW 102149205A TW 102149205 A TW102149205 A TW 102149205A TW I523121 B TWI523121 B TW I523121B
Authority
TW
Taiwan
Prior art keywords
bonding
package component
pair
thermal compression
package
Prior art date
Application number
TW102149205A
Other languages
English (en)
Other versions
TW201436059A (zh
Inventor
劉丙寅
黃信華
黃志輝
趙蘭璘
杜友倫
盧彥池
施俊吉
蔡嘉雄
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201436059A publication Critical patent/TW201436059A/zh
Application granted granted Critical
Publication of TWI523121B publication Critical patent/TWI523121B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7501Means for cleaning, e.g. brushes, for hydro blasting, for ultrasonic cleaning, for dry ice blasting, using gas-flow, by etching, by applying flux or plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75251Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75252Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/753Means for applying energy, e.g. heating means by means of pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009Pre-treatment of the bonding area
    • H01L2224/8001Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009Pre-treatment of the bonding area
    • H01L2224/8001Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013Plasma cleaning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053Bonding environment
    • H01L2224/80054Composition of the atmosphere
    • H01L2224/80065Composition of the atmosphere being reducing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053Bonding environment
    • H01L2224/80054Composition of the atmosphere
    • H01L2224/80075Composition of the atmosphere being inert
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8012Aligning
    • H01L2224/80121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802Applying energy for connecting
    • H01L2224/80201Compression bonding
    • H01L2224/80203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/80204Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802Applying energy for connecting
    • H01L2224/80201Compression bonding
    • H01L2224/80209Compression bonding applying unidirectional static pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034Bonding interfaces of the bonding area
    • H01L2224/80357Bonding interfaces of the bonding area being flush with the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808Bonding techniques
    • H01L2224/80894Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80905Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
    • H01L2224/80907Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909Post-treatment of the bonding area
    • H01L2224/80948Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Wire Bonding (AREA)

Description

鍵合方法及裝置
本發明係有關於一種鍵合方法。更具體地來說,本發明有關於封裝元件的鍵合方法與其裝置。
在晶圓與晶圓鍵合技術領域中,各種將兩個封裝元件(例如晶圓)鍵合在一起的方式已逐漸被開發,其中常見的可用鍵合方式包括融合鍵合(fusion bonding)、共晶鍵合(eutectic bonding)、直接金屬-金屬鍵合(direct metal-metal bonding)、混合鍵合(hybrid bonding)等等。在融合鍵合中,一晶圓上之氧化表面鍵合於另一晶圓上之氧化表面或矽表面。在共晶鍵合中,兩個共晶材料放置再一起,並施加高溫與高壓,因此共晶材料將會融化,當融化之共晶材料凝固,晶圓將鍵合在一起。在直接金屬-金屬鍵合中,兩金屬墊在升溫的環境下相互擠壓,而金屬的內擴散使金屬墊鍵合。在混合鍵合中,兩個晶圓上之金屬墊經由直接金屬-金屬鍵合而相互鍵合,且其中一晶圓之氧化表面鍵合於另一晶圓之氧化表面或矽表面。
先前發展的鍵合方法有其優點與缺點,舉例來說,融合鍵合僅需低壓力且可在室溫下施行,然而,因為兩個鍵合之晶圓之間沒有電性連接,需額外增加的電性連接線路使鍵合之晶圓互連。共晶鍵合不需要高品質的表面,因此要達成 鍵合在預先的準備上是很寬鬆的,然而,共晶鍵合之精密度很低,且在共晶鍵合的過程中,由於鍵合金屬的融化可能造成金屬擠壓的問題。直接金屬-金屬鍵合有較佳的精密度,然而其產量卻很低。在混合鍵合中,會產生介質分層之問題,其原因是來自於混合鍵合中的金屬墊相較於鍵合晶圓的介電層和矽表面擁有較高的熱膨脹係數,因此較易膨脹之金屬墊造成一晶圓之氧化表面分離於另一晶圓之氧化表面或矽表面。
為了解決上述問題點,本發明一實施例提供一鍵合方法包括以混合鍵合使第一封裝元件鍵合於第二封裝元件,從而形成一鍵合對。在前述鍵合對中,第一封裝元件上的第一金屬墊與第二封裝元件上的第二金屬墊經由直接金屬-金屬鍵合相互鍵合,而第一封裝元件表面之第一表面介電層與第二封裝元件表面之第二表面介電層經由融合鍵合相互鍵合。待混合鍵合完成後,熱壓縮退火將被施行於前述鍵合對。
本發明另一實施例中,混合鍵合形成複數個大致相同的鍵合對,當熱壓縮退火施行時,前述鍵合對設置於一底板和一頂板之間,且位於同一水平面,並有一壓力作用於前述頂板。
本發明另一實施例中,混合鍵合形成複數個大致相同的鍵合對,當熱壓縮退火施行時,前述鍵合對堆疊地設置於一底板和一頂板之間,並有一壓力作用於前述頂板。
本發明另一實施例中,混合鍵合形成複數個大致相同的鍵合對,當熱壓縮退火施行時,前述鍵合對分別地設置 於複數個隔板上,前述隔板利用一導軌引導,並有一壓力作用於前述鍵合對。
本發明另一實施例中,用於鍵合第一封裝元件與第二封裝元件之一鍵合設備包括有一預鍵合站,前述預鍵合站用以使第一封裝元件和第二封裝元件經由混合鍵合相互鍵合。此外,鍵合設備更包括一熱壓縮退火站,前述熱壓縮退火站包括一加壓工具用以使第一封裝元件朝向第二封裝元件擠壓,以及一加熱器用以加熱第一封裝元件和第二封裝元件。
本發明另一實施例中,鍵合裝置更包括一表面處理站,用於處理第一封裝元件和第二封裝元件之表面。
100‧‧‧第一封裝元件
102‧‧‧半導體基板
104‧‧‧主動元件
106‧‧‧金屬線路與接點
108‧‧‧介電層
110‧‧‧第一表面介電層
112‧‧‧第一金屬墊
200‧‧‧第二封裝元件
202‧‧‧半導體基板
204‧‧‧主動元件
206‧‧‧金屬線路與接點
208‧‧‧介電層
210‧‧‧第二表面介電層
212‧‧‧第二金屬墊
300‧‧‧裝置
302‧‧‧裝載站
304‧‧‧表面處理站
306‧‧‧表面清理站
308‧‧‧預鍵合站
310‧‧‧熱壓縮退火站
312‧‧‧卸載站
314‧‧‧運輸工具
320‧‧‧箭頭
322‧‧‧去離子水
324‧‧‧鍵合對
326‧‧‧壓力
327‧‧‧加壓器
328‧‧‧頂板
328a‧‧‧平面
330‧‧‧底板
330a‧‧‧平面
332‧‧‧壓力
333‧‧‧加壓器
334‧‧‧加熱器
336‧‧‧隔板
338‧‧‧導軌
第1~6圖係表示本發明一些實施例中,兩個封裝元件在鍵合之中間階段的剖視圖。
第7~10圖係表示本發明另一些實施例,鍵合封裝元件過程中的熱壓縮退火示意圖。
第11圖係表示本發明一實施例中,鍵合封裝元件的流程和執行鍵合之裝置示意圖。
以下說明本發明實施例之製作與使用。然而,可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明,並非用以侷限本發明的範圍。
封裝元件的鍵合方法以及施行鍵合所需之裝置在 數個較佳的實施例中提出,而鍵合過程的中間階段亦會介紹。裝置和鍵合方法的變化將會在實施例中討論,各處不同的視角和介紹的實施例中,使用相同的標號來表示相同或相似的部件。
第1圖至第6圖係表示本發明一實施例之鍵合過程中間階段的剖視圖,過程中的步驟可由第11圖所示之裝置300所執行,簡要的流程在此簡單的介紹,而流程與裝置300的細節將由第1圖至第6圖所討論。請參閱第11圖,相互鍵合的封裝元件(例如第1、2圖分別所示之第一封裝元件100和第二封裝元件200)經由裝載站302被加載至裝置300,前述裝載站302例如可為一承載室。接著,表面處理被施行於封裝元件之表面,其中表面處理的執行位於一表面處理站304中。表面清理會緊接著施行於封裝元件,用於清除封裝元件表面上之化學藥品、微粒或其他不良物質。在一些實施例中,表面清理站306被設置,用於施行表面清理。
接著,執行預鍵合使封裝元件相互鍵合,各個鍵合方法可為混合鍵合。預鍵合在預鍵合站308中執行,待預鍵合結束後,封裝元件會相互鍵合,且經由接下來的熱壓縮退火,鍵合強度將有所提升,前述熱壓縮退火施行於熱壓縮退火站310。運輸工具314用於運送封裝元件往來各站304、306、308和310之間,運輸工具314可包括承載室、機械手臂、運輸軌道等等,可用於自動運輸封裝元件從一站至另一站,藉此鍵合過程可自動化。待鍵合過程完成後,鍵合之封裝元件藉由卸載站312由裝置300卸載,前述卸載站312例如可包括機械手臂。
請參閱第1圖,一第一封裝元件100可以是一元件晶圓(device wafer)、一封裝基板(packaged substrate)或一內插晶圓(interposer wafer)等等。在本實施例中,第一封裝元件100為一元件晶圓,包括一半導體基板102,舉例來說,該半導體基板102可能為一矽基板,當然亦可使用其他種類的半導體基板。主動元件104形成於基板102之表面,例如一電晶體。金屬線路與接點106形成於介電層108,在一些實施例中,介電層108可能為低介電常數材料層(low-k dielectric layers),然而介電層108亦可能具有介電常數大於3.9之非低介電常數材料。金屬線路與接點106可能具有銅、鋁、鎳、鎢或其合金等材料,並與主動元件104相互連接,可連接主動元件104至覆蓋之第一金屬墊112。
在另一實施例中,第一封裝元件100為內插晶圓,可不包括主動元件。根據一些實施例,第一封裝元件100可以包括一被動元件(未顯示),例如電阻、電容、感應器、變壓器等等,當然亦可不包括。
在又一實施例中,第一封裝元件100為一封裝基板。在一些實施例中,第一封裝元件100為一層疊封裝基板(laminate package substrate),其中金屬線路與接點106嵌埋於層疊的介電層108。在另一實施例中,第一封裝元件100為組合封裝基板(built-up package substrates)(未圖示),包括一核心,而傳導路徑(例如金屬線路與接點)設置於核心的兩相反側,且兩側之傳導路徑經由核心的傳導特性相互連接。
在前述各個實施例中的第一封裝元件100,例如元 件晶圓、內插晶圓或封裝基板等等,第一表面介電層110形成於第一封裝元件100之表面。在一些實施例中,第一表面介電層110為氧化層,可能包括有氧化矽(silicon oxide)、氮氧化矽(SiON)、氮化矽(SiN)等等。第一金屬墊112形成於第一表面介電層110,且可經由金屬線路與接點106電耦接至主動元件104。第一金屬墊112可由銅、鋁、鎳、鎢或其合金所形成,第一表面介電層110與第一金屬墊112的表層大致位於同一水平面。儘管第1圖係表示第一表面介電層110及第一金屬墊112位於基板102之前側(設置主動元件之一側),然而應當理解到,在第一封裝元件100為元件晶圓的實施例中,作用於後續鍵合作用之第一表面介電層110及第一金屬墊112可能位於基板102之前側或後側。
第2圖係表示一第二封裝元件200,用於與第一封裝元件100鍵合。第二封裝元件200亦可為元件晶圓、內插晶圓或封裝基板其中之一,在第2圖中,第二封裝元件200包括基板202、主動元件204、介電層208、金屬線路與接點206(位於介電層208內)、第二表面介電層210和第二金屬墊212。第二封裝元件200可具有與前述第一封裝元件100相似的結構,故其細節不再重複描述。第二封裝元件200的材料特徵可在關於第一封裝元件100中相似的特徵找到,像是第一封裝元件100中「1」開頭的元件符號即對應第二封裝元件200中「2」開頭的元件符號。
接著請參閱第3圖,第一封裝元件100被加載至表面處理站304,如第11圖所示,表面處理站304為裝置300的一 部分,並可利用裝載站302執行加載。回到第3圖,表面處理(以箭頭320表示)施行於第一封裝元件100之表面,當酸處理(acid treatment)施行時,第一金屬墊112和第一表面介電層110之表面將被酸所處理,例如甲酸(HCOOH)。經由酸,可去除第一金屬墊112表面的金屬氧化物,一些位於第一金屬墊112和第一表面介電層110表面的微粒和不良物質也將被去除。
表面處理站304內的電漿處理(plasma treatment)將在一真空環境(真空室)下執行,舉例來說,也許是表面處理站304的一部分(第3圖以及第11圖)。用於產生電漿之處理氣體可包括一第一組合氣體、第二組合氣體或第三組合氣體,其中第一組合氣體具有氫氣和氬氣,第二組合氣體具有氫氣和氮氣,第三組合氣體具有氫氣和氦氣。在一些較佳的實施例中,氫氣在用於電漿處理的第一、第二和第三組合氣體大致介於4%~5%之間,氫氣有助於減少第一金屬墊112上之金屬氧化物回到金屬上。此外,經由此一處理,第一表面介電層110表面的羥基(OH groups)數量將會提升,有利於構成強力的融合鍵合。電漿處理亦可使用純粹或大致純粹的氫氣、氬氣或氮氣,如同處理氣體,係經由還原反應(reduction)和/或轟擊(bombardment)處理第一金屬墊112和第一表面介電層110之表面。使用於處理的電漿可能為低功率電漿(low-power plasma),其產生電漿之功率大致介於10瓦特至2000瓦特之間。在表面處理中,第一金屬墊112和第一表面介電層110之表面粗度相較於表面處理之前將不會改變或可保持(例如小於10Å,有部分原因即來自於低功率。
藉由如第3圖所示之表面處理站304,第二封裝元件200的處理方式亦等同於第一封裝元件100。接著,請參閱第4圖,第一封裝元件100被運輸至表面清理站306,並被施予表面清理的作業。在一些實施例中,表面清理包括噴灑去離子水322(De-Ionized,DI)在第一封裝元件100上來清洗。在另一實施例中,使用氫氧化銨(NH4OH)來清理表面。表面清理同樣施行於第二封裝元件200,其清理步驟基本等同於第4圖所示。
接著,如第5圖所示,第一封裝元件100和第二封裝元件200被運輸至預鍵合站308(請一併參閱第11圖),對齊第一封裝元件100和第二封裝元件200,且第一封裝元件100之第一金屬墊112與第二封裝元件200之第二金屬墊212對齊。對齊之步驟可於預鍵合站308中執行,然而亦可於一分離之對齊站中執行。待對齊之步驟完成後,使第一封裝元件100和第二封裝元件200相對於彼此互相擠壓,可利用一壓銷(未圖示)針對單一位置擠壓第二封裝元件200,而不是同時擠壓複數個第二封裝元件200上之位置。如此一來,第一封裝元件100和第二封裝元件200之間的任何空氣都將被擠出。
再請繼續參閱第5圖,在預鍵合的過程中,使用一加壓器327提供壓力326,壓力326使第一封裝元件100和第二封裝元件200相對於彼此互相擠壓。壓力326可低於5牛頓,且可作用在第一封裝元件100和第二封裝元件200的中央。預鍵合可能在室溫(例如大致接近21℃)下被執行,而鍵合時間可能小於一分鐘。
預鍵合是一種混合鍵合,其中第一金屬墊112和第 二金屬墊212經由直接金屬-金屬鍵合(direct metal-to-metal bonding)相互鍵合,而第一表面介電層110和第二表面介電層210則是經由融合鍵合(fusion bonding)相互鍵合。第一封裝元件100和第二封裝元件200經由預鍵合而成的組合,在整個說明書中被稱為鍵合對324。
由於在預鍵合中使用相對的低壓和低溫,鍵合對324的鍵合強度需要有所改善,可經由熱壓縮退火(thermal compression annealing)達到改善鍵合強度之目的,其中一些實施例如第6圖所示。第6圖係表示熱壓縮退火站310的一部分(同樣請參閱第11圖),在熱壓縮退火的過程中,加壓器333可經由液壓或氣壓(加壓工具)提供一壓力332。在一些實施例中,壓力332大致介於5000牛頓和350000牛頓之間,由第一封裝元件100和第二封裝元件200上之第一金屬墊112和第二金屬墊212的密度和面積所決定。
在熱壓縮退火的過程中,第一封裝元件100和第二封裝元件200的溫度可能會提升至超過約200℃,且大致介於300℃和450℃之間,為了退火第一金屬墊112和第二金屬墊212之間的鍵合。熱壓縮退火的時間大致介於0.5小時至4小時之間,熱壓縮退火站310可能充滿著氫氣、氮氣等,並可達到一大氣壓或更高。
退火使第一金屬墊112和第二金屬墊212產生內擴散,因此第一金屬墊112和第二金屬墊212之間的鍵合將會增強。不論如何,第一金屬墊112和第二金屬墊212的熱膨脹係數大於第一表面介電層110和第二表面介電層210,如此一來,由 於熱壓縮退火的溫度提升,第一金屬墊112和第二金屬墊212會較第一表面介電層110和第二表面介電層210更為膨脹,其表面分別趨於凸出第一表面介電層110和第二表面介電層210之表面,使得第一表面介電層110和第二表面介電層210彼此趨於分離。壓力332在熱壓縮退火的過程中被用於防止分離的情況,因為壓力332,第一表面介電層110和第二表面介電層210之間的融合鍵合亦得到增強。壓力332可在熱壓縮退火和第一封裝元件100及第二封裝元件200冷卻後移除。
第6圖係表示一單對的熱壓縮退火步驟,其中一單一鍵合對324被退火。鍵合對324放置於頂板328之下、底板330之上,為了能夠容納鍵合對324,因此底板330和頂板328的尺寸大於鍵合對324。底板330具有一平面330a,用於支撐鍵合對324,而頂板328亦具有一平面328a,用於均勻地供應壓力於鍵合對324的所有部分。壓力332可作用在頂板328上,且壓力332將被傳送至鍵合對324。在一些實施例中,加熱器334嵌於頂板328和/或底板330,用於加熱鍵合對324。在另一實施例中,加熱器334可設置於鍵合對324旁。
第7圖係表示另一實施例之熱壓縮退火,此一實施例與第6圖類似,除了複數個鍵合對324被夾在頂板328和底板330之間,前述複數個鍵合對324放置於同一水平面上,因此可同時退火並接受相同的壓力。其中複數個鍵合對324可具有相同的結構,熱壓縮退火站310因此被配置為可同時執行複數個鍵合對324的熱壓縮退火。藉由同時退火複數個鍵合對324,熱壓縮退火的處理量將得到改善。
第8圖係表示另一實施例之熱壓縮退火,其中堆疊的複數個鍵合對324被同時施行熱壓縮退火。在本實施例中,複數個鍵合對324被堆疊在頂板328和底板330之間,壓力332因此由最上方之一鍵合對324傳到最下方之另一鍵合對324,如此可傳送給所有的鍵合對324。在本實施例中,加熱器334可設置於鍵合對324旁,而額外的加熱器(未圖示)亦可設置於頂板328和底板330內。
第9、10圖係表示另一實施例之熱壓縮退火,此一實施例與第8圖類似,除了安裝導軌338,舉例來說,導軌338可被固定於底板330。隔板336可沿著導軌338滑動,鍵合對324設置在隔板336上,如第9圖所示,最初隔板336之間擁有足夠的間隔,使一個或多個的鍵合對324可以放置於前述各個隔板336上。接著,如第10圖所示,壓力332由上往下地被作用於頂板328,隔板336沿著導軌338向下移動,當接收到上方的鍵合對324傳來的力,其餘隔板336亦會將力傳至下方的鍵合對324。在熱壓縮退火的過程中,壓力332和提升的溫度會持續,舉例來說,經由加熱器334設置於鍵合對324旁。
在本發明揭露的實施例中,預鍵合後的封裝元件經由熱壓縮退火,直接金屬-金屬鍵合的鍵合強度將有所提升,而介電層之間容易分層的問題也獲得解決,此外,融合鍵合的鍵合強度也獲得改善。
在一些實施例中,一鍵合方法包括利用混合鍵合使第一封裝元件和第二封裝元件相互鍵合,從而形成一鍵合對。在鍵合對中,第一封裝元件上的第一金屬墊鍵合於第二封 裝元件上的第二金屬墊,而第一封裝元件表面之第一表面介電層鍵合於第二封裝元件表面之第二表面介電層。在混合鍵合完成後,熱壓縮退火將被施行於前述鍵合對。
在其他實施例中,一鍵合方法包括使第一晶圓對齊第二晶圓,且鍵合第一晶圓與第二晶圓,以形成一鍵合對。前述鍵合對包括直接金屬-金屬鍵合和融合鍵合,其中直接金屬-金屬鍵合包括第一晶圓上的第一金屬墊鍵合於第二晶圓上的第二金屬墊,而融合鍵合包括第一晶圓表面之第一表面介電層鍵合於第二晶圓表面之第二表面介電層。待鍵合步驟完成後,熱壓縮退火將被施行於前述鍵合對,在熱壓縮退火過程中,第一晶圓和第二晶圓將受到一壓力而互相擠壓。
在另一實施例中,用於鍵合第一封裝元件與第二封裝元件之一鍵合設備包括有一預鍵合站,前述預鍵合站用以使第一封裝元件和第二封裝元件經由混合鍵合相互鍵合。此外,鍵合設備更包括一熱壓縮退火站,前述熱壓縮退火站包括一加壓工具用以使第一封裝元件朝向第二封裝元件擠壓,以及一加熱器用以加熱第一封裝元件和第二封裝元件。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作更動、替代與潤飾。再者,本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟,任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法 及步驟,只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此,本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外,每一申請專利範圍構成個別的實施例,且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
300‧‧‧裝置
302‧‧‧裝載站
304‧‧‧表面處理站
306‧‧‧表面清理站
308‧‧‧預鍵合站
310‧‧‧熱壓縮退火站
312‧‧‧卸載站
314‧‧‧運輸工具

Claims (10)

  1. 一種鍵合方法,包括:執行一混合鍵合,使一第一封裝元件鍵合一第二封裝元件並形成一鍵合對,其中該第一封裝元件上之一第一金屬墊鍵合該第二封裝元件上之一第二金屬墊,且位於該第一封裝元件表面之一第一表面介電層鍵合位於該第二封裝元件表面之一第二表面介電層;以及待該混合鍵合結束後,施行一熱壓縮退火於該鍵合對。
  2. 如申請專利範圍第1項所述之鍵合方法,其中待混合鍵合結束後,該第一金屬墊經由直接金屬-金屬鍵合而鍵合於該第二金屬墊,且該第一表面介電層經由融合鍵合而鍵合於該第二表面介電層。
  3. 如申請專利範圍第1項所述之鍵合方法,其中該混合鍵合形成複數個大致相同的鍵合對,當該熱壓縮退火施行時,該些鍵合對設置於一底板和一頂板之間,且該些鍵合對位於同一水平面,並有一壓力作用於該頂板。
  4. 如申請專利範圍第1項所述之鍵合方法,其中該混合鍵合形成複數個大致相同的鍵合對,當該熱壓縮退火施行時,該些鍵合對堆疊地設置於一底板和一頂板之間,並有一壓力作用於該頂板。
  5. 如申請專利範圍第1項所述之鍵合方法,其中該混合鍵合形成複數個大致相同的鍵合對,當該熱壓縮退火施行時,該些鍵合對分別地設置於複數個隔板上,該些隔板藉由一導軌引導,並有一壓力作用於該些鍵合對。
  6. 一種鍵合裝置,用以鍵合一第一封裝元件於一第二封裝元件,包括:一預鍵合站,藉由混合鍵合方式鍵合該第一封裝元件於該第二封裝元件,並形成一鍵合對:以及一熱壓縮退火站,於該鍵合對上施行一熱壓縮退火,包括:一加壓工具,使該第一封裝元件朝向該第二封裝元件擠壓;以及一加熱器,加熱該第一封裝元件和該第二封裝元件。
  7. 如申請專利範圍第6項所述之鍵合裝置,其中該熱壓縮退火站更包括:一底板,該底板之尺寸大於該鍵合對;以及一頂板,該頂板之尺寸大於該鍵合對,其中該加熱器設置於該頂板或該底板。
  8. 如申請專利範圍第6項所述之鍵合裝置,其中該熱壓縮退火站更包括:一底板,該底板之尺寸大於該鍵合對;一導軌,相對於底板固定;一隔板,該隔板之尺寸大於該鍵合對,且該隔板藉由該導軌所引導;以及一頂板,該頂板之尺寸大於該鍵合對,且該頂板藉由該導軌所引導。
  9. 如申請專利範圍第8項所述之鍵合裝置,其中該加熱器設置於導軌之一側。
  10. 如申請專利範圍第6項所述之鍵合裝置,其中該鍵合裝置更 包括一表面處理站,用於處理該第一封裝元件和該第二封裝元件之表面。
TW102149205A 2013-03-06 2013-12-31 鍵合方法及裝置 TWI523121B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/787,566 US9331032B2 (en) 2013-03-06 2013-03-06 Hybrid bonding and apparatus for performing the same

Publications (2)

Publication Number Publication Date
TW201436059A TW201436059A (zh) 2014-09-16
TWI523121B true TWI523121B (zh) 2016-02-21

Family

ID=51467824

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102149205A TWI523121B (zh) 2013-03-06 2013-12-31 鍵合方法及裝置

Country Status (3)

Country Link
US (1) US9331032B2 (zh)
CN (1) CN104037102B (zh)
TW (1) TWI523121B (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448750A (zh) * 2014-08-28 2016-03-30 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
US9559081B1 (en) * 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
CN105140144A (zh) * 2015-09-02 2015-12-09 武汉新芯集成电路制造有限公司 一种介质加压热退火混合键合方法
DE102015120156B4 (de) * 2015-11-20 2019-07-04 Semikron Elektronik Gmbh & Co. Kg Vorrichtung zur materialschlüssigen Verbindung von Verbindungspartnern eines Leistungselekronik-Bauteils und Verwendung einer solchen Vorrichtung
US9893028B2 (en) 2015-12-28 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bond structures and the methods of forming the same
US10636661B2 (en) * 2016-01-15 2020-04-28 Taiwan Semiconductor Manufacturing Company Ltd. Apparatus and method for wafer bonding
US10096569B2 (en) * 2017-02-27 2018-10-09 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
KR20210009426A (ko) 2018-06-13 2021-01-26 인벤사스 본딩 테크놀로지스 인코포레이티드 패드로서의 tsv
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
KR102518803B1 (ko) * 2018-10-24 2023-04-07 삼성전자주식회사 반도체 패키지
WO2020140212A1 (en) 2019-01-02 2020-07-09 Yangtze Memory Technologies Co., Ltd. Plasma activation treatment for wafer bonding
DE102019105465B3 (de) * 2019-03-04 2020-07-23 Danfoss Silicon Power Gmbh Drucksintervorrichtung und Verfahren zum Herstellen eines elektronischen Bauteils
WO2021059485A1 (ja) * 2019-09-27 2021-04-01 三菱電機株式会社 光半導体装置およびその製造方法
KR20210037431A (ko) * 2019-09-27 2021-04-06 삼성전자주식회사 본딩 헤드, 이를 포함하는 다이 본딩 장치 및 이를 이용한 반도체 패키지의 제조 방법
CN111243972B (zh) * 2020-02-24 2022-06-10 哈尔滨工业大学 一种多步协同表面活化低温混合键合方法
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
WO2023215598A1 (en) * 2022-05-05 2023-11-09 Adeia Semiconductor Bonding Technologies Inc. Low temperature direct bonding

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4573627A (en) 1984-12-20 1986-03-04 The United States Of America As Represented By The Secretary Of The Army Indium bump hybrid bonding method and system
US5318651A (en) * 1991-11-27 1994-06-07 Nec Corporation Method of bonding circuit boards
US7385283B2 (en) * 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
TWI331388B (en) * 2007-01-25 2010-10-01 Advanced Semiconductor Eng Package substrate, method of fabricating the same and chip package
US8278142B2 (en) * 2008-05-22 2012-10-02 Texas Instruments Incorporated Combined metallic bonding and molding for electronic assemblies including void-reduced underfill
US8528802B2 (en) * 2008-09-04 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method of substrate to substrate bonding for three dimensional (3D) IC interconnects
US20100193884A1 (en) * 2009-02-02 2010-08-05 Woo Tae Park Method of Fabricating High Aspect Ratio Transducer Using Metal Compression Bonding
TWI460844B (zh) * 2009-04-06 2014-11-11 King Dragon Internat Inc 具有內嵌式晶片及矽導通孔晶粒之堆疊封裝結構及其製造方法
US8072064B1 (en) * 2010-06-21 2011-12-06 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for making the same
US8104666B1 (en) * 2010-09-01 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal compressive bonding with separate die-attach and reflow processes
KR20120075182A (ko) * 2010-12-28 2012-07-06 삼성전자주식회사 다중 패브리-페로 공진 모드를 이용한 광변조기 및 상기 광변조기를 포함하는 3차원 영상 획득 장치
US8967452B2 (en) * 2012-04-17 2015-03-03 Asm Technology Singapore Pte Ltd Thermal compression bonding of semiconductor chips
US9362143B2 (en) * 2012-05-14 2016-06-07 Micron Technology, Inc. Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages

Also Published As

Publication number Publication date
CN104037102B (zh) 2017-07-04
TW201436059A (zh) 2014-09-16
US9331032B2 (en) 2016-05-03
US20140256087A1 (en) 2014-09-11
CN104037102A (zh) 2014-09-10

Similar Documents

Publication Publication Date Title
TWI523121B (zh) 鍵合方法及裝置
US11854795B2 (en) Integrate rinse module in hybrid bonding platform
TWI564106B (zh) 接合裝置以及接合方法
CN100437995C (zh) 半导体装置及其制造方法
US5090609A (en) Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals
JP5918008B2 (ja) 冷却器の製造方法
JP2009110995A (ja) 3次元実装方法及び装置
US20130181040A1 (en) Semiconductor device manufacturing system and semiconductor device manufacturing method
US9875986B2 (en) Micro-scrub process for fluxless micro-bump bonding
JP2012231080A (ja) 接合装置および接合方法
CN102347250A (zh) 凸块结构的形成方法及装置
KR101619460B1 (ko) 적층형 반도체 패키지의 제조장치
JP6651924B2 (ja) 接合体の製造方法、及び、パワーモジュール用基板の製造方法
JP2013012539A (ja) 圧着装置および圧着方法
US9521795B2 (en) Two-step direct bonding processes and tools for performing the same
US9224712B2 (en) 3D bond and assembly process for severely bowed interposer die
JP6055387B2 (ja) 接合方法、プログラム、コンピュータ記憶媒体及び接合システム
US8501545B2 (en) Reduction of mechanical stress in metal stacks of sophisticated semiconductor devices during die-substrate soldering by an enhanced cool down regime
KR101619455B1 (ko) 적층형 반도체 패키지의 제조방법
JP2013012542A (ja) 圧着装置および温度制御方法
JP2018041867A (ja) 放熱基板、及び放熱基板の製造方法
TW201332047A (zh) 晶片三維構裝方法