TW201332047A - 晶片三維構裝方法 - Google Patents

晶片三維構裝方法 Download PDF

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Publication number
TW201332047A
TW201332047A TW101135218A TW101135218A TW201332047A TW 201332047 A TW201332047 A TW 201332047A TW 101135218 A TW101135218 A TW 101135218A TW 101135218 A TW101135218 A TW 101135218A TW 201332047 A TW201332047 A TW 201332047A
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Taiwan
Prior art keywords
wafer
wafers
adhesive
dimensional
reducing agent
Prior art date
Application number
TW101135218A
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English (en)
Inventor
Eiji Yamaguchi
Itaru Iida
Muneo Harada
Ken Nakao
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Tokyo Electron Ltd
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Publication date
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Publication of TW201332047A publication Critical patent/TW201332047A/zh

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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
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Abstract

提供一種晶片三維構裝方法，可防止半導體元件之晶片之熱劣化，並可防止製造效率之降低。於晶片積層裝置之平台上對於下面晶片來積層上面晶片之際，使得下面晶片之上側表面之各配線端部與於上面晶片之下側表面所配置之各電極墊相對向，且於兩晶片之間介設含有會因加熱而消失之還原劑的黏著劑來使得兩晶片彼此黏著，將積層後之複數晶片移動到晶片加熱裝置之平台上後，對積層後之複數晶片進行加熱使得黏著劑消失，進而持續加熱來使得對向之各配線端部與各電極墊相接合。

Description

晶片三維構裝方法
本發明係關於一種積層複數晶片之晶片三維構裝方法。
近年來，為了降低半導體元件之接腳，乃開發出一種積層複數IC基板(晶片)來製造半導體元件之三維構裝方法。此三維構裝方法，係於各晶片形成將該晶片朝厚度方向貫通之導體所構成之配線例如TSV(Through Silicon Via)，使得一個晶片的配線端部與其他晶片之配線端部連接來形成三維電路(參見例如專利文獻1)。
此三維構裝方法，為了防止於半導體元件之各晶片相對位置出現偏移，乃於每當積層新的晶片而進行加熱時來將新的晶片之配線端部與其他晶片之配線端部利用配線本身的熔融接合或焊料接合來做連接。亦即，反覆進行晶片之積層以及加熱。
先前技術文獻
專利文獻1 日本特開2010-198869號公報
上述三維構裝方法，由於反覆進行晶片之積層以及加熱，故下層晶片受到無數次之熱經歷，其結果，該晶片之配線、膜等有劣化之虞。此外，由於必須於1個裝置(例如加熱裝置)反覆進行晶片之積層以及加熱，故該加熱裝置所占據之時間變長，而有製造效率降低之問題。
本發明之課題在於提供一種晶片三維構裝方法，可防止半導體元件之晶片之熱劣化、並可防止製造效率之降低。
為了解決上述課題，依據本發明之樣態，係提供一種晶片三維構裝方法，係將於板狀構件表面形成有電極之電子積體電路之複數晶片加以積層者；其特徵在於具有下述步驟：積層步驟，係於一個該晶片積層其他該晶片之際，使得一個該晶片之該電極與其他該晶片之該電極相對向，且於兩該晶片之間介設會因加熱而消失之黏著劑來使得兩該晶片彼此黏著；以及接合步驟，係對積層後之複數該晶片進行加熱使得該黏著劑消失，進而使得該對向之電極彼此接合。。
於本發明之樣態，該對向之電極中至少一者以會因加熱而消失之還原劑所被覆為佳。
於本發明之樣態，較佳為該黏著劑含有該還原劑，於該積層步驟中，該黏著劑係被覆兩該晶片之至少一者的表面。
於本發明之樣態，較佳為於該積層步驟中，該黏著劑係以避開該對向之電極的方式被覆兩該晶片之至少一者的表面。
於本發明之樣態，較佳為該黏著劑相對於該晶片表面之突出量大於該電極以及被覆該電極之該還原劑相對於該晶片表面之突出量。
依據本發明，由於對一個晶片積層其他晶片之際，係於兩晶片之間介設會因加熱而消失之黏著劑來讓兩晶片彼此黏著，並對積層後之複數晶片進行加熱來使得黏著劑消失，進而將對向之電極彼此接合，故可於各晶片之相對位置不致偏 移的情況下而於半導體元件之製造過程中使得積層後之複數晶片移動。其結果，晶片之積層以及加熱所使用之裝置可加以區分。亦即，無須以1個裝置來反覆進行晶片之積層以及加熱。此外，若使得晶片之積層以及加熱以個別的裝置來實施，則積層以及加熱能分別以1個製程來進行。藉此，下層晶片不會受到無數次之熱經歷。其結果，可防止半導體元件之晶片之熱劣化，並可防止製造效率之降低。
以下，針對本發明之實施形態參見圖式來說明。
首先，針對本發明之第1實施形態之晶片三維構裝方法來說明。
圖1係示意顯示由本發明之第1實施形態之晶片三維構裝方法所製造之半導體元件構成之截面圖。
圖1中，半導體元件10係複數IC基板(晶片)11所積層而構成者。各晶片11係具備有：由半導體(例如矽)所構成之板狀基板12；複數配線13，係由將該基板12朝厚度方向貫通之導體所構成；薄膜狀電極墊14，係和於基板12表面露出之各配線13的一端相對應來配置，由被覆各配線13一端之導體所構成。於半導體元件10，一個晶片11之配線13的端部(電極)係和在該一個晶片11上所配置之其他晶片11之電極墊14(電極)相接合。
其次，針對本實施形態之晶片三維構裝方法說明。此三維構裝方法如圖2所示般，係於各晶片11之間填充黏著劑 15而後將各晶片11彼此黏著。
圖3A、圖3B、圖4A、圖4B係用以說明本實施形態之晶片三維構裝方法之製程圖。
首先，於具備有腔室16、平台17(配置於該腔室16內)、噴嘴狀分配器18(供給黏著劑15)、以及臂部19(握持各晶片11使其移動)之晶片積層裝置20，如圖3A所示般，將晶片11以臂部19載置於平台17，利用分配器18來塗布黏著劑15，而將該被載置之晶片11的圖中上側表面加以全面覆蓋。分配器18係以於腔室16內移動自如的方式所構成，藉由平行移動於晶片11之上側表面來將黏著劑15塗布於該晶片11之上側表面。或是，也可使用平台17來進行晶片11之平行移動，而使得該晶片11相對於分配器18作相對性移動而將黏著劑15塗布於晶片11之上側表面。於本實施形態，黏著劑15包含還原劑，黏著劑15以及還原劑之成分係被調整成為可因受熱而氣化消失。
其次，利用臂部19將其他晶片11重疊於上側表面被黏著劑15所被覆之晶片11。此時，兩晶片11係以下面晶片11之各配線13端部和在上面晶片11之下側表面所配置之各電極墊14成為對向的方式進行積層，但由於兩晶片11間介設有黏著劑15，故下面晶片11之各配線13端部與上面晶片11之各電極墊14不會直接接觸。
其次，將積層後之複數晶片11從晶片積層裝置20移動至具備有腔室21、平台22(配置於該腔室21內)、內蓋23(對向於該平台22)、排氣裝置25(調整腔室21內之壓力)之晶片 加熱裝置24。此時，由於兩晶片11彼此因為黏著劑15之黏著力而黏著著，故積層後之複數晶片11，各晶片11對其他晶片11之相對位置不致偏移，下面晶片11之各配線13端部維持在和上面晶片11之各電極墊14相對向之狀態。此外，於晶片加熱裝置24，內蓋23構成為可朝平台22來移動自如，平台22以及內蓋23分別內設有未圖示之加熱器。之後，圖3B所示般，將積層後之複數晶片11載置於平台22，讓內蓋23抵接於該積層後之複數晶片11之最上部晶片11之上側表面。
其次，如圖4A所示般，將積層後之複數晶片11以內蓋23來朝平台22抵壓，並對腔室21內從未圖示之氣體供給裝置以流量3 l/分鐘以上來供給惰性氣體例如N2氣體，使得腔室21內之氧濃度降低至10~100ppm程度。再者，使得平台22或內蓋23之加熱器發熱來將積層後之複數晶片11加熱至140℃~200℃，使得各晶片11之金屬表面還原。
於晶片加熱裝置24之腔室21內，還原劑係於約100℃~160℃前後開始氣化，而於該氣化之際，露出於晶片11之上側表面的各配線13之端部受到還原使得該端部表面受到潔淨。之後，黏著劑15也於約150℃前後開始氣化，各晶片11間之黏著劑15會慢慢減少，至終全部黏著劑15消失，則露出於下面晶片11之上側表面的各配線13端部會和配置於上面晶片11之下側表面的各電極墊14相接觸。此時，由於各配線13之端部受到潔淨，此外，於腔室21內係填充N2氣體而減少O2氣體，故各配線13之端部不會立即氧化。藉此，可 防止各配線13之端部與各電極墊14之接觸不良，可確保導通。
其次，於各晶片11之金屬表面受到還原後，將腔室21內之壓力降低至例如25~200Pa程度，如圖4B所示般，即便全部的黏著劑15消失後，仍將積層後之複數晶片11以內蓋23來持續朝平台22抵壓，利用平台22或內蓋23之加熱器將積層後之複數晶片11加熱至更高溫例如280℃。此時，各配線13之端部受熱熔融而和各電極墊14相接合。其結果，構成半導體元件10。之後，結束本處理。
依據本實施形態之晶片三維構裝方法，於晶片積層裝置20，在下面晶片11重疊上面晶片11之際，係於兩晶片11之間介設會因加熱而氣化消失之黏著劑15來將兩晶片11彼此黏著，再對積層後之複數晶片11進行加熱使得黏著劑15消失，進而使得相對之各配線13端部與各電極墊14產生接合，故可於各晶片11之相對位置不致偏移的情況下於半導體元件10之製造過程中使得積層後之複數晶片11進行移動。其結果，可區分積層裝置與加熱裝置。亦即，無須於1個裝置反覆進行晶片11之積層以及加熱。此外，晶片11之積層以及加熱分別以晶片積層裝置20以及晶片加熱裝置24來實施，藉此，積層以及加熱能分別以1製程來進行。藉此，下層之晶片11不會受到無數次之熱經歷。其結果，可防止半導體元件10之晶片11的熱劣化，且可防止半導體元件10之製造效率的降低。
此外，上述三維構裝方法，由於黏著劑15包含還原劑， 該黏著劑15係全面被覆晶片11之上側表面，故下面晶片11與上面晶片11之間可確實地介設黏著劑15來將兩晶片11確實黏著，且還原劑與黏著劑15無須分開來塗布，故可提高晶片11之積層效率。
再者，上述三維構裝方法，將黏著劑15、還原劑予以加熱氣化之際，由於將腔室21內之壓力降低至25Pa~200Pa，故可促進黏著劑15、還原劑之氣化，可更為提高半導體元件10之製造效率。
上述三維構裝方法，係將在下面晶片11之上側表面所露出之各配線13端部與在上面晶片11之下側表面所配置之各電極墊14利用各配線13之熔融來接合，但亦可於露出於下面晶片11之上側表面的各配線13端部設置焊球或焊料凸塊，使得焊料熔融以將各配線13之端部與各電極墊14加以接合。
此外，於上述三維構裝方法係先使得黏著劑15消失來將各配線13端部與各電極墊14加以接合，但也可先將各配線13端部與各電極墊14加以接合後再使得黏著劑15消失。於此情況，塗布於各晶片11之上側表面的黏著劑15係避開各配線13端部來塗布，於各配線13端部與各電極墊14之接合之際，腔室21內之壓力上升以抑制黏著劑15之氣化。
其次，針對本發明之第2實施形態之晶片三維構裝方法來說明。
本實施形態，其構成、作用基本上和上述第1實施形態相同，故針對重複之構成、作用省略說明，以下針對不同之 構成、作用來說明。具體而言，如圖5所示般，於各晶片11之間，各配線13之端部僅以還原劑26所被覆，黏著劑27係以避開各配線13端部的方式來配置，此點有別於第1實施形態。
圖6A、圖6B、圖7A以及圖7B係用以說明本實施形態之晶片三維構裝方法之製程圖。
首先，於晶片積層裝置20，如圖6A所示般，將晶片11以臂部19載置於平台17，在該載置後之晶片11的圖中上側表面，以被覆各配線13端部的方式塗布還原劑26，且以避開各配線13端部的方式塗布黏著劑27。此時，黏著劑27相對於晶片11上側表面之突出量係調整為比各配線13端部以及被覆該端部之還原劑26相對於晶片11之上側表面的突出量來得大。此外，於本實施形態同樣地係以將還原劑26以及黏著劑27利用加熱來氣化消失的方式來調整成分。
其次，利用臂部19將其他晶片11重疊於上側表面塗布有還原劑26以及黏著劑27之晶片11處。此時，兩晶片11係以下面晶片11之各配線13端部和在上面晶片11之下側表面所配置之各電極墊14相對向的方式來積層，但由於兩晶片11之間介設還原劑26以及黏著劑27，故下面晶片11之各配線13端部與上面晶片11之各電極墊14不會直接接觸。
其次，將積層後之複數晶片11從晶片積層裝置20移動至晶片加熱裝置24。此時，由於兩晶片11彼此藉由黏著劑27之黏著力而黏著著，故於積層後之複數晶片11，各晶片11相對於其他晶片11之相對位置不致偏移，下面晶片11之 各配線13端部維持在和上面晶片11之各電極墊14相對向之狀態。之後，如圖6B所示般，將積層後之複數晶片11載置於平台22，使得內蓋23抵接於該積層後之複數晶片11的最上部之晶片11之上側表面。
其次，如圖7A所示般，將積層後之複數晶片11以內蓋23朝平台22做抵壓，而將N2氣體之供給量、積層後之複數晶片11之溫度、以及腔室21內之壓力設定為和第1實施形態為相同條件。此時，還原劑26係於約100~160℃前後開始氣化，而還原各配線13端部來潔淨該端部之表面。之後，黏著劑27也於約150℃前後開始氣化，至終全部的還原劑26以及黏著劑27皆消失，於是在下面晶片11之上側表面所露出之各配線13的端部會和在上面晶片11之下側表面所配置之各電極墊14相接觸。
其次，如圖7B所示般，即便所有的還原劑26以及黏著劑27消失後，仍將積層後之複數晶片11利用內蓋23朝平台22持續抵壓，利用平台22、內蓋23之加熱器來將積層後之複數晶片11加熱至更高溫例如280℃。此時，各配線13之端部會因受熱而熔融來和各電極墊14接合。其結果，構成半導體元件10。之後，結束本處理。
依據本實施形態之晶片三維構裝方法，於晶片積層裝置20中對下面晶片11重疊上面晶片11之際，係於兩晶片11之間介設會因加熱而氣化消失之黏著劑27然後使得兩晶片11彼此黏著，對積層後之複數晶片11進行加熱來使得黏著劑27消失，故和第1實施形態之晶片三維構裝方法同樣地， 可防止半導體元件10之晶片11之熱劣化，並可防止半導體元件10之製造效率之降低。
此外，本實施形態之晶片三維構裝方法，黏著劑27係以避開各配線13端部的方式塗布於晶片11之上側表面，故可減少黏著劑27之使用量，並可消除阻礙還原劑26對各配線13端部表面之還原。
再者，本實施形態之晶片三維構裝方法，黏著劑27相對於晶片11上側表面之突出量大於各配線13之端部以及覆蓋該端部之還原劑26相對於晶片11上側表面之突出量，故於積層複數晶片11之際，於各晶片11之間在還原劑26上方會產生間隙。其結果，受熱氣化之還原劑26會平順地從各晶片11間排出而可防止還原劑26之殘渣殘留於各晶片11間。
以上，針對本發明使用上述各實施形態來說明，但本發明不限於上述各實施形態。
11‧‧‧IC基板(晶片)
12‧‧‧板狀基板
13‧‧‧配線
14‧‧‧電極墊
15‧‧‧黏著劑
16‧‧‧腔室
17‧‧‧平台
18‧‧‧分配器
19‧‧‧臂部
20‧‧‧晶片積層裝置
21‧‧‧腔室
22‧‧‧平台
23‧‧‧內蓋
24‧‧‧晶片加熱裝置
25‧‧‧排氣裝置
26‧‧‧還原劑
27‧‧‧黏著劑
圖1係示意顯示本發明之第1實施形態之晶片三維構裝方法所製造之半導體元件構成之截面圖。
圖2係用以說明本實施形態之晶片三維構裝方法中之黏著劑之塗布形態的截面圖。
圖3A係用以說明本實施形態之晶片三維構裝方法之製程圖。
圖3B係用以說明本實施形態之晶片三維構裝方法之製程圖。
圖4A係用以說明本實施形態之晶片三維構裝方法之製程圖。
圖4B係用以說明本實施形態之晶片三維構裝方法之製程圖。
圖5係用以說明本發明之第2實施形態之晶片三維構裝方法之黏著劑以及還原劑之塗布形態之截面圖。
圖6A係用以說明本實施形態之晶片三維構裝方法之製程圖。
圖6B係用以說明本實施形態之晶片三維構裝方法之製程圖。
圖7A係用以說明本實施形態之晶片三維構裝方法之製程圖。
圖7B係用以說明本實施形態之晶片三維構裝方法之製程圖。
11‧‧‧IC基板(晶片)
15‧‧‧黏著劑
16‧‧‧腔室
17‧‧‧平台
18‧‧‧分配器
19‧‧‧臂部
20‧‧‧晶片積層裝置
21‧‧‧腔室
22‧‧‧平台
23‧‧‧內蓋
24‧‧‧晶片加熱裝置

Claims (5)

  1. 一種晶片三維構裝方法，係將於板狀構件表面形成有電極之電子積體電路之複數晶片加以積層者；其特徵在於具有下述步驟：積層步驟，係於一個該晶片積層其他該晶片之際，使得一個該晶片之該電極與其他該晶片之該電極相對向，且於兩該晶片之間介設會因加熱而消失之黏著劑來使得兩該晶片彼此黏著；以及接合步驟，係對積層後之複數該晶片進行加熱使得該黏著劑消失，進而使得該對向之電極彼此接合。
  2. 如申請專利範圍第1項之晶片三維構裝方法，其中該對向之電極之至少一者係由會因加熱而消失之還原劑所被覆。
  3. 如申請專利範圍第2項之晶片三維構裝方法，其中該黏著劑係含有該還原劑，於該積層步驟中，該黏著劑係被覆兩該晶片之至少一者的表面。
  4. 如申請專利範圍第2項之晶片三維構裝方法，其中於該積層步驟中，該黏著劑係以避開該對向之電極的方式被覆兩該晶片之至少一者的表面。
  5. 如申請專利範圍第4項之晶片三維構裝方法，其中該黏著劑相對於該晶片表面之突出量係大於該電極以及被覆該電極之該還原劑相對於該晶片表面之突出量。
TW101135218A 2011-09-27 2012-09-26 晶片三維構裝方法 TW201332047A (zh)

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