CN103165474A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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Publication number
CN103165474A
CN103165474A CN2012105368928A CN201210536892A CN103165474A CN 103165474 A CN103165474 A CN 103165474A CN 2012105368928 A CN2012105368928 A CN 2012105368928A CN 201210536892 A CN201210536892 A CN 201210536892A CN 103165474 A CN103165474 A CN 103165474A
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China
Prior art keywords
filling material
bottom filling
semiconductor device
semiconductor
adherend
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CN2012105368928A
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English (en)
Inventor
盛田浩介
高本尚英
千岁裕之
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Nitto Denko Corp
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Nitto Denko Corp
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Priority claimed from JP2011275995A external-priority patent/JP2013127997A/ja
Priority claimed from JP2011276003A external-priority patent/JP5889625B2/ja
Priority claimed from JP2011275997A external-priority patent/JP5907717B2/ja
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Publication of CN103165474A publication Critical patent/CN103165474A/zh
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Abstract

本发明提供能够抑制在半导体元件与底层填充片的界面中产生空隙而制造可靠性高的半导体装置的半导体装置的制造方法。本发明是具备被粘附体、与该被粘附体电连接的半导体元件、和将该被粘附体与该半导体元件之间的空间填充的底层填充材料的半导体装置的制造方法，其包括：准备具备支承材和层叠于该支承材上的底层填充材料的密封片的准备工序，使半导体晶片的形成有连接构件的电路面与上述密封片的底层填充材料在10000Pa以下的减压气氛、0.2MPa以上的按压、和40℃以上的热压接温度的条件下热压接的热压接工序，将上述半导体晶片切割而形成带有上述底层填充材料的半导体元件的切割工序，和用上述底层填充材料将上述被粘附体与上述半导体元件之间的空间填充并且经由上述连接构件将上述半导体元件与上述被粘附体电连接的连接工序。

Description

半导体装置的制造方法
技术领域
本发明涉及半导体装置的制造方法。
背景技术
基于电子机器的小型·薄型化的高密度安装的需求近年来急剧地增加。应这种需要，采用了将半导体晶片的背面(与形成有图案的电路面相反侧的面)研磨而将半导体装置薄型化的方法。半导体晶片的背面研磨一般通过使背面研磨用带贴合于半导体晶片的电路面，对半导体晶片的背面实施研磨加工而进行。
另一方面，对于半导体组件而言，适于高密度安装的表面安装型代替了以往的销插入型而成为主流。就该表面安装型而言，直接将引线焊接于印制电路板等。作为加热方法，可利用红外线回流焊、气相回流焊、浸焊等对组件整体进行加热而进行安装。
在表面安装后，为了半导体元件表面的保护、确保半导体元件与基板之间的连接可靠性，而进行了向半导体元件与基板之间的空间填充密封树脂。作为这样的密封树脂，广泛使用的是液状的密封树脂，但是对于液状的密封树脂来说，注入位置、注入量的调节是困难的。因此，还提出了使用片状的密封树脂(底层填充片)来填充半导体元件与基板之间的空间的技术(专利文献1)。
一般来说，在使用底层填充片的工艺中，采用了利用贴附于半导体元件的底层填充片来填充基板等被粘附体与半导体元件之间的空间，同时将半导体元件连接于被粘附体而进行安装这样的步骤。在上述工艺中，被粘附体与半导体元件之间的空间的填充变得容易。
专利文献
专利文献1：日本专利第4438973号
发明内容
发明所要解决的课题
但是，在上述工艺中需要考虑如下几点。
第1，在上述工艺中，从使导体晶片的电路面与底层填充片贴合出发，需要底层填充片追随半导体晶片表面的凹凸而与其密合。但是，伴随着半导体晶片上的凸点等立体结构物的数量的增加、电路的狭小化，存在底层填充片与半导体晶片的密合的程度降低，在半导体晶片与底层填充片之间产生空隙(气泡)的情况。若在半导体晶片与底层填充材料的界面存在气泡，则在以后的工序中，有时在进行减压处理、加热处理时气泡发生膨胀，而半导体晶片与底层填充材料之间的密合性降低，其结果是：在将半导体元件安装于被粘附体时，半导体元件与被粘附体的连接可靠性降低。另外，在半导体晶片的背面研磨、切割时水分混进气泡中的情况下，若在此之后进行加热工序，则该水分进行蒸发，气泡扩大或膨胀，结果导致半导体元件与被粘附体的连接可靠性降低。
第2，本申请发明人等为了使从半导体晶片的背面研磨或切割开始至半导体元件-被粘附体间的空间的填充为止的一系列的工序高效化，而尝试开展了使背面研磨用带与底层填充片组合的技术、或使切割带(DicingTape)与底层填充片组合的技术。对于这种技术而言，从使半导体晶片的电路面与底层填充片贴合出发，而需要底层填充片追随半导体晶片表面的凹凸而与其密合。但是，伴随半导体晶片上的凸点等立体结构物的数量的增加、电路的狭小化，存在底层填充片与半导体晶片的密合的程度降低，在半导体晶片与底层填充片之间产生空隙(气泡)的情况。若在半导体晶片与底层填充材料的界面中存在气泡，则在以后的工序中进行减压处理、加热处理时，存在气泡膨胀而半导体晶片与底层填充材料之间的密合性降低的情况，其结果是：在将半导体元件安装于被粘附体时，半导体元件与被粘附体的连接可靠性降低。另外，在半导体晶片的背面研磨、切割时水分混进气泡中的情况下，若在此之后进行加热工序，则该水分进行蒸发，气泡扩大或膨胀，结果导致半导体元件与被粘附体的连接可靠性降低。
本发明的目的在于提供能够抑制在半导体元件与底层填充片的界面中产生空隙，从而制造可靠性高的半导体装置的半导体装置的制造方法。
解决课题的手段
本申请发明人等对第1点进行了深入的研究，结果发现通过采用下述构成而能够实现前述目的，从而完成了本发明。
即，本发明是具备被粘附体、与该被粘附体电连接的半导体元件、和将该被粘附体与该半导体元件之间的空间填充的底层填充材料的半导体装置的制造方法；
其包括：
准备工序，准备具备支承材和层叠于该支承材上的底层填充材料的密封片，
热压接工序，使半导体晶片的形成有连接构件的电路面与上述密封片的底层填充材料在10000Pa以下的减压气氛、0.2MPa以上的按压、和40℃以上的热压接温度的条件下热压接，
切割工序，将上述半导体晶片切割而形成带有上述底层填充材料的半导体元件，和
连接工序，用上述底层填充材料将上述被粘附体与上述半导体元件之间的空间填充，并且经由上述连接构件将上述半导体元件与上述被粘附体电连接。
对于该制造方法而言，因为在10000Pa以下的减压气氛、0.2MPa以上的按压和40℃以上的热压接温度这样的特定的热压接条件下进行半导体晶片的电路面与底层填充材料的贴合，所以能够大幅地减少气体介于两者的界面中的存在，而提高密合性，由此能够抑制上述界面中的空隙的产生。其结果是能够高效率地制造半导体晶片与被粘附体的连接可靠性优异的半导体装置。
对于该制造方法而言，优选上述贴合工序后的上述半导体晶片与上述底层填充材料的界面(以下有时简单地称为“界面”)中基本上不存在气泡。由此，因为半导体晶片与底层填充材料之间的密合性提高，所以能够进一步提高半导体装置的连接可靠性。需说明的是，在本说明书中，“基本上不存在气泡”是指减压至用于贴合工序中的贴合的预定压力时通过目视没有确认出气泡的状态，且指不存在最大径为1mm以上的气泡。
对于该制造方法而言，优选在10～10000Pa的减压气氛、0.2～1MPa的按压、和40～120℃的热压接温度的条件下进行上述热压接工序。由此，能够充分地排出上述界面中的气体，并且能够防止底层填充材料的变形、防止连接构件向底层填充材料中的不慎进入。
热固化前的上述底层填充材料在上述热压接温度下的熔融粘度优选为20000Pa·s以下。由此，能够在热压接工序时使连接构件向底层填充材料中的进入变得容易。另外，能够防止半导体元件的电连接时的空隙的产生、和来自半导体元件与被粘附体之间的空间的底层填充材料的渗出。需说明的是，熔融粘度按照实施例中所述的步骤进行测定。
上述底层填充材料优选含有热塑性树脂和热固化性树脂。其中，上述热塑性树脂优选含有丙烯酸树脂，上述热固化性树脂优选含有环氧树脂和酚醛树脂。提高热压接工序中的底层填充材料与半导体晶片的密合性，从而能够平衡性良好地对底层填充材料赋予必要的柔软性、强度、粘接性。
在该制造方法中，上述底层填充材料的厚度T(μm)与上述连接构件的高度H(μm)之比(T/H)优选为0.5～2。通过使上述底层填充材料的厚度T(μm)与上述连接构件的高度H(μm)满足上述关系，从而能够充分地填充半导体元件与被粘附体之间的空间，并且能够防止来自该空间的底层填充材料的过剩的渗出，能够防止因底层填充材料造成的半导体元件的污染等。需说明的是，即使在连接构件的高度H的绝对值比底层填充材料的厚度T的绝对值大的情况下，只要满足上述关系，则由于安装时的连接构件的熔融且连接构件的高度H变低，因而也能够良好地进行半导体元件与被粘附体的电连接。
在该制造方法中，上述支承材可以为基材。另外，上述支承材可以为具备基材和层叠于该基材上的粘合剂层的背面研磨用带或者切割带。通过使背面研磨用带或切割带与底层填充材料一体化，从而能够在半导体晶片的背面研磨或切割时牢固地保持半导体晶片，简便地填充半导体元件与被粘附体之间的空间，在半导体装置的制造中可效率良好地进行从背面研磨或切割开始至电连接时的填充为止的工序。
本申请发明人等对第2点进行了深入的研究，结果发现通过采用下述构成而能够实现前述目的，从而完成了本发明。
即，本发明是具备被粘附体、与该被粘附体电连接的半导体元件、和将该被粘附体与该半导体元件之间的空间填充的底层填充材料的半导体装置的制造方法；
其包括：
准备工序，准备具备背面研磨用带和层叠于该背面研磨用带上的底层填充材料的密封片，
贴合工序，在1000Pa以下的减压下将半导体晶片的形成有连接构件的电路面与上述密封片的底层填充材料贴合，
研磨工序，对与上述半导体晶片的电路面相反侧的面进行研磨，
切割工序，切割上述半导体晶片而形成带有上述底层填充材料的半导体元件，和
连接工序，用上述底层填充材料将上述被粘附体与上述半导体元件之间的空间填充，并且经由上述连接构件将上述半导体元件与上述被粘附体电连接。
另外，本发明是具备被粘附体、与该被粘附体电连接的半导体元件、和将该被粘附体与该半导体元件之间的空间填充的底层填充材料的半导体装置的制造方法；
其包括：
准备工序，准备具备切割带和层叠于该切割带上的底层填充材料的密封片，
贴合工序，在1000Pa以下的减压下将半导体晶片的形成有连接构件的电路面与上述密封片的底层填充材料贴合，
切割工序，将上述半导体晶片切割而形成带有上述底层填充材料的半导体元件，和
用上述底层填充材料将上述被粘附体与上述半导体元件之间的空间填充，经由上述连接构件将上述半导体元件与上述被粘附体电连接的连接工序。
就该制造方法而言，因为在1000Pa以下的减压下进行半导体晶片的电路面与底层填充材料的贴合，所以能够大幅地减少气体介于两者的界面中的存在，从而提高密合性，由此能够抑制在上述界面中产生空隙。其结果是能够效率良好地制造半导体晶片与被粘附体的连接可靠性优异的半导体装置。另外，因为背面研磨用带与底层填充材料进行一体化、或者切割带与底层填充材料进行一体化，所以能够在半导体晶片的背面研磨或切割时牢固地保持半导体晶片，并且因为能够简便地填充半导体元件与被粘附体之间的空间，所以在半导体装置的制造中能够效率良好地进行从背面研磨或切割开始至电连接时的填充为止的工序。
就该制造方法而言，优选在上述贴合工序后的上述半导体晶片与上述底层填充材料的界面(以下有时简单地称为“界面”)中基本上不存在气泡。由此，因为半导体晶片与底层填充材料之间的密合性提高，所以能够进一步提高半导体装置的连接可靠性。需说明的是，在本说明书中，“基本上不存在气泡”是指减压至用于贴合工序中的贴合的预定压力为止时通过目视没有确认出气泡的状态，且指不存在最大径为1mm以上的气泡。
在该制造方法中，上述连接工序优选包括：
在下述条件(1)的温度α下使上述连接构件与上述被粘附体接触的工序，和
在下述条件(2)的温度β下将上述接触后的连接构件固定于上述被粘附体的工序。
条件(1)：连接构件的熔点-100℃≤α＜连接构件的熔点
条件(2)：连接构件的熔点≤β≤连接构件的熔点+100℃
通过采用包括上述规定工序的连接工序，从而在半导体元件与被粘附体的电连接时，首选在未达到连接构件的熔点的规定温度α的加热下使半导体元件的连接构件与被粘附体接触。由此，可使底层填充材料软化，容易使连接构件向底层填充材料进入，可使连接构件与被粘附体的接触达到充分的水平。因为在这种状态下、在连接构件的熔点以上的规定温度β下，将连接构件与被粘附体相互固定而得到电连接，所以能够效率良好地制造连接可靠性高的半导体装置。
就该制造方法而言，热固化前的上述底层填充材料在100～200℃下的最低熔融粘度优选为100Pa·s以上20000Pa·s以下。由此，能够使连接构件容易进入到底层填充材料中。另外，能够防止半导体元件的电连接时的空隙的产生、和防止来自半导体元件与被粘附体之间的空间的底层填充材料的渗出。需说明的是，最低熔融粘度的测定按照实施例中所述的步骤进行。
在该制造方法中，热固化前的上述底层填充材料在23℃下的粘度优选为0.01MPa·s以上100MPa·s以下。通过热固化前的底层填充材料具有这样的粘度，从而能够提高切割时的半导体晶片的保持性、作业时的操作性。
附图说明
图1是表示本发明的一实施方式所述的密封片的剖面示意图。
图2A是表示本发明的一实施方式所述的半导体装置的制造工序的剖面示意图。
图2B是表示本发明的一实施方式所述半导体装置的制造工序的剖面示意图。
图2C是表示本发明的一实施方式所述的半导体装置的制造工序的剖面示意图。
图2D是表示本发明的一实施方式所述的半导体装置的制造工序的剖面示意图。
图2E是表示本发明的一实施方式所述的半导体装置的制造工序的剖面示意图。
具体实施方式
<第1实施方式>
[准备工序]
就准备工序而言，准备具备支承材和层叠于该支承材上的底层填充材料的密封片。作为支承材，可很好地使用基材、背面研磨用带、切割带等。在本实施方式中，以使用背面研磨用带的情况为例进行说明。
(密封片)
如图1所示，密封片10具备背面研磨用带1、和层叠于背面研磨用带1上的底层填充材料2。需说明的是，如图1所示，底层填充材料2也可以不层叠于背面研磨用带1的整面，只要对于与半导体晶片3(参照图2A)的贴合而言，以充分的尺寸加以设置就好。
(背面研磨用带)
背面研磨用带1具备基材1a、和层叠于基材1a上的粘合剂层1b。需说明的是，底层填充材料2层叠于粘合剂层1b上。
(基材)
上述基材1a作为密封片10的强度母体。例如可举出低密度聚乙烯、直链状聚乙烯、中密度聚乙烯、高密度聚乙烯、超低密度聚乙烯、无规共聚聚丙烯、嵌段共聚聚丙烯、均聚聚丙烯、聚丁烯、聚甲基戊烯等聚烯烃，乙烯-乙酸乙烯酯共聚物、离聚物树脂、乙烯-(甲基)丙烯酸共聚物、乙烯-(甲基)丙烯酸酯(无规、交替)共聚物、乙烯-丁烯共聚物、乙烯-己烯共聚物、聚氨酯、聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二醇酯等聚酯、聚碳酸酯、聚酰亚胺、聚醚醚酮、聚酰亚胺、聚醚酰亚胺、聚酰胺、全芳香族聚酰胺、聚二苯硫醚、芳族聚酰胺(纸)、玻璃、玻璃布、氟树脂、聚氯乙烯、聚偏二氯乙烯、纤维素系树脂、硅酮树脂、金属(箔)、纸等。在粘合剂层1b为紫外线固化型的情况下，优选基材1a对紫外线具有透射性。
另外，作为基材1a的材料，可举出上述树脂的交联体等的聚合物。上述塑料膜可以无拉伸地使用，也可以根据需要来使用实施了单轴或双轴的拉伸处理的塑料膜。
为了提高基材1a的表面与邻接的层的密合性、保持性等，而可实施惯用的表面处理，例如铬酸处理、臭氧暴露、火炎暴露、高压电击暴露、离子化放射线处理等化学或物理处理、利用底涂剂(例如后述的粘合物质)的涂布处理。
上述基材1a可适当地选择同种或不同种的基材来使用，根据需要，可使用将数种基材混合而得的基材。另外，为了对基材1a赋予抗静电性，而可在上述基材1a上设置由金属、合金、它们的氧化物等构成的厚度为
Figure BDA00002570898200081
左右的导电性物质的蒸镀层。基材1a可以为单层或2种以上的多层。
基材1a的厚度可适当地确定，一般而言为5μm以上200μm以下左右，优选为35μm以上120μm以下。
需说明的是，在不损害本发明的效果等的范围内，基材1a可含有各种添加剂(例如着色剂、填充剂、增塑剂、抗老化剂、抗氧化剂、表面活性剂、阻燃剂等)。
(粘合剂层)
就用于粘合剂层1b的形成的粘合剂而言，只要是在背面研磨和切割时经由底层填充材料而牢固地保持半导体晶片或半导体芯片、在拾取时能够将带有底层填充材料的半导体芯片控制为可剥离状态的粘合剂，就没有特别限制。例如可使用丙烯酸系粘合剂、橡胶系粘合剂等一般的感压性粘接剂。作为上述感压性粘接剂，从忌避半导体晶片、玻璃等的污染的电子零件利用超纯水、醇等有机溶剂的清洁洗涤性等方面出发，优选为将丙烯酸系聚合物作为基底聚合物的丙烯酸系粘合剂。
作为上述丙烯酸系聚合物，可举出将丙烯酸酯用作主要单体成分的聚合物。作为上述丙烯酸酯，例如可举出将(甲基)丙烯酸烷基酯(例如甲基酯、乙基酯、丙基酯、异丙基酯、丁基酯、异丁基酯、仲丁基酯、叔丁基酯、戊基酯、异戊基酯、己基酯、庚基酯、辛基酯、2-乙基己酯、异辛基酯、壬基酯、癸基酯、异癸基酯、十一烷基酯、十二烷基酯、十三烷基酯、十四烷基酯、十六烷基酯、十八烷基酯、二十烷基酯等烷基的碳数为1～30、尤其是碳数为4～18的直链状或支链状的烷基酯等)和(甲基)丙烯酸环烷基酯(例如环戊基酯、环己基酯等)中的1种或2种以上用作单体成分的丙烯酸系聚合物等。需说明的是，(甲基)丙烯酸酯是指丙烯酸酯和/或甲基丙烯酸酯，本发明的(甲基)均为相同的意思。
对于上述丙烯酸系聚合物而言，以凝聚力、耐热性等的改性为目标，根据需要，可含有与能够与上述(甲基)丙烯酸烷基酯或环烷基酯共聚的其他的单体成分相对应的单元。作为这样的单体成分，例如可举出：丙烯酸、甲基丙烯酸、羧乙基(甲基)丙烯酸酯、羧戊基(甲基)丙烯酸酯、衣康酸、马来酸、富马酸、巴豆酸等含有羧基的单体；马来酸酐、衣康酸酐等酸酐单体；(甲基)丙烯酸2-羟基乙酯、(甲基)丙烯酸2-羟基丙酯、(甲基)丙烯酸4-羟基丁酯、(甲基)丙烯酸6-羟基己酯、(甲基)丙烯酸8-羟基辛酯、(甲基)丙烯酸10-羟基癸酯、(甲基)丙烯酸12-羟基月桂酯、(4-羟基甲基环己基)甲基(甲基)丙烯酸酯等含有羟基的单体；苯乙烯磺酸、烯丙基磺酸、2-(甲基)丙烯酰胺-2-甲基丙烷磺酸、(甲基)丙烯酰胺丙烷磺酸、磺基丙基(甲基)丙烯酸酯、(甲基)丙烯酰氧基萘磺酸等含有磺酸基的单体；2-羟乙基丙烯酰基磷酸酯等含有磷酸基的单体；丙烯酰胺、丙烯腈等。这些可共聚的单体成分可使用1种或2种以上。这些可共聚的单体的使用量优选为总单体成分的40重量％以下。
进而，对于上述丙烯酸系聚合物而言，为了使其交联，还可根据需要含有多官能的单体等作为共聚用单体成分。作为这样的多官能的单体，例如可举出己二醇二(甲基)丙烯酸酯、(聚)乙二醇二(甲基)丙烯酸酯、(聚)丙二醇二(甲基)丙烯酸酯、新戊二醇二(甲基)丙烯酸酯、季戊四醇二(甲基)丙烯酸酯、三羟甲基丙烷三(甲基)丙烯酸酯、季戊四醇三(甲基)丙烯酸酯、二季戊四醇六(甲基)丙烯酸酯、环氧(甲基)丙烯酸酯、聚酯(甲基)丙烯酸酯、氨基甲酸酯(甲基)丙烯酸酯等。这些多官能的单体可使用1种或2种以上。多官能的单体的使用量从粘合特性等方面出发而优选为总单体成分的30重量％以下。
上述丙烯酸系聚合物可通过使单一单体或2种以上的单体混合物进行聚合而制得。聚合还可以利用溶液聚合、乳液聚合、本体聚合、悬浊聚合等中的某种方式进行。从防止对清洁的被粘附体的污染等方面出发，优选低分子量物的含量小的聚合物。从这方面出发，丙烯酸系聚合物的数均分子量优选为30万以上、进而优选为40万～300万左右。
另外，对于上述粘合剂而言，为了提高作为基底聚合物的丙烯酸系聚合物等的数均分子量，还可适当地采用外部交联剂。作为外部交联方法的具体的方法，可举出添加多异氰酸酯化合物、环氧化合物、氮丙啶化合物、密胺系交联剂等所谓的交联剂并使其反应的方法。在使用外部交联剂时，其使用量可根据与适于交联的基底聚合物的平衡、以及根据作为粘合剂的使用用途来适当地确定。一般而言，相对于上述基底聚合物100重量份，优选为5重量份左右以下、进而优选配合0.1～5重量份。进而，对于粘合剂而言，除了上述成分以外，还可根据需要使用以往公知的各种增粘剂、抗老化剂等添加剂。
粘合剂层1b可利用放射线固化型粘合剂形成。放射线固化型粘合剂可利用紫外线等放射线的照射而使交联度增大，从而使其粘合力容易地降低，容易地进行拾取。作为放射线，可举出X射线、紫外线、电子束、α射线、β射线、中子射线等。
放射线固化型粘合剂可不加限制地使用具有碳-碳双键等放射线固化性的官能团并且显示出粘合性的放射线固化型粘合剂。作为放射线固化型粘合剂，例如可例示出在上述丙烯酸系粘合剂、橡胶系粘合剂等一般的感压性粘合剂中配合了放射线固化性的单体成分、低聚物成分而得的添加型放射线固化性粘合剂。
作为所配合的放射线固化性的单体成分，例如可举出氨基甲酸酯低聚物、氨基甲酸酯(甲基)丙烯酸酯、三羟甲基丙烷三(甲基)丙烯酸酯、四羟甲基甲烷四(甲基)丙烯酸酯、季戊四醇三(甲基)丙烯酸酯、季戊四醇四(甲基)丙烯酸酯、二季戊四醇单羟基五(甲基)丙烯酸酯、二季戊四醇六(甲基)丙烯酸酯、1，4-丁二醇二(甲基)丙烯酸酯等。另外，放射线固化性的低聚物成分可举出氨基甲酸酯系、聚醚系、聚酯系、聚碳酸酯系、聚丁二烯系等各种低聚物，其重均分子量应为100～30000左右的范围。放射线固化性的单体成分、低聚物成分的配合量可根据上述粘合剂层的种类而确定为使粘合剂层的粘合力降低的量。一般而言，相对于构成粘合剂的丙烯酸系聚合物等基底聚合物100重量份，例如为5～500重量份、优选为40～150重量份左右。
另外，作为放射线固化型粘合剂，除了上述已说明的添加型放射线固化性粘合剂以外，还可举出将在聚合物侧链或主链中或者主链末端具有碳-碳双键的聚合物用作基底聚合物的内在型放射线固化性粘合剂。内在型放射线固化性粘合剂无需含有作为低分子成分的低聚物成分等，或者不大量地含有，因此，低聚物成分等不会在粘合剂在中经时地移动，就可形成稳定的层结构的粘合剂层，因而优选。
上述具有碳-碳双键的基底聚合物可不加限制地使用具有碳-碳双键且具有粘合性的聚合物。作为这样的基底聚合物，优选将丙烯酸系聚合物作为基本骨架。作为丙烯酸系聚合物的基本骨架，可举出上述已例示的丙烯酸系聚合物。
向上述丙烯酸系聚合物中导入碳-碳双键的导入法没有特别限制，可采用各种方法，碳-碳双键导入到聚合物侧链中在分子设计方面是容易的。例如可举出预先将丙烯酸系聚合物与具有官能团的单体共聚，然后使具有能够与该官能团反应的官能团和碳-碳双键的化合物在维持碳-碳双键的放射线固化性的状态下进行缩合或加成反应的方法。
作为上述官能团的组合的例子，可举出羧酸基和环氧基、羧酸基和氮丙啶基、羟基和异氰酸酯基等。这些官能团的组合中，从追随反应的容易性出发，优选为羟基与异氰酸酯基的组合。另外，根据这些官能团的组合，只要为生成上述具有碳-碳双键的丙烯酸系聚合物的组合，官能团就可处于丙烯酸系聚合物和上述化合物中的任一侧，但是对于上述优选的组合而言，优选为丙烯酸系聚合物具有羟基、上述化合物具有异氰酸酯基的情况。在这种情况下，作为具有碳-碳双键的异氰酸酯化合物，例如可举出甲基丙烯酰基异氰酸酯、2-甲基丙烯酰氧基乙基异氰酸酯、间-异丙烯基-α，α-二甲基苄基异氰酸酯等。另外，作为丙烯酸系聚合物，可使用将上述例示的含有羟基的单体、2-羟基乙基乙烯基醚、4-羟基丁基乙烯基醚、二乙二醇单乙烯基醚这样的醚系化合物等共聚而得的聚合物。
上述内在型放射线固化性粘合剂可单独使用上述具有碳-碳双键的基底聚合物(特别是丙烯酸系聚合物)，在不使特性变差的程度上还可配合上述放射线固化性的单体成分、低聚物成分。放射线固化性的低聚物成分等通常相对于基底聚合物100重量份在30重量份的范围内，优选为0～10重量份的范围。
在通过紫外线等使上述放射线固化型粘合剂固化的情况下，优选含有光聚合引发剂。作为光聚合引发剂，例如可举出4-(2-羟基乙氧基)苯基(2-羟基-2-丙基)酮、α-羟基-α，α′-二甲基苯乙酮、2-甲基-2-羟基苯丙酮、1-羟基环己基苯基酮等的α-乙酮醇系化合物；甲氧基苯乙酮、2，2-二甲氧基-2-苯基苯乙酮、2，2-二乙氧基苯乙酮、2-甲基-1-[4-(甲硫基)-苯基]-2-吗啉代丙烷-1等苯乙酮系化合物；苯偶姻乙醚、苯偶姻异丙醚、茴香偶姻甲基醚等苯偶姻醚系化合物；苄基二甲基酮缩醇等酮缩醇系化合物；2-萘磺酰氯等芳香族磺酰氯系化合物；1-苯基-1，2-丙二酮-2-(O-乙氧基羰基)肟等光活性肟系化合物；二苯甲酮、苯甲酰苯甲酸、3，3′-二甲基-4-甲氧基二苯甲酮等二苯甲酮系化合物；噻吨酮、2-氯噻吨酮、2-甲基噻吨酮、2，4-二甲基噻吨酮、异丙基噻吨酮、2，4-二氯噻吨酮、2，4-二乙基噻吨酮、2，4-二异丙基噻吨酮等噻吨酮系化合物；樟脑醌；卤化酮；酰基氧化膦；酰基膦酸酯等。光聚合引发剂的配合量相对于构成粘合剂的丙烯酸系聚合物等基底聚合物100重量份，例如为0.05～20重量份左右。
需说明的是，在放射线照射时发生因氧而导致的固化障碍的情况下，优选利用某些方法将氧(空气)阻挡于放射线固化型粘合剂层1b的表面外。例如可举出利用剥离物覆盖上述粘合剂层1b的表面的方法、在氮气气氛中进行紫外线等放射线的照射的方法等。
需说明的是，在不损害本发明的效果等的范围内，粘合剂层1b中可含有各种添加剂(例如着色剂、增稠剂、增量剂、填充剂、增粘剂、增塑剂、抗老化剂、抗氧化剂、表面活性剂、交联剂等)。
粘合剂层1b的厚度没有特别限定，从防止芯片剖面的破碎、底层填充材料2的固定保持的兼顾性等观点出发，优选为1～80μm左右。优选为2～50μm、进一步优选为5～35μm。
(底层填充材料)
本实施方式所述的底层填充材料2可用作将表面安装后的半导体元件与被粘附体之间的空间填充的密封用膜。作为底层填充材料的构成材料，可举出将热塑性树脂和热固化性树脂并用的材料。或者，也可单独使用热塑性树脂或热固化性树脂。
作为前述热塑性树脂，可举出天然橡胶、丁基橡胶、异戊二烯橡胶、氯丁二烯橡胶、乙烯-乙酸乙烯酯共聚物、乙烯-丙烯酸共聚物、乙烯-丙烯酸酯共聚物、聚丁二烯树脂、聚碳酸酯树脂、热塑性聚酰亚胺树脂、6-尼龙、6，6-尼龙等聚酰胺树脂、苯氧基树脂、丙烯酸树脂、PET或PBT等饱和聚酯树脂、聚酰胺酰亚胺树脂、或氟树脂等。这些热塑性树脂可单独使用或者并用2种以上。在这些热塑性树脂中，优选为离子性杂质少、耐热性高、可确保半导体元件的可靠性的丙烯酸树脂。
作为前述丙烯酸树脂，没有特别限定，可举出将具有碳数30以下、尤其是碳数4～18的直链或支链的烷基的丙烯酸或甲基丙烯酸的酯的1种或2种以上作为成分的聚合物等。作为前述烷基，例如可举出甲基、乙基、丙基、异丙基、正丁基、叔丁基、异丁基、戊基、异戊基、己基、庚基、环己基、2-乙基己基、辛基、异辛基、壬基、异壬基、癸基、异癸基、十一烷基、月桂基、十三烷基、十四烷基、硬脂酰基、十八烷基、或二十烷基等。
另外，作为形成前述聚合物的其他的单体，没有特别限定，例如可举出丙烯酸、甲基丙烯酸、羧乙基丙烯酸酯、羧戊基丙烯酸酯、衣康酸、马来酸、富马酸或巴豆酸等各种含有羧基的单体，马来酸酐或衣康酸酐等各种酸酐单体，(甲基)丙烯酸2-羟基乙酯、(甲基)丙烯酸2-羟基丙酯、(甲基)丙烯酸4-羟基丁酯、(甲基)丙烯酸6-羟基己酯、(甲基)丙烯酸8-羟基辛酯、(甲基)丙烯酸10-羟基癸酯、(甲基)丙烯酸12-羟基月桂酯或(4-羟基甲基环己基)-甲基丙烯酸酯等各种含有羟基的单体，苯乙烯磺酸、烯丙基磺酸、2-(甲基)丙烯酰胺-2-甲基丙烷磺酸、(甲基)丙烯酰胺丙烷磺酸、磺基丙基(甲基)丙烯酸酯或(甲基)丙烯酰氧基萘磺酸等各种含有磺酸基的单体，或者2-羟基乙基丙烯酰基磷酸酯等之类的含有磷酸基的单体，丙烯腈等这样的含有氰基的单体等。
作为前述热固化性树脂，可举出酚醛树脂、氨基树脂、不饱和聚酯树脂、环氧树脂、聚氨酯树脂、硅酮树脂、或热固化性聚酰亚胺树脂等。这些树脂可单独使用或者并用2种以上。尤其优选为含有使半导体元件腐蚀的离子性杂质等少的环氧树脂。另外，作为环氧树脂的固化剂，优选为酚醛树脂。
前述环氧树脂只要为通常可用作粘接剂组合物的环氧树脂，就没有特别限定，例如可使用双酚A型、双酚F型、双酚S型、溴化双酚A型、氢化双酚A型、双酚AF型、联苯型、萘型、芴型、苯酚酚醛清漆型、邻甲酚酚醛清漆型、三羟基苯基甲烷型、四羟苯基乙烷型等的二官能环氧树脂或多官能环氧树脂，或者乙内酰脲型、三缩水甘油基异氰脲酸酯型或缩水甘油胺型等的环氧树脂。它们可以单独使用或者并用2种以上。这些环氧树脂中，特别优选为酚醛清漆型环氧树脂、联苯型环氧树脂、三羟基苯基甲烷型树脂或四羟苯基乙烷型环氧树脂。这是由于这些环氧树脂富于与作为固化剂的酚醛树脂的反应性、且耐热性等优异的缘故。
进而，前述酚醛树脂是作为前述环氧树脂的固化剂来发挥作用的物质，例如可举出苯酚酚醛清漆树脂、苯酚芳烷基树脂、甲酚酚醛清漆树脂、叔丁基苯酚酚醛清漆树脂、壬基苯酚酚醛清漆树脂等酚醛清漆型酚醛树脂，甲酚型酚醛树脂，聚对羟基苯乙烯等聚羟基苯乙烯等。它们可以单独使用，或者可以并用2种以上。这些酚醛树脂中，优选为苯酚酚醛清漆树脂、苯酚芳烷基树脂。这是由于能够提高半导体装置的连接可靠性的缘故。
就前述环氧树脂与酚醛树脂的配合比例而言，例如优选按照相对于前述环氧树脂成分中的环氧基1当量，酚醛树脂中的羟基达到0.5～2.0当量的方式加以配合。更优选为0.8～1.2当量。即，这是因为若两者的配合比例逸出前述范围，则无法进行充分的固化反应，环氧树脂固化物的特性也容易变差的缘故。
需说明的是，在本发明中，特别优选为使用了环氧树脂、酚醛树脂和丙烯酸树脂的底层填充材料。这些树脂因为离子性杂质少且耐热性高，所以能够确保半导体元件的可靠性。对于这种情况下的配合比来说，相对于丙烯酸树脂成分100重量份而言，环氧树脂与酚醛树脂的混合量为10～200重量份。
作为环氧树脂与酚醛树脂的热固化促进催化剂，没有特别限制，可从公知的热固化促进催化剂中适当地选择使用。热固化促进催化剂可单独使用、或组合2种以上使用。作为热固化促进催化剂，例如可使用胺系固化促进剂、磷系固化促进剂、咪唑系固化促进剂、硼系固化促进剂、磷-硼系固化促进剂等。
为了将焊料凸点的表面的氧化膜除去而使半导体元件的安装变得容易，可以在底层填充材料2中添加焊剂。作为焊剂，没有特别限定，可使用以往公知的具有焊剂作用的化合物，例如可举出双酚酸、己二酸、乙酰基水杨酸、苯甲酸、二苯乙醇酸、壬二酸、苯甲酸苄酯、丙二酸、2，2-双(羟基甲基)丙酸、水杨酸、邻甲氧基苯甲酸、间羟基苯甲酸、琥珀酸、2，6-二甲氧基甲基对甲酚、苯甲酸酰肼、碳酰肼、丙二酸二酰肼、琥珀酸二酰肼、戊二酸二酰肼、水杨酸酰肼、亚氨基二乙酸二酰肼、衣康酸二酰肼、柠檬酸三酰肼、硫代碳酰肼、二苯甲酮腙、4，4’-羟基双苯磺酰酰肼和己二酸二酰肼等。焊剂的添加量为可发挥上述焊剂作用的程度即可，通常，相对于底层填充材料所含的树脂成分100重量份，为0.1～20重量份左右。
在本实施方式中，底层填充材料2根据需要可以着色。对于底层填充材料2而言，作为通过着色而呈现出的颜色，没有特别限制，例如优选为黑色、蓝色、红色、绿色等。着色时，可从颜料、染料等公知的着色剂中适当地选择使用。
在预先使本实施方式的底层填充材料2交联至预定的程度的情况下，在制作时，可以预先添加与聚合物的分子链末端的官能团等反应的多官能的化合物作为交联剂。由此，可使高温下的粘接特性提高，实现耐热性的改善。
作为前述交联剂，尤其更优选为甲苯二异氰酸酯、二苯基甲烷二异氰酸酯、对苯二异氰酸酯、1，5-萘二异氰酸酯、多元醇与二异氰酸酯的加成物等多异氰酸酯化合物。作为交联剂的添加量，相对于前述的聚合物100重量份，通常优选设为0.05～7重量份。若交联剂的量多于7重量份，则粘接力降低，因而不优选。其另一方面，若少于0.05重量份，则凝聚力不足，因而不优选。另外，与这样的多异氰酸酯化合物一起，根据需要还可同时含有环氧树脂等其他的多官能的化合物。
另外，可以在底层填充材料2中适当地配合无机填充剂。无机填充剂的配合能够赋予导电性、提高热传导性、调节贮藏弹性模量等。
作为前述无机填充剂，例如可举出含有二氧化硅、粘土、石膏、碳酸钙、硫酸钡、氧化铝、氧化铍、碳化硅、氮化硅等陶瓷类，铝、铜、银、金、镍、铬、铅、锡、锌、钯、焊料等金属，或合金类，其他的碳等各种无机粉末。它们可以单独使用，或者并用2种以上。其中，优选使用二氧化硅、特别是熔融二氧化硅。
无机填充剂的平均粒径没有特别限定，但是优选为0.005～10μm的范围内、更优选为0.01～5μm的范围内、进一步优选为0.1～2.0μm。若无机填充剂的平均粒径不足0.005μm，则成为底层填充材料的挠性降低的原因。另一方面，若前述平均粒径超过10μm，则相对于底层填充材料所密封的缝隙而言，粒径大，成为密封性降低的主要原因。需说明的是，在本发明中，可以使平均粒径相互不同的无机填充剂彼此组合来使用。另外，平均粒径是利用激光衍射式的粒度分布仪(HORIBA制、装置名；LA-910)所求得的值。
前述无机填充剂的配合量相对于有机树脂成分100重量份而言优选为10～400重量份、更优选为50～250重量份。若无机填充剂的配合量不足10重量份，则贮藏弹性模量降低，存在组件的应力可靠性被严重损害的情况。另一方面，若超过400重量份，则存在如下情况：底层填充材料2的流动性降低，没有充分地埋入到基板、半导体元件的凹凸中，而成为空隙、裂缝的原因。
需说明的是，在底层填充材料2中除了前述无机填充剂以外，还可根据需要适当地配合其他的添加剂。作为其他的添加剂，例如可举出阻燃剂、硅烷偶联剂或离子捕获剂等。作为前述阻燃剂，例如可举出三氧化锑、五氧化锑、溴化环氧树脂等。它们可以单独使用，或者并用2种以上使用。作为前述硅烷偶联剂，例如可举出β-(3，4-环氧基环己基)乙基三甲氧基硅烷、γ-环氧丙氧丙基三甲氧基硅烷、γ-环氧丙氧丙基甲基二乙氧基硅烷等。这些化合物可以单独使用或者并用2种以上。作为前述离子捕获剂，例如可举出水滑石类、氢氧化铋等。它们可以单独使用或者并用2种以上。
在本实施方式中，热固化前的上述底层填充材料在上述热压接温度下的熔融粘度优选为20000Pa·s以下、更优选为100Pa·s以上10000Pa·s以下。通过将热压接温度下的熔融粘度设为上述范围，从而可使连接构件4(参照图2A)容易地进入到底层填充材料2中。另外，能够防止半导体元件5的电连接时的空隙的产生、和来自半导体元件5与被粘附体6之间的空间的底层填充材料2的渗出(参照图2E)。
另外，热固化前的上述底层填充材料2在23℃下的粘度优选为0.01MPa·s以上100MPa·s以下、更优选为0.1MPa·s以上10MPa·s以下。通过使热固化前的底层填充材料具有上述范围的粘度，从而能够提高背面研磨、切割时的半导体晶片3(参照图2C)的保持性、作业的操作性。需说明的是，粘度的测定可按照熔融粘度的测定法进行。
进而，热固化前的上述底层填充材料2的温度23℃、湿度70％的条件下的吸水率优选为1重量％以下、更优选为0.5重量％以下。通过使底层填充材料2具有上述这样的吸水率，从而可更有效地抑制在底层填充材料2中的水分的吸收、半导体元件5在安装时的空隙的产生。需说明的是，上述吸水率的下限优选越小越好、优选基本上为0重量％，更优选为0重量％。
底层填充材料2的厚度(多层时为总厚度)没有特别限定，但若考虑到底层填充材料2的强度、半导体元件5与被粘附体6之间的空间的填充性，则可以为10μm以上100μm以下左右。需说明的是，底层填充材料2的厚度可考虑半导体元件5与被粘附体6之间的缝隙、连接构件的高度而适当地设定。
密封片10的底层填充材料2优选被剥离物保护(未图示)。剥离物具有一直到供于实用为止而作为保护底层填充材料2的保护材料的功能。剥离物在将半导体晶片3贴合在密封片的底层填充材料2上时被剥离。作为剥离物，还可使用聚对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯，利用氟系剥离剂、长链烷基丙烯酸酯系剥离剂等剥离剂进行了表面涂布的塑料膜或纸等。
(密封片的制造方法)
本实施方式所述的密封片10例如可通过分别预先制作背面研磨用带1和底层填充材料2，最后将它们贴合而制成。具体而言，可按照以下这样的步骤进行制作。
首先，基材1a可以利用以往公知的制膜方法进行制膜。作为该制膜方法，例如可例示出压延制膜法、有机溶剂中的流延法、密闭体系中的吹胀挤出法、T模挤出法、共挤出法、干式层压法等。
然后，制备粘合剂层形成用的粘合剂组合物。在粘合剂组合物中配合了在粘合剂层一项中所说明的树脂、添加物等。将制备所得的粘合剂组合物涂布在基材1a上而形成涂布膜后，在规定条件下使该涂布膜干燥(根据需要使其加热交联)，形成粘合剂层1b。作为涂布方法，没有特别限定，例如可举出辊涂装、丝网涂装、凹版涂装等。另外，作为干燥条件，例如可在干燥温度80～150℃、干燥时间0.5～5分钟的范围内进行。另外，可以将粘合剂组合物涂布在剥离物上形成涂布膜后，在上述干燥条件下使涂布膜干燥，形成粘合剂层1b。然后，将粘合剂层1b与剥离物一起贴合于基材1a上。由此，可制作具备基材1a和粘合剂层1b的背面研磨用带1。
底层填充材料2例如可如下所述地加以制作。首先，制备作为底层填充材料2的形成材料的粘接剂组合物。在该粘接剂组合物中，如底层填充材料一项中所述，配合了热塑性成分、环氧树脂、各种添加剂等。
接下来，在基材剥离物上按照达到规定的厚度的方式涂布制备好的粘接剂组合物而形成涂布膜，然后在规定条件下使该涂布膜干燥，形成底层填充材料。作为涂布方法，没有特别限定，例如可举出辊涂装、丝网涂装、凹版涂装等。另外，作为干燥条件，例如可在干燥温度70～160℃、干燥时间1～5分钟的范围内进行。另外，可在剥离物上涂布粘接剂组合物而形成涂布膜，然后在上述干燥条件下使涂布膜干燥，形成底层填充材料。然后，将底层填充材料与剥离物一起贴合于基材剥离物上。
接着，从背面研磨用带1和底层填充材料2中分别将剥离物剥离，按照形成贴合面的方式将底层填充材料与粘合剂层两者贴合。贴合例如可通过压接进行。此时，层压温度没有特别限定，例如优选为30～100℃、更优选为40～80℃。另外，线压力没有特别限定，例如优选为0.98～196N/cm、更优选为9.8～98N/cm。然后，将底层填充材料上的基材剥离物剥离，得到本实施方式所述的密封片。
[热压接工序]
在热压接工序中，在1000Pa以下的减压气氛、0.2MPa以上的按压、和40℃以上的热压接温度的条件下使半导体晶片3的形成有连接构件4的电路面3a与上述密封片的底层填充材料2进行热压接(参照图2A)。
(半导体晶片)
在半导体晶片3的电路面3a上形成有多个连接构件4(参照图2A)。作为凸点、导电材料等连接构件的材质，没有特别限定，例如可举出锡-铅系金属材、锡-银系金属材、锡-银-铜系金属材、锡-锌系金属材、锡-锌-铋系金属材等焊料类(合金)，金系金属材、铜系金属材等。连接构件的高度也可根据用途而定，一般而言为15～100μm左右。当然，半导体晶片3中的各个连接构件的高度可以相同或不同。
本实施方式所述的半导体装置的制造方法中，上述底层填充材料的厚度T(μm)相对于上述连接构件的高度H(μm)之比(T/H)优选为0.5～2、更优选为0.8～1.5。通过使上述底层填充材料的厚度T(μm)与上述连接构件的高度H(μm)满足上述关系，从而能够将半导体元件与被粘附体之间的空间充分地填充，并且能够防止来自该空间的底层填充材料的过剩的渗出，能够防止因底层填充材料而导致的半导体元件的污染等。需说明的是，各连接构件的高度不同时，将最高的连接构件的高度作为基准。
(贴合)
如图2A所示，首先，将任意地设置在密封片10的底层填充材料2上的剥离物适当地剥离，使前述半导体晶片3的形成有连接构件4的电路面3a与底层填充材料2相对，通过热压接使前述底层填充材料2与前述半导体晶片3贴合。
在本实施方式中，通过热压接进行半导体晶片与底层填充材料的贴合。热压接通常可利用压接辊等公知的按压装置进行。作为减压条件，为10000Pa以下即可，优选为5000Pa以下、更优选为1000Pa以下。需说明的是，减压条件的下限没有特别限定，但从生产率的方面出发，为10Pa以上即可。作为按压条件，为0.2MPa以上即可、优选为0.2MPa以上1MPa以下、更优选为0.4Pa以上0.8Pa以下。另外，作为热压接温度的条件，为40℃以上即可、优选为40℃以上120℃以下、更优选为60℃以上100℃以下。通过在规定的热压接条件下进行贴合，从而能够使底层填充材料充分地追随半导体晶片表面的凹凸，能够大幅地减少半导体晶片与底层填充材料的界面中的气泡而提高密合性。由此能够抑制上述界面中的空隙的产生，其结果：能够效率良好地制造半导体晶片与被粘附体的连接可靠性优异的半导体装置。
[研磨工序]
在本实施方式中，将背面研磨用带用作了支承材，因而紧接着热压接工序之后而设置研磨工序。在研磨工序中，对上述半导体晶片3的与电路面3a相反一侧的面(即背面)3b进行研磨(参照图2B)。作为用于半导体晶片3的背面研磨的薄型加工机，没有特别限定，例如可例示出研磨机(晶圆磨背机(back grinder))、研磨垫等。另外，也可以利用蚀刻等化学方法进行背面研磨。背面研磨进行至半导体晶片达到所需的厚度(例如700～25μm)为止。
[切割工序]
在切割工序中，如图2C所示，将半导体晶片3切割而形成带有底层填充材料的半导体元件5。通过经过切割工序，从而将半导体晶片3切断为规定尺寸，形成单片(小片化)，制造半导体芯片(半导体元件)5。使在此得到的半导体芯片5与被切断为相同形状的底层填充材料2成为一体。切割是按照常规方法从半导体晶片3的与贴合有底层填充材料2的电路面3a相反一侧的面3b开始进行的。切断位置的位置调准可以利用使用了直射光或间接光或者红外线(IR)的图像识别来进行。
在本工序中，例如可采用进行切入至密封片为止的被称作全断的切断方式等。作为在本工序中所使用的切割装置，没有特别限定，可使用以往公知的装置。另外，由于半导体晶片可利用具有底层填充材料的密封片、以优异的密合性被粘接固定，因而能够抑制芯片破碎、碎片飞散，还能够抑制半导体晶片的破损。需说明的是，若底层填充材料由含有环氧树脂的树脂组合物形成，则即使通过切割被切断，在其剖面中也能够抑制或防止底层填充材料产生底层填充材料的糊渗出的情况。其结果，能够抑制或防止剖面彼此再附着(粘连)，能够更良好地进行后述的拾取。
需说明的是，在接着切割工序而进行密封片的扩展的情况下，该扩展可利用以往公知的扩展装置进行。扩展装置具有可经由切割环将密封片向下方压入的环形状的外环、和比外环的直径小且支承密封片的内环。通过上述扩展工序，能够在后述的拾取工序中防止挨着的半导体芯片彼此接触而发生破损。
[拾取工序]
为了回收被粘接固定于密封片的半导体芯片5，如图2D所示，进行带有底层填充材料2的半导体芯片5的拾取，从背面研磨用带1将半导体芯片5与底层填充材料3的层叠体A剥离。
作为拾取的方法，没有特别限定，可采用以往公知的各种方法。例如，可举出从密封片的基材侧用针将各个半导体芯片顶出，利用拾取装置将被顶出的半导体芯片拾取的方法等。需说明的是，被拾取的半导体芯片5与贴合于电路面3a的底层填充材料2成为一体而构成层叠体A。
在此，在粘合剂层1b为紫外线固化型的情况下，拾取是对该粘合剂层1b照射紫外线后进行的。由此，粘合剂层1b对底层填充材料2的粘合力降低，使半导体芯片5的剥离变得容易。其结果，不使半导体芯片5发生损伤，就能够拾取。紫外线照射时的照射强度、照射时间等条件没有特别限定，可适当地根据需要而进行设定。另外，作为用于紫外线照射的光源，例如可使用低压汞灯、低压高功率灯、中压汞灯、无电极汞灯、氙闪光灯、准分子灯、紫外LED等。
[安装工序]
在安装工序中，利用底层填充材料2将被粘附体6与半导体元件5之间的空间填充，并且经由连接构件4将半导体元件5与被粘附体6电连接(参照图2E)。具体而言，按照常规方法，以半导体芯片5的电路面3a与被粘附体6相对的形态，将层叠体A的半导体芯片5固定于被粘附体6。例如，通过使形成于半导体芯片5的凸点(连接构件)4与粘附于被粘附体6的连接垫的接合用的导电材料7(焊料等)接触而进行按压，同时使导电材料熔融，从而可确保半导体芯片5与被粘附体6的电连接，将半导体芯片5固定于被粘附体6。由于底层填充材料2被贴附于半导体芯片5的电路面3a，所以在半导体芯片5与被粘附体6的电连接的同时，利用底层填充材料2将半导体芯片5与被粘附体6之间的空间填充。
一般而言，作为安装工序中的加热条件，为100～300℃，作为加压条件，为0.5～500N。另外，可以以多个阶段进行安装工序中的加热加压处理。例如，可采用在150℃、100N下处理10秒后，在300℃、100～200N下处理10秒这样的步骤。通过在多个阶段中进行加热加压处理，从而能够效率良好地将连接构件与垫间的树脂除去，得到更良好的金属间接合。
作为被粘附体6，可使用引线框、电路基板(配线电路基板等)等各种基板、其他的半导体元件。作为基板的材质，没有特别限定，可举出陶瓷基板、塑料基板。作为塑料基板，例如可举出环氧基板、双马来酰亚胺三嗪基板、聚酰亚胺基板、玻璃环氧基板等。
需说明的是，在安装工序中，使连接构件和导电材料中的一方或两方熔融，使半导体芯片5的连接构件形成面3a的凸点4与被粘附体6的表面的导电材料7连接，作为该凸点4和导电材料7的熔融时的温度，通常为260℃左右(例如250℃～300℃)。就本实施方式所述的密封片而言，通过利用环氧树脂等形成底层填充材料2，从而能够具有还耐受该安装工序中的高温的耐热性。
[底层填充材料固化工序]
在进行了半导体元件5与被粘附体6的电连接后，通过加热使底层填充材料2固化。由此，能够保护半导体元件5的表面，并且能够确保半导体元件5与被粘附体6之间的连接可靠性。作为用于底层填充材料的固化的加热温度，没有特别限定，为150～250℃左右即可。需说明的是，通过安装工序中的加热处理，在底层填充材料进行固化的情况下，可省略本工序。
[密封工序]
然后，为了保护具备安装有半导体芯片5的半导体装置20整体，可进行密封工序。密封工序可利用密封树脂进行。作为此时的密封条件，没有特别限定，通常通过在175℃下进行60秒～90秒的加热，从而进行密封树脂的热固化，但本发明并不限定于此，例如可在165℃～185℃下处理数分钟。
作为前述密封树脂，只要为具有绝缘性的树脂(绝缘树脂)，就没有特别限定，可从公知的密封树脂等密封材料中适当地选择使用，更优选为具有弹性的绝缘树脂。作为密封树脂，例如可举出含有环氧树脂的树脂组合物等。作为环氧树脂，可举出前述所例示的环氧树脂等。另外，作为基于含有环氧树脂的树脂组合物的密封树脂而言，作为树脂成分，除了环氧树脂以外，还可含有环氧树脂以外的热固化性树脂(酚醛树脂等)、热塑性树脂等。需说明的是，作为酚醛树脂，还可作为环氧树脂的固化剂来利用，作为这样的酚醛树脂，可举出前述所例示的酚醛树脂等。
[半导体装置]
接着，对于使用该密封片而得的半导体装置，参照附图来进行说明(参照图2E)。在本实施方式所述的半导体装置20中，半导体元件5与被粘附体6经由形成于半导体元件5上的凸点(连接构件)4和设置于被粘附体6上的导电材料7被电连接。另外，按照将在半导体元件5与被粘附体6之间的空间填充的方式来配置底层填充材料2。半导体装置20通过使用密封片10的上述制造方法而制得，因此在半导体元件5与底层填充材料2之间可抑制空隙的产生。因而，半导体元件5表面保护、和半导体元件5与被粘附体6之间的空间的填充可达到充分的水平，作为半导体装置20，可发挥高可靠性。
<第2实施方式>
在本实施方式中，代替第1实施方式中的热压接工序，而采用在1000Pa以下的减压下使半导体晶片3的形成有连接构件4的电路面3a与上述密封片10的底层填充材料2贴合的贴合工序(参照图2A)。除该点以外，通过经由与第1实施方式相同的工序而能够制造规定的半导体装置，但对于其他的优选的方式也进行说明。
贴合的方法没有特别限定，优选为利用压接的方法。压接通常利用压接辊等公知的按压装置，在载荷优选0.1～1MPa、更优选0.2～0.7MPa的压力而进行按压的同时来进行压接。此时，可以在加热至40～100℃左右的同时进行压接。
在本实施方式中，在1000Pa以下的减压下进行半导体晶片与底层填充材料的贴合。减压条件的上限优选为500Pa以下、更优选为300Pa以下。需说明的是，减压条件的下限没有特别限定，但从生产率的方面出发为10Pa以上即可。通过在规定的减压条件下进行贴合，从而能够大幅地将少在半导体晶片与底层填充材料的界面中的气泡而提高密合性，由此能够抑制上述界面中的空隙的产生。其结果，能够效率良好地制造半导体晶片与被粘附体的连接可靠性优异的半导体装置。
在本实施方式所述的半导体装置的制造方法中，作为底层填充材料的厚度，优选形成于半导体晶片表面的连接构件的高度X(μm)与前述底层填充材料的厚度Y(μm)满足下述的关系。
0.5≤Y/X≤2
通过使前述连接构件的高度X(μm)与前述固化膜的厚度Y(μm)满足上述关系，从而能够充分地将半导体元件与被粘附体之间的空间填充，并且能够防止来自该空间的底层填充材料的过剩的渗出，能够防止由底层填充材料造成的半导体元件的污染等。需说明的是，各连接构件的高度不同的情况下，以最高的连接构件的高度为基准。
在本实施方式中，热固化前的上述底层填充材料2的100～200℃下的最低熔融粘度优选为100Pa·s以上20000Pa·s以下、更优选为1000Pa·s以上10000Pa·s以下。通过将最低熔融粘度设为上述范围，从而能够使连接构件4(参照图2A)向底层填充材料2中的进入变得容易。另外，能够防止半导体元件5的电连接时的空隙的产生、和来自半导体元件5与被粘附体6之间的空间的底层填充材料2的渗出(参照图2E)。
<第3实施方式>
在第1实施方式中将背面研磨用带用作支承材，但在本实施方式中，将基材与在该基材上层叠有粘合剂层的切割带用作支承材。在这种情况下，使用目标厚度的半导体晶片而省略研磨工序，除此以外，通过经过与第1实施方式和第2实施方式相同的工序，从而能够制造规定的半导体装置(即除去图2A而至图2B～2E的工序)。
<第4实施方式>
在第1实施方式中将背面研磨用带用作支承材，但在本实施方式中，没有设置粘合剂层而是单独使用基材作为支承材。因而，作为本实施方式的密封片，形成为在基材上层叠有底层填充材料的状态。在本实施方式中可任意地进行研磨工序，但是拾取工序前的紫外线照射由于粘合剂层的省略而没有进行。除了这些方面，通过经过与第1实施方式和第2实施方式相同的工序，从而能够制造规定的半导体装置。
[实施例]
以下，例示出该发明的优选的实施例来详细地进行说明。但是，在该实施例中所记载的材料、配合量等只要没有特别限定，该发明的范围就不仅限于此。另外，份是指重量份。
<第1实施方式所述的实施例>
[实施例1]
(密封片的制作)
相对于以丙烯酸乙酯-甲基丙烯酸甲酯为主成分的丙烯酸酯系聚合物(商品名“Paracron W-197CM”根上工业株式会社制)：100份，加入将环氧树脂1(商品名“Epikote 1004”JER株式会社制)：56份、环氧树脂2(商品名“Epikote 828”JER株式会社制)：19份、酚醛树脂(商品名“Mirex XLC-4L”三井化学株式会社制)：75份、球状二氧化硅(商品名“SO-25R”株式会社Admatechs制)：167份、有机酸(商品名“Ortho-anisic acid”东京化成株式会社制)：1.3份、咪唑催化剂(商品名“2PHZ-PW”四国化成株式会社制)：1.3份溶解在甲基乙基酮中制备的溶液，制备了固体成分浓度达到23.6重量％的粘接剂组合物的溶液。
将该粘接剂组合物的溶液涂布在作为剥离衬(剥离物)而经硅酮脱模处理的厚度为50μm的由聚对苯二甲酸乙二醇酯膜构成的脱模处理膜上，然后在130℃下使其干燥2分钟，从而制作了厚45μm的底层填充材料。
使用手推辊将上述底层填充材料贴合在晶圆磨背带(back grind tape)(商品名“UB-2154”、日东电工株式会社制)的粘合剂层上，制作密封片。
(半导体装置的制作)
准备在单面形成有凸点的单面带有凸点的硅晶片，将所制作的密封片以底层填充材料为贴合面而使其热压接于在该单面带有凸点的硅晶片的形成有凸点一侧的面。作为单面带有凸点的硅晶片，使用以下的硅晶片。另外，热压接条件如下所述。底层填充材料的厚度Y(＝45μm)与连接构件的高度X(＝45μm)之比(Y/X)为1。
<单面带有凸点的硅晶片>
硅晶片的直径：8英寸
硅晶片的厚度：0.7mm(700μm)
凸点的高度：45μm
凸点的间距：50μm
凸点的材质：SnAg焊料+铜柱
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：0.5MPa
贴附时的台面温度(热压接温度)：80℃
贴附时的减压度：150Pa
按照上述步骤，将单面带有凸点的硅晶片与密封片贴合后，在下述条件下对硅晶片的背面进行研磨。
<研磨条件>
研磨装置：商品名“DFG-8560”、Disco公司制
半导体晶片：从厚度0.7mm(700μm)背面研磨至0.2mm(200μm)
接下来，在下述条件下对半导体晶片进行切割。切割按照达到7.3mm见方的芯片尺寸的方式加以全断切割。
<切割条件>
切割装置：商品名“DFD-6361”Disco公司制
切割环：“2-8-1”(Disco公司制)
切割速度：30mm/秒
切割刀片：
Z1；Disco公司制“203O-SE 27HCDD”
Z2；Disco公司制“203O-SE 27HCBB”
切割刀片转速：
Z1；40000rpm
Z2；40000rpm
切割方式：阶梯式切割
晶片芯片尺寸：7.3mm见方
然后，从各密封片的基材侧，以利用针的顶出方式，将底层填充材料与单面带有凸点的半导体芯片的层叠体拾取。拾取条件如下所述。
<拾取条件>
拾取装置：商品名“SPA-300”株式会社新川社制
针根数：9根
针顶出量：500μm(0.5mm)
针顶出速度：20mm/秒
拾取时间：1秒
扩展量：3mm
最后，如下述的安装条件，在使半导体芯片的凸点形成面与BGA(BallGrid Array)基板相对的状态下，进行半导体芯片向BGA基板的安装。由此，得到将半导体芯片安装于BGA基板而得的半导体装置。需说明的是，在本工序中，进行了紧接着安装条件1之后实施安装条件2的2阶段式的处理。
<安装条件1>
拾取装置：商品名“FCB-3”松下制
加热温度：150℃
荷重：98N
保持时间：10秒
<安装条件2>
拾取装置：商品名“FCB-3”松下制
加热温度：260℃
荷重：98N
保持时间：10秒
[实施例2]
在下述的热压接条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：0.5MPa
贴附时的台面温度(热压接温度)：80℃
贴附时的减压度：1000Pa
[实施例3]
在下述的热压接条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：0.5MPa
贴附时的台面温度(热压接温度)：80℃
贴附时的减压度：10000Pa
[实施例4]
在下述的热压接条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：0.2MPa
贴附时的台面温度(热压接温度)：80℃
贴附时的减压度：150Pa
[实施例5]
在下述的热压接条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：1.0MPa
贴附时的台面温度(热压接温度)：80℃
贴附时的减压度：150Pa
[实施例6]
在下述的热压接条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：0.5MPa
贴附时的台面温度(热压接温度)：40℃
贴附时的减压度：150Pa
[实施例7]
在下述的热压接条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：0.5MPa
贴附时的台面温度(热压接温度)：120℃
贴附时的减压度：150Pa
[实施例8]
不将晶圆磨背带贴合于底层填充材料，而将脱模膜与底层填充材料的层叠体用作密封片，除此以外，与实施例1相同地制作了半导体装置。
[比较例1]
在下述的热压接条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：0.5MPa
贴附时的台面温度(热压接温度)：80℃
贴附时的减压度：20000Pa
[比较例2]
在下述的热压接条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：0.05MPa
贴附时的台面温度(热压接温度)：80℃
贴附时的减压度：150Pa
[比较例3]
在下述的热压接条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<热压接条件>
贴附装置：商品名“DSA840-WS”、日东精机株式会社制
贴附速度：5mm/min
贴附压力(按压)：0.5MPa
贴附时的台面温度(热压接温度)：25℃
贴附时的减压度：150Pa
(熔融粘度的测定)
测定实施例和比较例的底层填充材料(热固化前)在热压接时的熔融粘度。熔融粘度的测定是使用流变仪(HAAKE公司制、RS-1)，利用平行板法所测定的值。更详细而言，在缝隙100μm、旋转锥直径20mm、旋转速度10s-1、升温速度10℃/分钟的条件下，在从20℃开始至200℃的范围内测定熔融粘度，读取此时所得的各热压接温度下的熔融粘度。结果示于表1。
(空隙的产生的评价)
空隙的产生的评价是通过在实施例和比较例中所制作的半导体装置的半导体芯片与底层填充材料之间切断，利用图像识别装置(HamamatsuPhotonics公司制、商品名“C9597-11”)观察剖面，算出空隙部分的总面积相对于底层填充材料的面积的比例而进行的。相对于剖面的观察图像中的底层填充材料的面积，将空隙部分的总面积为0～5％的情况设为“○”、将超过5％且25％以下的情况设为“△”、将超过25％的情况设为“×”。将结果示于表1。
由表1可知，在实施例所述的半导体装置中，抑制了空隙的产生。另一方面，在比较例的半导体装置中产生了空隙。从在比较例1中减压条件超过10000Pa且减压度弱、在比较例2中按压条件低于0.2MPa且弱、在比较例3中热压接温度低于40℃的观点出发，可认为半导体晶片与底层填充材料之间的气泡没有充分减少，最终产生了空隙。根据以上情况可知：作为半导体装置的制造工序，通过在10000Pa以下的减压气氛、0.2MPa以上的按压和40℃以上的热压接温度的条件下将半导体晶片与底层填充材料热压接，从而能够制造抑制了空隙的产生的高可靠性的半导体装置。
<第2实施方式所述的实施例>
[实施例1]
与第1实施方式的实施例1相同地制造密封片和半导体装置。
[实施例2]
在下述的贴合条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<贴合条件>
贴附装置：商品名“DSA840-WS”日东精机株式会社制
贴附速度：5mm/min
贴附压力：0.25MPa
贴附时的台面温度：80℃
贴附时的减压度：1000Pa
[实施例3]
在下述的贴合条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<贴合条件>
贴附装置：商品名“DSA840-WS”日东精机株式会社制
贴附速度：5mm/min
贴附压力：0.25MPa
贴附时的台面温度：80℃
贴附时的减压度：100Pa
[比较例1]
在下述的贴合条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作半导体装置。
<贴合条件>
贴附装置：商品名“DSA840-WS”日东精机株式会社制
贴附速度：5mm/min
贴附压力：0.25MPa
贴附时的台面温度：80℃
贴附时的减压度：1100Pa
[比较例2]
在半导体晶片与底层填充材料的贴合时没有减压，(即在大气压下贴合)，除此以外，与实施例1相同地制作了半导体装置。
(最低熔融粘度的测定)
测定底层填充材料(热固化前)的最低熔融粘度。最低熔融粘度的测定是使用流变仪(HAAKE公司制、RS-1)，利用平行板法测得的值。更详细而言，在缝隙100μm、旋转锥直径20mm、旋转速度10s-1、升温速度10℃/分钟的条件下，从60℃开始至200℃的范围下测定熔融粘度，将此时得到的从100℃至200℃的范围内的熔融粘度的最低值设为最低熔融粘度。将结果示于表2。
(空隙的产生的评价)
空隙的产生的评价是通过在实施例和比较例中所制作的半导体装置的半导体芯片与底层填充材料之间切断，利用图像识别装置(HamamatsuPhotonics公司制、商品名“C9597-11”)观察剖面，算出空隙部分的总面积相对于底层填充材料的面积的比例而进行的。相对于剖面的观察图像中的底层填充材料的面积，将空隙部分的总面积为0～5％的情况设为“○”、将超过5％且25％以下的情况评价为“△”、将超过25％的情况评价为“×”。将结果示于表2中。
[表2]
Figure BDA00002570898200351
由表2可知：在实施例所述的半导体装置中，空隙的产生得到了抑制。另一方面，在比较例1～2的半导体装置中产生了空隙。从在比较例1中减压条件超过了1000Pa，另外在比较例2中没有进行减压处理的观点出发，可认为半导体晶片与底层填充材料之间的气泡没有被充分地减少，最终产生了空隙。根据以上情况可知：作为半导体装置的制造工序，通过在1000Pa以下的减压下进行半导体晶片与底层填充材料的贴合，从而能够制造空隙的产生被抑制了的高可靠性的半导体装置。
<第3实施方式所述的实施例>
[实施例1]
利用手推辊将在上述第1实施方式的实施例1中所制作的底层填充材料贴合于切割带(商品名“V-8-T”、日东电工株式会社制)的粘合剂层上，制作了密封片。
(半导体装置的制作)
准备单面形成有凸点的单面带有凸点的硅晶片，将所制作的密封片以底层填充材料为贴合面而使其贴合于在该单面带有凸点的硅晶片的形成有凸点一侧的面。作为单面带有凸点的硅晶片，可使用以下的硅晶片。另外，贴合条件如下所述。底层填充材料的厚度Y(＝45μm)与连接构件的高度X(＝45μm)之(Y/X)为1。
<单面带有凸点的硅晶片>
硅晶片的直径：8英寸
硅晶片的厚度：0.2mm(200μm)
凸点的高度：45μm
凸点的间距：50μm
凸点的材质：焊料+铜柱
<贴合条件>
贴附装置：商品名“DSA840-WS”日东精机株式会社制
贴附速度：5mm/min
贴附压力：0.25MPa
贴附时的台面温度：80℃
贴附时的减压度：150Pa
然后，按照上述步骤将单面带有凸点的硅晶片与密封片贴合后，在下述条件下对半导体晶片进行切割。切割按照形成7.3mm见方的芯片尺寸的方式进行切割。
<切割条件>
切割装置：商品名“DFD-6361”Disco公司制
切割环：“2-8-1”(Disco公司制)
切割速度：30mm/秒
切割刀片：
Z1；Disco公司制“203O-SE 27HCDD”
Z2；Disco公司制“203O-SE 27HCBB”
切割刀片转速：
Z1；40000rpm
Z2；45000rpm
切割方式：阶梯式切割
晶片芯片尺寸：7.3mm见方
之后，在与第1实施方式的实施例1相同的条件下进行拾取和半导体芯片的热压接，得到半导体装置。
[实施例2]
在下述的贴合条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<贴合条件>
贴附装置：商品名“DSA840-WS”日东精机株式会社制
贴附速度：5mm/min
贴附压力：0.25MPa
贴附时的台面温度：80℃
贴附时的减压度：1000Pa
[实施例3]
在下述的贴合条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<贴合条件>
贴附装置：商品名“DSA840-WS”日东精机株式会社制
贴附速度：5mm/min
贴附压力：0.25MPa
贴附时的台面温度：80℃
贴附时的减压度：100Pa
[比较例1]
在下述的贴合条件下将半导体晶片与底层填充材料贴合，除此以外，与实施例1相同地制作了半导体装置。
<贴合条件>
贴附装置：商品名“DSA840-WS”日东精机株式会社制
贴附速度：5mm/min
贴附压力：0.25MPa
贴附时的台面温度：80℃
贴附时的减压度：1100Pa
[比较例2]
在半导体晶片与底层填充材料的贴合时没有减压(即在大气压下进行贴合)，除此以外，与实施例1相同地制作了半导体装置。
(最低熔融粘度的测定)
测定底层填充材料(热固化前)的最低熔融粘度。最低熔融粘度的测定是使用流变仪(HAAKE公司制、RS-1)，利用平行板法所测得的值。更详细而言，在缝隙100μm、旋转锥直径20mm、旋转速度10s-1、升温速度10℃/分钟的条件下，在从60℃至200℃的范围内测定熔融粘度，将在此时所得的从100℃至200℃的范围内的熔融粘度的最低值设为最低熔融粘度。将结果示于表3中。
(切割时的碎片飞散评价)
将样品数设为20个，将在切割时没有发生半导体芯片的碎片飞散的情况评价为“○”，将发生了碎片飞散的情况评价为“×”，将有无碎片飞散作为基准来评价半导体芯片的保持性。将结果示于表3中。
(拾取性评价)
将样品数设为20个，将在拾取时能够完全拾取的情况评价为“○”，将1个也无法拾取的情况评价为“×”，评价拾取性。将结果示于表3。
(空隙的产生的评价)
空隙的产生的评价是通过在实施例和比较例中所制作的半导体装置的半导体芯片与底层填充材料之间切断，使用图像识别装置(HamamatsuPhotonics公司制、商品名“C9597-11”)来观察剖面，算出空隙部分的总面积相对于底层填充材料的面积的比例而进行的。相对于剖面的观察图像中的底层填充材料的面积，将空隙部分的总面积为0～5％的情况评价“○”、将超过5％且25％以下的情况评价为“△”、将超过25％的情况评价为“×”。将结果示于表3。
[表3]
Figure BDA00002570898200381
由表3可知：在实施例所述的半导体装置的制造过程中，切割时的碎片飞散得到抑制、显示出良好的拾取性，并且空隙的产生受到了抑制。另一方面，在比较例1～2的半导体装置的制造过程中，碎片飞散和拾取性评价良好，但是产生了空隙。从在比较例1中减压条件超过1000Pa、另外在比较例2中没有进行减压处理的观点出发，可认为半导体晶片与底层填充材料之间的气泡没有充分减少，最终产生了空隙。由以上可知：作为半导体装置的制造工序，通过在1000Pa以下的减压下进行半导体晶片与底层填充材料的贴合，从而能够制造出空隙的产生被抑制的高可靠性的半导体装置。
符号说明
1、背面研磨用带
1a、基材
1b、粘合剂层
2、底层填充材料
3、半导体晶片
3a、半导体晶片的电路面
3b、半导体晶片的与电路面相反侧的面
4、凸点(连接构件)
5、半导体芯片(半导体元件)
6、被粘附体
7、导通件
10、密封片
20、半导体装置

Claims (9)

1.一种半导体装置的制造方法，所述半导体装置具备被粘附体、与该被粘附体电连接的半导体元件、和将该被粘附体与该半导体元件之间的空间填充的底层填充材料，
所述半导体装置的制造方法包括：
准备工序，准备具备支承材和层叠于该支承材上的底层填充材料的密封片，
热压接工序，使半导体晶片的形成有连接构件的电路面与所述密封片的底层填充材料在10000Pa以下的减压气氛、0.2MPa以上的按压、和40℃以上的热压接温度的条件下热压接，
切割工序，将所述半导体晶片切割而形成带有所述底层填充材料的半导体元件，和
连接工序，用所述底层填充材料将所述被粘附体与所述半导体元件之间的空间填充，并且经由所述连接构件将所述半导体元件与所述被粘附体电连接。
2.根据权利要求1所述的半导体装置的制造方法，其中，在所述贴合工序后的所述半导体晶片与所述底层填充材料的界面基本上不存在气泡。
3.根据权利要求1所述的半导体装置的制造方法，其中，在10～10000Pa的减压气氛、0.2～1MPa的按压、和40～120℃的热压接温度的条件下进行所述热压接工序。
4.根据权利要求1所述的半导体装置的制造方法，其中，热固化前的所述底层填充材料在所述热压接温度下的熔融粘度为20000Pa·s以下。
5.根据权利要求1所述的半导体装置的制造方法，其中，所述底层填充材料包含热塑性树脂和热固化性树脂。
6.根据权利要求5所述的半导体装置的制造方法，其中，所述热塑性树脂包含丙烯酸树脂，所述热固化性树脂包含环氧树脂和酚醛树脂。
7.根据权利要求1所述的半导体装置的制造方法，其中，所述底层填充材料的厚度T与所述连接构件的高度H之比T/H为0.5～2，T和H的单位都为μm。
8.根据权利要求1所述的半导体装置的制造方法，其中，所述支承材是基材。
9.根据权利要求1所述的半导体装置的制造方法，其中，所述支承材是具备基材和层叠于该基材上的粘合剂层的背面研磨用带或者切割带。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111954925A (zh) * 2018-03-30 2020-11-17 三井化学东赛璐株式会社 电子装置的制造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9136173B2 (en) * 2012-11-07 2015-09-15 Semiconductor Components Industries, Llc Singulation method for semiconductor die having a layer of material along one major surface
US9484260B2 (en) 2012-11-07 2016-11-01 Semiconductor Components Industries, Llc Heated carrier substrate semiconductor die singulation method
KR102165264B1 (ko) * 2013-10-10 2020-10-13 삼성전자 주식회사 아연 입자를 함유하는 비전도성 폴리머 막, 비전도성 폴리머 페이스트, 이들을 포함하는 반도체 패키지, 및 반도체 패키지의 제조 방법
KR101837511B1 (ko) 2016-04-04 2018-03-14 주식회사 네패스 반도체 패키지 및 그 제조방법
US10373869B2 (en) 2017-05-24 2019-08-06 Semiconductor Components Industries, Llc Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus
KR102480379B1 (ko) 2019-01-29 2022-12-23 주식회사 엘지화학 반도체 패키지의 제조방법
EP3780094A4 (en) * 2019-01-29 2022-03-30 Lg Chem, Ltd. SEMICONDUCTOR PACKAGE MANUFACTURING METHOD
JP7301468B2 (ja) 2019-04-17 2023-07-03 株式会社ディスコ 被加工物の加工方法、熱圧着方法
JP7132198B2 (ja) * 2019-09-27 2022-09-06 芝浦メカトロニクス株式会社 成膜装置及び埋込処理装置
JP7031830B2 (ja) 2020-03-31 2022-03-08 株式会社オリジン 貼合部材の製造方法及び貼合部材製造装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998028788A1 (en) * 1996-12-24 1998-07-02 Nitto Denko Corporation Manufacture of semiconductor device
US20020001688A1 (en) * 2000-05-23 2002-01-03 Hirotaka Ueda Sheet resin composition and process for manufacturing semiconductor device therewith
US8008122B1 (en) * 2010-09-21 2011-08-30 International Business Machines Corporation Pressurized underfill cure

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6796866B2 (en) * 1999-07-08 2004-09-28 California Institute Of Technology Silicon micromachined broad band light source
WO2006033315A1 (ja) * 2004-09-24 2006-03-30 Ibiden Co., Ltd. めっき方法及びめっき装置
US8399291B2 (en) * 2005-06-29 2013-03-19 Intel Corporation Underfill device and method
US20070298260A1 (en) * 2006-06-22 2007-12-27 Kuppusamy Kanakarajan Multi-layer laminate substrates useful in electronic type applications
JP5436901B2 (ja) * 2009-03-23 2014-03-05 三洋電機株式会社 太陽電池モジュールの製造方法
US8409918B2 (en) * 2010-09-03 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming pre-molded substrate to reduce warpage during die mounting
JP2012089750A (ja) * 2010-10-21 2012-05-10 Hitachi Chem Co Ltd 半導体封止充てん用熱硬化性樹脂組成物及び半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998028788A1 (en) * 1996-12-24 1998-07-02 Nitto Denko Corporation Manufacture of semiconductor device
US20020001688A1 (en) * 2000-05-23 2002-01-03 Hirotaka Ueda Sheet resin composition and process for manufacturing semiconductor device therewith
US8008122B1 (en) * 2010-09-21 2011-08-30 International Business Machines Corporation Pressurized underfill cure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111954925A (zh) * 2018-03-30 2020-11-17 三井化学东赛璐株式会社 电子装置的制造方法

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