CN103155139A - 制造三维结构存储元件的方法及装置 - Google Patents

制造三维结构存储元件的方法及装置 Download PDF

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CN103155139A
CN103155139A CN2011800489972A CN201180048997A CN103155139A CN 103155139 A CN103155139 A CN 103155139A CN 2011800489972 A CN2011800489972 A CN 2011800489972A CN 201180048997 A CN201180048997 A CN 201180048997A CN 103155139 A CN103155139 A CN 103155139A
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substrate
insulating barrier
memory element
dimensional structure
sacrifice layer
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CN103155139B (zh
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赵星吉
金海元
禹相浩
申承祐
张吉淳
吴完锡
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Eugene Technology Co Ltd
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Abstract

根据本发明的一实施例，制造垂直结构存储元件的方法包括：在基底上交替层叠一个以上绝缘层和一个以上牺牲层的步骤；形成贯通所述绝缘层和所述牺牲层的贯通孔的步骤；形成填充所述贯通孔的图形的步骤；形成贯通所述绝缘层和所述牺牲层的开口的步骤；以及通过所述开口供给蚀刻剂而去除所述牺牲层的步骤。其中，所述层叠绝缘层的步骤包括向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10群中的一种以上气体而蒸镀第一氧化硅膜的步骤。所述层叠牺牲层的步骤包括向所述基底供给二氯硅烷（SiCl2H2）而蒸镀第二氧化硅膜的步骤。

Description

制造三维结构存储元件的方法及装置
技术领域
本发明涉及一种制造存储元件的方法和装置，更详细地，涉及一种制造三维结构存储元件的方法和装置。
背景技术
对于电子产品而言，在要求体积变得越来越小的同时，还要求高容量数据的处理。因此，需要减小这种电子产品的存储元件体积的同时提高其集成度，在这一点上，考虑具有三维结构的存储元件来代替现有平面型结构。
发明内容
发明要解决的课题
本发明的目的在于，提供一种能够降低存储元件体积的存储元件的制造方法及装置。
本发明的其他目的在于，提供一种能够有效制造三维结构存储元件的方法及装置。
本发明的另外其他目的在于，提供一种能够防止在蒸镀多个薄膜的工序中由薄膜的应力差引起的基底变形的存储元件的制造方法及装置。
通过详细的说明和添加的附图，能够进一步明确本发明的一些其他目的。
解决课题的方法
根据本发明的一实施例，三维结构存储元件的制造方法包括：在基底上交替层叠一个以上绝缘层和一个以上牺牲层的步骤；形成贯通所述绝缘层和所述牺牲层的贯通孔的步骤；形成填充所述贯通孔的图形的步骤；形成贯通所述绝缘层和所述牺牲层的开口的步骤；以及通过所述开口供给蚀刻剂而去除所述牺牲层的步骤，其中，所述层叠绝缘层的步骤包括向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10群中的一种以上气体而蒸镀第一氧化硅膜的步骤，所述层叠牺牲层的步骤包括向所述基底供给二氯硅烷（SiCl2H2）而蒸镀第二氧化硅膜的步骤。
所述绝缘层和所述牺牲层对所述蚀刻剂具有刻蚀选择比（etchselectivity），所述牺牲层的蚀刻率为所述绝缘层的蚀刻率的五倍至三百倍以上。
所述蚀刻剂可以包含HF或者BOE中的任意一个。
所述层叠绝缘层的步骤进一步包括供给基于乙基的气体的步骤，所述第一氧化硅膜为SiCO（Silicon Carbon Oxide）。
所述层叠绝缘层的步骤进一步包括供给基于甲基的气体的步骤，所述第一氧化硅膜为SiCO（Silicon Carbon Oxide）。
所述基底的温度保持在300至790度，所述基底的加工压力保持在10mTorr至250Torr。
所述第一氧化硅膜和所述第二氧化硅膜可以具有互相不同的厚度。
所述交替层叠绝缘层和牺牲层的步骤进一步包括通过环形边对所述基底的边缘部施压的步骤。
所述基底的边缘部相当于从所述基底的边缘向所述基底的内侧0.5mm-3mm的范围。
所述环形边可以为陶瓷材料。
根据本发明的其他实施例，三维结构存储元件的制造方法包括：在基底上交替层叠一个以上绝缘层和一个以上牺牲层的步骤；形成贯通所述绝缘层和所述牺牲层的贯通孔的步骤；形成填充所述贯通孔的图形的步骤；形成贯通所述绝缘层和所述牺牲层的开口的步骤；以及通过所述开口供给蚀刻剂而去除所述牺牲层的步骤。其中，所述层叠绝缘层的步骤包括向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10群中的一种以上气体而蒸镀第一氧化硅膜的步骤。所述层叠牺牲层的步骤包括向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10、二氯硅烷（SiCl2H2）群中的一种以上气体和选自B2H6、PH3群中的一种以上气体而蒸镀注入有硼（boron）或者磷（phosphorus）的第二氧化硅膜的步骤。
根据本发明的一实施例，一种三维结构存储元件的制造装置，其用于在基底上交替层叠一个以上绝缘层和一个以上牺牲层而制造三维结构存储元件，所述制造装置包括：用于实行基底加工的腔室；设置于所述腔室内并用于放置所述基底的基底支撑台；以及喷头，当在所述基底上层叠所述绝缘层时，所述喷头向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10群中的一种以上气体，并且，当在所述基底上层叠所述牺牲层时，所述喷头向所述基底供给二氯硅烷（SiCl2H2）。
根据本发明的其他实施例，一种三维结构存储元件的制造装置，其用于在基底上交替层叠一个以上绝缘层和一个以上牺牲层而制造三维结构存储元件，所述制造装置包括：用于实行基底加工的腔室；设置于所述腔室内并用于放置所述基底的基底支撑台；以及喷头，当在所述基底上层叠所述绝缘层时，所述喷头向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10群中的一种以上气体，并且，当在所述基底上层叠所述牺牲层时，所述喷头向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10、二氯硅烷（SiCl2H2）群中的一种以上气体和选自B2H6、PH3群中的一种以上气体。
发明的效果
根据本发明的实施例，通过将存储元件形成为三维结构，能够降低存储元件的体积。并且，在基底上交替层叠形成绝缘层和牺牲层之后，在通过如多晶硅薄膜等图形来支撑绝缘层的状态下，能够有效地去除牺牲层，该图形作为半导体晶体管通道而使用。而且，能够防止在蒸镀多个薄膜的工序中由薄膜的应力差引起的基底变形。
附图说明
图1至图6是概略性地表示本发明一实施例的存储元件的制造方法的剖面图。
图7是表示基于乙基的气体的供给量和蒸镀的薄膜的蚀刻率的关系的图表。
图8是概略性地表示本发明一实施例的半导体制造装置的图。
图9是概略性地表示本发明其他实施例的存储元件制造装置的图。
图10是概略性地表示图9所示的环形边的立体图。
图11和图12是表示图9所示的环形边的动作的图。
具体实施方式
图1至图6是概略性地表示本发明一实施例的存储元件的制造方法的剖面图。以下，参考图1至图6说明存储元件的制造方法。
首先，如图1所示，可以提供基底105。基底105可以包含半导体物质，如IV族半导体、III-V族化合物半导体或者II-VI族氧化物半导体。例如，IV族半导体可以包含硅、锗或者硅锗。基底105可以作为块晶（bulk wafer）或者外延层被提供。
其次，可以在基底105的上部注入杂质，由此限定杂质区域110。接着，可以在基底105上交替层叠绝缘层115和牺牲层120。绝缘层115和牺牲层120可以形成为8×8或18×18、或者n×n的多层结构。在本实施例中，先层叠绝缘层115，最后层叠牺牲层120，但是根据需要可以改变绝缘层115和牺牲层120的层叠顺序。
绝缘层115可以是硅氧化膜（Silicon Dioxide，SiO2），其可以通过使供给在基底105上的硅烷（SiH4）和氧化氮（N2O）反应而形成。可以用Si2H6、Si3H8、Si4H10等来代替硅烷（SiH4）。同样，牺牲层120可以是硅氧化膜，其可以通过供给在基底105上的二氯硅烷（SiCl2H2）（DCS）和氧化氮（N2O）反应而形成。此外，与本实施例不同地，牺牲层120可以是向基底105上提供选自SiH4、Si2H6、Si3H8、Si4H10、二氯硅烷（SiCl2H2）群中的一种以上气体，和选自B2H6、PH3群中的一种以上气体而形成的硅氧化膜。在该情况下，可以向氧化硅膜上注入硼（boron）或者磷（phosphorus）（可以同时注入硼和磷）。
接着，如图2所示，可以通过蚀刻绝缘层115和牺牲层120来形成多个贯通孔125，贯通孔125贯通绝缘层115和牺牲层120。贯通孔125可以使用公知的光刻和蚀刻技术来形成。然后，通过公知的用于形成半导体晶体管的通道的形成工序（或者形成多晶硅薄膜的工序）来形成图形130，以填充贯通孔125。此时，图形130可以是中空的圆筒形状，同样，图形130贯通绝缘层115和牺牲层120。例如，图形130可以形成为多晶结构，或者也可以是单晶结构的外延层等薄膜形状。
其次，如图3所示，通过蚀刻图形130之间的绝缘层115和牺牲层120来形成开口135。开口135可以使用光刻和蚀刻技术来形成。
而后，如图4所示，可以去除牺牲层120。如上所述，绝缘层115可以是由硅烷形成的硅氧化膜。牺牲层120可以是由二氯硅烷形成的硅氧化膜；或可以是供给选自SiH4、Si2H6、Si3H8、Si4H10、二氯硅烷（SiCl2H2）群中的一种以上气体和选自B2H6、PH3群中的一种以上气体而形成的、注入有硼（boron）或者磷（phosphorus）（可以同时注入硼和磷）的硅氧化膜。以下表示由硅烷形成的硅氧化膜和由二氯硅烷而形成的硅氧化膜所具有的特性。
[表1]
薄膜 （As Dep）E/R（HF）100:1（A/sec）
硅烷-SiO2 8.8
DCS-SiO2 223
如上表1所示，牺牲层120相对绝缘层115具有刻蚀选择比（etchselectivity），牺牲层120的蚀刻率为绝缘层115的蚀刻率的二十倍左右。由此，当绝缘层115和牺牲层120以相同的时间露出于蚀刻剂时，已蚀刻的牺牲层120的大小是已蚀刻的绝缘层115的大小的二十倍以上，绝缘层115被蚀刻的程度非常小。如由二氯硅烷形成的硅氧化膜等的具有Cl基的硅氧化膜而言，其蒸镀薄膜的密度相对较低，因此表现出高的蚀刻率。
可以利用如上所述的原理去除牺牲层120。通过等向性蚀刻可以将蚀刻剂从开口135渗透至绝缘层115之间，等向性蚀刻可以包括湿法蚀刻或者化学干法蚀刻（chemical dry etch）。蚀刻剂可以包含HF或者BOE（缓冲氧化蚀刻剂：buffered oxide etch）中的任意一个。由此去除绝缘层115之间的牺牲层120，从而可以形成与开口135相连接的隧道140。图形130的侧壁通过隧道140露出。
然后，如图5所示，在通过开口（图8的135）和隧道（图8的140）而露出的绝缘层115和图形130侧壁上，形成存储介质150。就存储介质150而言，可以依次形成隧道绝缘层142、电荷存储层144和屏蔽绝缘层146。接着，可以在存储介质150上形成导电层155。例如，存储介质150和导电层155可以通过边角涂覆性高的化学气相沉积或者镀金法而形成。
之后，如图6所示，选择性地对通过开口（图4的135）露出的导电层（图5的155）进行蚀刻，由此可以形成接地选择栅电极（groundselect gate electrode）162、控制栅电极（control gate electrode）164以及线选择栅电极（string select gate electrode）166。
一方面，与本实施例不同地，可以与硅烷（SiH4）一起供给基于乙基的气体（例如，C2H4）或者基于甲基的气体（例如，CH3），由此，绝缘层115可以是SiCO（氧化碳硅：Silicon Carbon Oxide）薄膜。由SiCO薄膜形成的绝缘层115与如上所述的由二氯硅烷而形成的牺牲层120相比具有更大的刻蚀选择比，因此在去除牺牲层120的同时可以使受损伤的绝缘层115的量达到最小。图7是表示基于乙基的气体的供给量和蒸镀的薄膜的、蚀刻率关系的图表。如图7所示，可以确认随着基于乙基的气体的供给，蒸镀的薄膜的蚀刻率减小，由此可以根据需求调整相对牺牲层120的刻蚀选择比。
图8是概略性地表示本发明一实施例的半导体制造装置的图。如图8所示，半导体制造装置10具有用于导入源气体或者反应气体的导入部12，源气体或者反应气体通过导入部12而被导入，并通过喷头13向腔室11内部喷射。在进行加工时，硅烷或者二氯硅烷可以以1-1000sccm供给，反应气体（例如，N2O）可以以100-50000sccm供给。一方面，如上所述，当供给基于乙基的气体（例如，C2H4）或者基于甲基的气体（例如，CH3）时，可以以50至10000sccm供给。
作为加工对象的基底15被置于加热器14的上部，加热器14被支撑台16支撑。进行加工的过程中，加热器14能够将基底的温度保持在300至790度，此时腔室11内部的压力可以保持在10mTorr至250Torr。完成加工的基底15通过排出部17被排出于外部。
图9是概略性地表示本发明其他实施例的存储元件制造装置的图，图10是概略性地表示图9所示的环形边的立体图。以下仅对与图8不同的部分进行说明，可以用图8的说明代替省略的说明。
如图9所示，存储元件制造装置210具备设置于腔室211的内部的基底支撑台214，基底支撑台214由支撑台216支撑。如后文所述，基底支撑台214通过另行设置的驱动部（未图示）与支撑台216一起升降，由此，转换至基底215可以出入于腔室211内部的解除位置（参照图9）和对基底215进行加工的加工位置（参照图11）。
基底215通过形成于腔室211的侧壁的排出部217出入于腔室211的内部，通过排出部217向腔室211内部移动的基底215位于基底支撑台214的上部。基底支撑台214具有大于基底215的直径，基底215位于基底支撑台214的中央。此时，基底215由贯通基底支撑台214的顶杆（lift pin）220支撑，由此保持从基底支撑台214上升分离的状态。并且，喷头213设置于基底支撑台214的上部，源气体或者反应气体通过喷头213向腔室211的内部喷射。
一方面，腔室211进一步包括真空导向部（vacuum guide）212和环形边230。真空导向部212呈圆筒状，其设置于腔室211的内部。如图10所示，环形边230呈与腔室211的内部形状相对应的环状，环形边230具备支撑部232、水平支撑部234、垂直支撑部236、以及具有施压面238a的施压部238。环形边230位于基底支撑台214和喷头213之间并置于从真空导向部212的内侧壁突出的固定突起212a上。如图9所示，当基底支撑台214处于解除位置时，环形边230位于固定突起212a上，如下文所述，当基底支撑台214转换至加工位置时，环形边230离开固定突起212a而置于基底支撑台214的上部。
图11和图12是表示图9所示的环形边的动作的图。如上所述，基底支撑台214通过驱动部（未图示）与支撑台216一起升降，由此，可以转换至解除位置和加工位置。
如图12所示，水平支撑部234从支撑部232向腔室211的侧壁延伸，垂直支撑部236从支撑部232向下部延伸。施压部238从支撑部232向腔室211的内侧向下倾斜延伸。
如图9所示，当基底支撑台214处于解除位置时，可以通过水平支撑部234和垂直支撑部236使环形边230位于固定突起212a上，水平支撑部234与固定突起212a的上面相接触，垂直支撑部236与固定突起212a的侧面相接触。此时，支撑部232和施压部238保持向腔室211的内侧突出的状态。
如图11所示，当基底支撑台214转换至加工位置时，基底支撑台214通过位于基底215外侧的环状边缘部来提升环形边230，由此，环形边230离开固定突起212a而上升。此时，如图12所示，支撑部232邻接于基底支撑台214的边缘部，施压部238与置于基底支撑台214的基底215的边缘部相接触，从而对基底215的边缘部施压。即，环形边230在置于基底支撑台214的状态下，通过自身重量对基底215的边缘部施压，施压部238具有与基底215的边缘部相接触的施压面238a。
如先前通过图1进行的说明，当在基底上交替层叠互相不同的氧化硅时，由加工导致在两个氧化硅膜之间产生应力差，由此，引发基底变形（warpage，弯曲或者扭曲）。这种基底变形导致基底的边缘部从基底支撑台离开，从而基底变形成基底中心部凹陷的“U”字形。这将影响基底内的温度分布（基底中心与边缘之间）等，因此对加工均匀度（例如，蒸镀率）产生较大影响。实际可知：在完成如上所述的加工后，在基底边缘部测量的蒸镀率明显低于在基底中心部测量的蒸镀率。因此，为防止基底边缘部从基底支撑台离开而导致基底变形的现象，可以通过环形边230的施压部238对基底215的边缘部施压。
另一方面，如图12所示，被环形边230的施压部238施压的基底215的边缘部的宽度（w）可以是，从基底215的边缘向该基底215内侧约0.5mm至3mm的距离，由于该部分在实际半导体加工中并非是用于半导体器件的部分，因此不会影响半导体器件的收益率。另外，先前说明的施压面238a可以具有与边缘部相对应的宽度（w）。
如图12所示，环形边230可以只通过施压部238来保持被支撑在基底支撑台214上的状态，并且支撑部232可以保持从基底支撑台214的边缘部离开的状态（d）。在该情况下，环形边230的整体重量通过施压部238的施压面238a传递至基底215的边缘部，因此可以使环形边230的重量达到最小的同时将高的压力传递至基底215的边缘部。该原理可通过压力大小与接触面积的大小成反比的事实来理解。
产业上的可利用性
本发明可应用于各种形状的存储元件的制造方法和装置。

Claims (13)

1.一种三维结构存储元件的制造方法，其特征在于，所述方法包括：
在基底上交替层叠一个以上绝缘层和一个以上牺牲层的步骤；
形成贯通所述绝缘层和所述牺牲层的贯通孔的步骤；
形成填充所述贯通孔的图形的步骤；
形成贯通所述绝缘层和所述牺牲层的开口的步骤；以及
通过所述开口供给蚀刻剂而去除所述牺牲层的步骤，
其中，所述层叠绝缘层的步骤包括向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10群中的一种以上气体而蒸镀第一氧化硅膜的步骤，
所述层叠牺牲层的步骤包括向所述基底供给二氯硅烷（SiCl2H2）而蒸镀第二氧化硅膜的步骤。
2.权利要求1所述的三维结构存储元件的制造方法，其特征在于，所述绝缘层和所述牺牲层对所述蚀刻剂具有刻蚀选择比，所述牺牲层的蚀刻率为所述绝缘层的蚀刻率的五倍至三百倍以上。
3.权利要求1或2所述的三维结构存储元件的制造方法，其特征在于，所述蚀刻剂包含HF或者BOE中的任意一个。
4.权利要求1或2所述的三维结构存储元件的制造方法，其特征在于，所述层叠绝缘层的步骤进一步包括供给基于乙基的气体的步骤，所述第一氧化硅膜为SiCO。
5.权利要求1或2所述的三维结构存储元件的制造方法，其特征在于，所述层叠绝缘层的步骤进一步包括供给基于甲基的气体的步骤，所述第一氧化硅膜为SiCO。
6.权利要求1或2所述的三维结构存储元件的制造方法，其特征在于，所述基底的温度保持在300至790度，所述基底的加工压力保持在10mTorr至250Torr。
7.权利要求1或2所述的三维结构存储元件的制造方法，其特征在于，所述第一氧化硅膜和所述第二氧化硅膜具有互相不同的厚度。
8.权利要求1所述的三维结构存储元件的制造方法，其特征在于，所述交替层叠绝缘层和牺牲层的步骤进一步包括通过环形边对所述基底的边缘部施压的步骤。
9.权利要求8所述的三维结构存储元件的制造方法，其特征在于，所述基底的边缘部相当于从所述基底的边缘向所述基底的内侧0.5mm-3mm的范围。
10.权利要求8或9所述的三维结构存储元件的制造方法，其特征在于，所述环形边为陶瓷材料。
11.一种三维结构存储元件的制造方法，其特征在于，
所述方法包括：
在基底上交替层叠一个以上绝缘层和一个以上牺牲层的步骤；
形成贯通所述绝缘层和所述牺牲层的贯通孔的步骤；
形成填充所述贯通孔的图形的步骤；
形成贯通所述绝缘层和所述牺牲层的开口的步骤；以及
通过所述开口供给蚀刻剂而去除所述牺牲层的步骤，
其中，所述层叠绝缘层的步骤包括向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10群中的一种以上气体而蒸镀第一氧化硅膜的步骤，
所述层叠牺牲层的步骤包括向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10、二氯硅烷（SiCl2H2）群中的一种以上气体和选自B2H6、PH3群中的一种以上气体而蒸镀注入有硼或者磷的第二氧化硅膜的步骤。
12.一种三维结构存储元件的制造装置，其用于在基底上交替层叠一个以上绝缘层和一个以上牺牲层而制造三维结构存储元件，
其特征在于，所述制造装置包括：
用于实行基底加工的腔室；
设置于所述腔室内并用于放置所述基底的基底支撑台；以及
喷头，当在所述基底上层叠所述绝缘层时，所述喷头向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10群中的一种以上气体，并且，当在所述基底上层叠所述牺牲层时，所述喷头向所述基底供给二氯硅烷（SiCl2H2）。
13.一种三维结构存储元件的制造装置，其用于在基底上交替层叠一个以上绝缘层和一个以上牺牲层而制造三维结构存储元件，
其特征在于，所述制造装置包括：
用于实行基底加工的腔室；
设置于所述腔室内并用于放置所述基底的基底支撑台；以及
喷头，当在所述基底上层叠所述绝缘层时，所述喷头向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10群中的一种以上气体，并且，当在所述基底上层叠所述牺牲层时，所述喷头向所述基底供给选自SiH4、Si2H6、Si3H8、Si4H10、二氯硅烷（SiCl2H2）群中的一种以上气体和选自B2H6、PH3群中的一种以上气体。
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