WO2023050715A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2023050715A1
WO2023050715A1 PCT/CN2022/078665 CN2022078665W WO2023050715A1 WO 2023050715 A1 WO2023050715 A1 WO 2023050715A1 CN 2022078665 W CN2022078665 W CN 2022078665W WO 2023050715 A1 WO2023050715 A1 WO 2023050715A1
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WIPO (PCT)
Prior art keywords
storage
contact
lead
transistor
preset pattern
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PCT/CN2022/078665
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English (en)
French (fr)
Inventor
王晓光
曾定桂
李辉辉
邓杰芳
曹堪宇
Original Assignee
长鑫存储技术有限公司
北京超弦存储器研究院
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Priority to US17/808,797 priority Critical patent/US20230094859A1/en
Publication of WO2023050715A1 publication Critical patent/WO2023050715A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

Definitions

  • the present application relates to the technical field of integrated circuits, in particular to a semiconductor structure and a preparation method thereof.
  • Non-volatile memory has the characteristics of high-speed reading and writing, low power consumption, radiation resistance, and long data storage time. It has an irreplaceable position in fields with high reliability requirements, such as national defense and aerospace.
  • the embodiment of the present application provides a semiconductor structure and a manufacturing method thereof, which can optimize the manufacturing process of the non-volatile memory and achieve the purpose of reducing the production cost and process difficulty of the non-volatile memory.
  • a semiconductor structure comprising:
  • a plurality of storage elements are located on the first surface of the substrate, and the storage elements are arranged in a first preset pattern
  • a plurality of storage contact structures correspond to the storage elements one by one, and the bottoms of the storage contact structures are in contact with the tops of the storage elements, and the tops of the storage contact structures are arranged in a second preset pattern;
  • the bottom of the storage contact structure is opposite to the top of the storage contact structure.
  • the first preset figure includes a regular hexagon, and each storage element is located at the apex and the center of the regular hexagon.
  • the bottoms of the storage contact structures are arranged in a first preset pattern.
  • the second preset pattern includes a multi-row multi-column array.
  • the semiconductor structure further includes:
  • bit line structures any bit line structure is in contact with the top of the storage contact structure located in the same column, and the bit line structures are straight lines.
  • the semiconductor structure further includes:
  • a plurality of transistors are located between the substrate and the storage element, the transistors correspond to the storage elements one by one, and the transistors are arranged in a second preset pattern;
  • a plurality of transistor contact structures are located between the transistor and the storage element, are in contact with the transistor and the storage element respectively, and the tops of the transistor contact structures are arranged in a first preset pattern.
  • the bottom of the transistor contact structure is arranged in a second preset pattern
  • the bottom of the transistor contact structure is opposite to the top of the transistor contact structure.
  • the transistor contact structure includes:
  • first lead-out structure the bottom of the first lead-out structure is in contact with the transistor
  • the bottom of the second lead-out structure is in contact with the top of the first lead-out structure, and the top of the second lead-out structure is the top of the transistor contact structure;
  • the bottom of the first lead-out structure is set opposite to the top of the first lead-out structure
  • the bottom of the second lead-out structure is set opposite to the top of the second lead-out structure
  • the area of the bottom of the second extraction structure is not smaller than the area of the top of the first extraction structure.
  • the memory element includes a ferroelectric memory element, a magnetoresistive memory element, a resistive change memory element or a phase change memory element.
  • a method for preparing a semiconductor structure comprising:
  • the substrate has a first surface
  • a storage contact structure is formed on the top of each storage element, and the top of the storage contact structure is arranged in a second preset pattern.
  • the first preset figure includes a regular hexagon, and each storage element is located at the apex and the center of the regular hexagon.
  • the bottom of the storage contact structure is in contact with the top of the storage element, and the bottom of the storage contact structure is arranged in a first preset pattern
  • the bottom of the storage contact structure is opposite to the top of the storage contact structure.
  • the second preset pattern includes a multi-row multi-column array.
  • the method for preparing the semiconductor structure further includes:
  • a plurality of bit line structures are formed on the top of the storage contact structure, any bit line structure is in contact with the top of the storage contact structure in the same column, and the bit line structures are straight lines.
  • the substrate before forming the plurality of storage elements on the first surface of the substrate, it further includes:
  • the transistors correspond to the storage elements one by one, and the transistors are arranged in a second preset pattern;
  • a transistor contact structure is respectively formed on each transistor, and the transistor contact structure is respectively in contact with the transistor and the storage element, and the top of the transistor contact structure is arranged according to a first preset pattern.
  • the bottom of the transistor contact structure is arranged in a second preset pattern
  • the bottom of the transistor contact structure is opposite to the top of the transistor contact structure.
  • the transistor contact structure includes a first lead-out structure and a second lead-out structure
  • the step of forming the transistor contact structure on each transistor includes:
  • first lead-out structure Forming a first lead-out structure on each transistor respectively, the bottom of the first lead-out structure is in contact with the transistor;
  • the bottom of the first lead-out structure is opposite to the top of the first lead-out structure.
  • the area of the bottom of the second extraction structure is not smaller than the area of the top of the first extraction structure
  • the bottom of the second lead-out structure is opposite to the top of the second lead-out structure.
  • the bottom of the first lead-out structure is arranged in a second preset pattern, and the top of the second lead-out structure is arranged in a first preset pattern.
  • the above-mentioned semiconductor structure includes a plurality of storage elements located on the first surface of the substrate, the storage elements are arranged according to a first preset pattern, the plurality of storage contact structures correspond to the storage elements one by one, and the bottom of the storage contact structure is in contact with the storage elements.
  • the tops of the elements are in contact, and the tops of the storage contact structures are arranged in a second preset pattern.
  • the method for preparing the above semiconductor structure includes providing a substrate with a first surface, forming a plurality of storage elements arranged in a first preset pattern on the first surface of the substrate, forming a storage contact structure on the top of each storage element, and storing The tops of the contact structures are arranged in a second preset pattern.
  • device structures arranged according to the second preset pattern can be formed on the storage elements arranged according to the first preset pattern, and the arrangement shape of the storage elements has no effect on the arrangement or shape of the device structures formed on the storage elements.
  • the impact of the process is achieved to reduce the difficulty of the process and reduce the production cost.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure in an embodiment
  • FIG. 2 is a schematic top view of a storage element in a semiconductor structure after the storage element is formed in an embodiment
  • FIG. 3 is a schematic top view of a semiconductor structure in an embodiment
  • FIG. 4 is a schematic cross-sectional view of a storage element in an embodiment
  • FIG. 5 is a schematic flow diagram of a method for preparing a semiconductor structure in an embodiment
  • FIG. 6 is a schematic flow diagram of a method for preparing a semiconductor structure in another embodiment
  • FIG. 7 is a schematic flow chart of forming transistor contact structures on each transistor in an embodiment
  • FIG. 8 is a schematic cross-sectional view of a semiconductor structure after forming a transistor contact mask layer in an embodiment
  • FIG. 9 is a schematic cross-sectional view of the semiconductor structure after the transistor contact structure is formed in an embodiment corresponding to FIG. 8;
  • FIG. 10 is a schematic cross-sectional view of a semiconductor structure after forming a storage element in an embodiment corresponding to FIG. 9;
  • FIG. 11 is a schematic cross-sectional view of the semiconductor structure after forming a bit line mask layer in an embodiment corresponding to FIG. 10;
  • FIG. 12 is a schematic cross-sectional view of the semiconductor structure after forming the bit line structure in an embodiment corresponding to FIG. 11 .
  • first doping type becomes the second doping type
  • second doping type can be referred to as the first doping type
  • first doping type and the second doping type are different doping types, for example,
  • the first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type.
  • MRAM Magnetic Random Access Memory
  • the storage element of the storage unit in MRAM includes an upper electrode, a lower electrode, and a magnetic material between the upper electrode and the lower electrode. Pass current between them, write data into the memory cell, and the current flowing through the memory element generates a magnetic field, which can lead to wrong writing to non-target memory elements with a certain probability, and the probability of wrong writing depends on the coercivity of the memory element Magnetism (resistance to external magnetic fields) and the magnitude of the magnetic field, which is proportional to the inverse of the distance between the targeted storage element and the affected non-targeted storage element.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure in an embodiment.
  • a semiconductor structure is provided in this embodiment, including: a substrate 100, a plurality of storage elements 102, and a plurality of storage contact structures 104; the substrate 100 has The first surface: the storage elements 102 are located on the first surface of the substrate 100 , and the storage elements 102 are arranged in a first preset pattern, that is, the storage elements 102 are arranged in a first preset pattern on the first surface of the substrate 100 .
  • the storage contact structure 104 is located on the storage element 102, corresponding to the storage element 102 on the substrate 100, and the bottom of the storage contact structure 104 is in contact with the top of the storage element 102, and the top of the storage contact structure 104 is in a second preset pattern Arrangement, that is, the top of the storage contact structure 104 on the storage element 102 is arranged according to a second preset pattern, and the second preset pattern and the first preset pattern are respectively different patterns; wherein, the bottom of the storage contact structure 104 and The top of the storage contact structure 104 is arranged oppositely, that is, the bottom of the storage contact structure 104 and the top of the storage contact structure 104 are arranged in parallel.
  • the above-mentioned semiconductor structure includes a plurality of storage elements 102 located on the first surface of the substrate 100, the storage elements 102 are arranged according to a first preset pattern, a plurality of storage contact structures 104 correspond to the storage elements 102 one-to-one, and the storage contacts
  • the bottom of the structure 104 is in contact with the top of the storage element 102, and the top of the storage contact structure 104 is arranged in a second preset pattern.
  • the storage element 102 arranged in the first preset pattern can be formed according to the second preset pattern.
  • the device structure arranged in a preset pattern eliminates the influence of the arrangement shape of the storage element 102 on the arrangement or shape of the device structure formed on the storage element 102, so as to reduce the difficulty of the process and reduce the production cost.
  • FIG. 2 is a schematic top view of a storage element in a semiconductor structure after forming a storage element 102 in one embodiment.
  • the first preset pattern includes a regular hexagon, and each storage element 102 is located The vertices and centers of the polygons.
  • the bottoms of the storage contact structures 104 are arranged in a first preset pattern.
  • the area of the bottom of the storage contact structure 104 is larger than the area of the top of the storage element 102 . In other embodiments, the area of the bottom of the storage contact structure 104 is smaller than or equal to the area of the top of the storage element 102, through this setting, the process of forming the storage contact structure 104 can be avoided while satisfying the close contact between the storage contact structure 104 and the storage element 102 The storage element 102 is damaged.
  • the material of the storage contact structure 104 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide, wherein the metal can be tungsten (W) , nickel (Ni) or titanium (Ti); conductive metal nitrides include titanium nitride (TiN); conductive metal oxides include iridium oxide (I rO 2 ); metal silicides include titanium silicide (TiSi).
  • FIG. 3 is a schematic top view of a semiconductor structure in an embodiment. As shown in FIG. 3 , in one embodiment, the second preset pattern includes an array of multiple rows and multiple columns.
  • the semiconductor structure further includes: a plurality of bit line structures 106, any bit line structure 106 is in contact with the top of the storage contact structure 104 in the same column, and the bit line structure 106 is a straight line .
  • the length of the bit line structure 106 along the X direction is not less than the length of the top of the storage contact structure 104 along the X direction, and the X direction intersects the extending direction of the bit line structure 106 .
  • the semiconductor structure further includes: a plurality of transistors 108 and a plurality of transistor contact structures 110; the transistors 108 are located between the substrate 100 and the storage element 102, and the transistors 108 correspond to the storage elements 102 one-to-one ,
  • the transistor contact structure 110 is located between the transistor 108 and the storage element 102, and is in contact with the transistor 108 and the storage element 102 respectively, and the top of the transistor contact structure 110 is arranged in a first preset pattern.
  • the transistors 108 are arranged in a third preset pattern.
  • the third preset graphic includes an arrangement of the first preset graphic and the second preset graphic.
  • the arrangement shape of the transistors 108 can be set as required.
  • the transistors 108 are arranged in a first preset pattern, the arrangement of the transistors 108 and the storage elements 102 is the same.
  • the transistors 108 are arranged in the second preset pattern, the arrangement of the transistors 108 and the storage contact structure 104 is the same.
  • the bottom of the transistor contact structure 110 is arranged in a third preset pattern, and the bottom of the transistor contact structure 110 is arranged opposite to the top of the transistor contact structure 110, wherein the third preset pattern includes the first preset pattern Graphics, the second preset graphic layout.
  • the area of the top of the transistor contact structure 110 is larger than the area of the bottom of the memory element 102 . In other embodiments, the area of the top of the transistor contact structure 110 is smaller than or equal to the area of the bottom of the storage element 102 , which can eliminate the influence of process deviation on the contact resistance between the transistor contact structure 110 and the storage element 102 .
  • the transistor contact structure 110 includes: a first lead-out structure 202 and a second lead-out structure 204; the bottom of the first lead-out structure 202 is in contact with the transistor 108, and is used to lead out the transistor 108; example Preferably, the bottom of the first lead-out structure 202 is connected to the drain of the transistor 108, and is used to lead out the drain of the transistor 108.
  • the area of the bottom of the first lead-out structure 202 is equal to the area of the drain of the transistor 108;
  • the bottom of the lead-out structure 204 is in contact with the top of the first lead-out structure 202, wherein the bottom of the first lead-out structure 202 is opposite to the top of the first lead-out structure 202, and the bottom of the second lead-out structure 204 is in contact with the top of the second lead-out structure 204.
  • the tops are oppositely arranged, the bottom of the first lead-out structure 202 is the bottom of the transistor contact structure 110 , and the top of the second lead-out structure 204 is the top of the transistor contact structure 110 .
  • the bottom of the first lead-out structure 202 is arranged in a third preset pattern, and the top of the second lead-out structure 204 is arranged in a first preset pattern, for example, the bottom of the first lead-out structure 202 is arranged in a second preset pattern.
  • the top of the second lead-out structure 204 is arranged in a first preset pattern; or the bottom of the first lead-out structure 202 and the top of the second lead-out structure 204 are both arranged in a first preset pattern.
  • the area of the bottom of the second extraction structure 204 is not smaller than the area of the top of the first extraction structure 202 .
  • the part of the first lead-out structure 202 near the bottom of the second lead-out structure 204 is a trapezoidal structure.
  • the materials of the first lead-out structure 202 and the second lead-out structure 204 include one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein,
  • the metal can be tungsten (W), nickel (Ni) or titanium (Ti);
  • conductive metal nitrides include titanium nitride (TiN);
  • conductive metal oxides include iridium oxide (I rO 2 );
  • metal silicides include silicide Titanium (TiSi).
  • the material of at least one of the storage contact structure 104, the first lead-out structure 202 and the second lead-out structure 204 is different from the others, for example, the material of the first lead-out structure 202 is different from that of the storage contact structure 104, the second lead-out structure The material of 204 is different.
  • the storage contact structure 104 , the first lead-out structure 202 and the second lead-out structure 204 can also be prepared from the same material as required.
  • the memory element 102 includes a ferroelectric memory element, a magnetoresistive memory element, a resistive change memory element or a phase change memory element.
  • FIG. 4 is a schematic cross-sectional view of the storage element 102 in one embodiment.
  • the storage element 102 is a magnetoresistive storage element
  • the storage element 102 includes: a fixed layer 206, a non-magnetic isolation layer 208 and a free layer 210
  • the fixed layer 206 is located at the bottom of the storage element 102, That is, the pinned layer 206 is connected to the transistor contact structure 110 and has a magnetic field in a preset direction.
  • the pinned layer 206 has a thicker film layer and stronger magnetism, and the magnetic moment is not easily reversed.
  • the pinned layer The material of 206 includes CoFe, CoFeB, and typical fixed layer 206 is the lamination structure that is made of multi-layer film, and this lamination structure comprises seed layer (seed layer), [Co(x)/Pt(y) successively from bottom to top. )] m stack, Ru or Ir metal layer, [Co(x)/Pt(y)] m stack, Ta metal layer, CoFeB metal layer; non-magnetic isolation layer 208 is located between free layer 210 and pinned layer 206 , used to isolate the pinned layer 206 and the free layer 210.
  • seed layer seed layer
  • [Co(x)/Pt(y) successively from bottom to top. )
  • Ru or Ir metal layer [Co(x)/Pt(y)] m stack
  • Ta metal layer CoFeB metal layer
  • non-magnetic isolation layer 208 is located between free layer 210 and pinned layer 206 , used to isolate the pinned layer 206 and the free layer 210
  • the material of the non-magnetic isolation layer 208 includes MgO and Al 2 O 3 ; the free layer 210 is made of a soft ferromagnetic material, which has relatively low coercivity, high Permeability and high sensitivity to low magnetic field, the free layer 210 has weak magnetism and easy magnetic moment reversal.
  • the material of the free layer 210 includes CoFe, NiFe, NiFeCo, CoFeB.
  • the magnetoresistive storage element is a current control element, and the magnetization direction of the free layer 210 is controlled by the current flowing through the storage element 102.
  • the storage element 102 When the magnetization direction of the free layer 210 is consistent with the magnetization direction of the fixed layer 206, the storage element 102 is at a low resistance value state, the storage element 102 stores data as "0", when the magnetization direction of the free layer 210 is opposite to that of the pinned layer 206, the storage element 102 is in a high resistance state, and the storage element 102 stores data as "1".
  • the storage element 102 further includes a bottom electrode 212 located on the upper surface of the transistor contact structure 110 . It can be understood that, in some embodiments, the second lead-out structure 204 serves as the bottom electrode 212 of the storage element 102 at the same time.
  • the storage element 102 further includes a top electrode 214 located on the upper surface of the free layer 210 . It can be understood that, in some embodiments, the storage contact structure 104 serves as the top electrode 214 of the storage element 102 at the same time.
  • the memory element 102 further includes a protective layer 216 covering the sidewall of the pinned layer 206 and extending along the sidewall of the pinned layer 206 to cover the sidewall of the free layer 210 .
  • the material of the protection layer 216 is silicon nitride.
  • the semiconductor structure further includes: a plurality of word line structures 112 and a plurality of global source lines 114, the word line structures 112 are connected to the gate of the transistor 108, and the global source lines 114 are connected to Source connection of transistor 108 .
  • FIG. 5 is a schematic flow diagram of a method for preparing a semiconductor structure in an embodiment. As shown in FIGS. 1 and 5, the present application also provides a method for preparing a semiconductor structure, including:
  • a plurality of storage elements 102 are formed on the first surface of the substrate 100 , and each storage element 102 is arranged on the first surface of the substrate 100 according to a first preset pattern.
  • a storage contact structure 104 is formed on each storage element 102, the bottom of the storage contact structure 104 is in contact with the top of the storage element 102, the top of the storage contact structure 104 is arranged in a second preset pattern, and the second preset The pattern is different from the first preset pattern; wherein, the bottom of the storage contact structure 104 is opposite to the top of the storage contact structure 104 , that is, the bottom of the storage contact structure 104 is parallel to the top of the storage contact structure 104 .
  • the method for preparing the above-mentioned semiconductor structure includes providing a substrate 100 having a first surface, forming a plurality of storage elements 102 arranged in a first preset pattern on the first surface of the substrate 100, and forming storage elements 102 on top of each storage element 102 respectively.
  • the contact structure 104 and the top of the storage contact structure 104 are arranged in a second preset pattern.
  • the device structures arranged according to the second preset pattern can be formed on the storage elements 102 arranged according to the first preset pattern, and the arrangement shape of the storage elements 102 can eliminate the arrangement of the device structures formed on the storage elements 102.
  • the effect of cloth or shape can be achieved to reduce the difficulty of the process and reduce the production cost.
  • the first preset figure includes a regular hexagon, and each storage element 102 is located at the apex and center of the regular hexagon.
  • the bottom of the storage contact structure 104 is in contact with the top of the storage element 102, and the bottom of the storage contact structure 104 is arranged in a first preset pattern.
  • the area of the bottom of the storage contact structure 104 is greater than the area of the top of the storage element 102 . In other embodiments, the area of the bottom of the storage contact structure 104 is smaller than or equal to the area of the top of the storage element 102, through this setting, the process of forming the storage contact structure 104 can be avoided while satisfying the close contact between the storage contact structure 104 and the storage element 102 The storage element 102 is damaged.
  • the material of the storage contact structure 104 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide, wherein the metal can be tungsten (W) , nickel (Ni) or titanium (Ti); conductive metal nitrides include titanium nitride (TiN); conductive metal oxides include iridium oxide (I rO 2 ); metal silicides include titanium silicide (TiSi).
  • the second preset pattern includes an array of multiple rows and multiple columns.
  • the method for preparing a semiconductor structure further includes:
  • a plurality of bit line structures 106 are formed on the top of the storage contact structure 104, any bit line structure 106 is in contact with the top of the storage contact structure 104 in the same row, and the bit line structures 106 are straight lines.
  • the length of the bit line structure 106 along the X direction is not less than the length of the top of the storage contact structure 104 along the X direction, and the X direction intersects the extending direction of the bit line structure 106 .
  • Fig. 6 is a schematic flow chart of a method for preparing a semiconductor structure in another embodiment, as shown in Fig. 1 and Fig. 6, in one of the embodiments, before step S104, it also includes:
  • a plurality of transistors 108 are formed on the first surface of the substrate 100 , and the transistors 108 correspond to the storage elements 102 one by one.
  • the transistors 108 are arranged in a third preset pattern.
  • the third preset graphic includes an arrangement of the first preset graphic and the second preset graphic.
  • the arrangement shape of the transistors 108 can be set as required.
  • the transistors 108 are arranged in a first preset pattern, the arrangement of the transistors 108 and the storage elements 102 is the same.
  • the transistors 108 are arranged in the second predetermined pattern, the arrangement of the transistors 108 and the storage contact structure 104 is the same.
  • a transistor contact structure 110 is formed on each transistor 108, and the transistor contact structure 110 is in contact with the transistor 108 and the storage element 102 respectively, and the top of the transistor contact structure 110 is arranged in a first preset pattern.
  • the bottom of the transistor contact structure 110 is arranged in a third preset pattern, and the bottom of the transistor contact structure 110 is arranged opposite to the top of the transistor contact structure 110, wherein the third preset pattern includes the first preset pattern Graphics, the second preset graphic layout.
  • the area of the top of the transistor contact structure 110 is larger than the area of the bottom of the memory element 102 . In other embodiments, the area of the top of the transistor contact structure 110 is smaller than or equal to the area of the bottom of the storage element 102 , which can eliminate the influence of process deviation on the contact resistance between the transistor contact structure 110 and the storage element 102 .
  • FIG. 7 is a schematic flow diagram of forming a transistor contact structure on each transistor in an embodiment, as shown in FIG. 1 and FIG. Structure 204, step S204 includes:
  • the bottom of the first extraction structure 202 is in contact with the transistor 108, and is used to extract the transistor 108; exemplary, the bottom of the first extraction structure 202 is connected to the drain of the transistor 108, and is used to extract the drain of the transistor 108, Typically, the area of the bottom of the first extraction structure 202 is equal to the area of the drain of the transistor 108 .
  • the bottom of the first lead-out structure 202 is the bottom of the transistor contact structure 110
  • the top of the second lead-out structure 204 is the top of the transistor contact structure 110
  • the bottom of the first lead-out structure 202 is arranged in a third preset pattern
  • the top of the second lead-out structure 204 is arranged in a first preset pattern, for example, the bottom of the first lead-out structure 202 is arranged in a second preset pattern.
  • the top of the second lead-out structure 204 is arranged in a first preset pattern; or the bottom of the first lead-out structure 202 and the top of the second lead-out structure 204 are both arranged in a first preset pattern.
  • FIG. 8 is a schematic cross-sectional view of the semiconductor structure after forming a transistor contact mask layer in an embodiment
  • FIG. 9 is a schematic cross-sectional view of the semiconductor structure after forming a transistor contact structure in an embodiment corresponding to FIG. 8 .
  • a first contact structure 302 , a first conductive film 304 and a transistor contact mask layer 306 are sequentially formed on the substrate 100 on which the transistor 108 is formed, wherein the first contact structure 302 Connected to the drain of the transistor 108, the first dielectric layer 308 whose upper surface is flush with the upper surface of the first contact structure 302 is filled between adjacent first contact structures 302, and the first conductive film 304 is located on the first contact structure 302
  • the transistor contact mask layer 306 is located on the first conductive film 304 to define the shape and position of the transistor contact structure 110 .
  • the second dielectric layer 310 whose top surface is flush with the top surface of the second lead-out structures 204 is filled between adjacent second lead-out structures 204 .
  • the area of the bottom of the second extraction structure 204 is not smaller than the area of the top of the first extraction structure 202 ; wherein, the bottom of the second extraction structure 204 is opposite to the top of the second extraction structure 204 .
  • the part of the first lead-out structure 202 near the bottom of the second lead-out structure 204 is a trapezoidal structure.
  • the materials of the first lead-out structure 202 and the second lead-out structure 204 include one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein, Metals can be tungsten (W), nickel (Ni) or titanium (Ti); conductive metal nitrides include titanium nitride (TiN); conductive metal oxides include iridium oxide (I rO 2 ); metal silicides include silicide Titanium (TiSi).
  • Metals can be tungsten (W), nickel (Ni) or titanium (Ti); conductive metal nitrides include titanium nitride (TiN); conductive metal oxides include iridium oxide (I rO 2 ); metal silicides include silicide Titanium (TiSi).
  • the material of at least one of the storage contact structure 104, the first lead-out structure 202 and the second lead-out structure 204 is different from the others, for example, the material of the first lead-out structure 202 is different from that of the storage contact structure 104, the second lead-out structure The material of 204 is different.
  • the storage contact structure 104 , the first lead-out structure 202 and the second lead-out structure 204 can also be prepared from the same material as required.
  • the memory element 102 includes a ferroelectric memory element, a magnetoresistive memory element, a resistive change memory element or a phase change memory element.
  • the bottoms of the first lead-out structures 202 are arranged in a second preset pattern, and the tops of the second lead-out structures 204 are arranged in a first preset pattern.
  • FIG. 10 is a schematic cross-sectional view of the semiconductor structure after forming a storage element in an embodiment corresponding to FIG. 9;
  • FIG. 11 is a schematic cross-sectional view of the semiconductor structure after forming a bit line mask layer in an embodiment corresponding to FIG. 10;
  • FIG. 12 is a schematic cross-sectional view of the semiconductor structure in FIG. 11 A schematic cross-sectional view of the semiconductor structure after forming the bit line structure in a corresponding embodiment.
  • the third step is to form the storage element 102 on each second lead-out structure 204.
  • the steps of forming the storage element 102 are as follows, first A fixed layer structure is formed on the upper surface of the second lead-out structure 204 by a common deposition process, such as a physical vapor deposition process.
  • the fixed layer structure is a laminated structure composed of multi-layer thin films, including The seed layer, [Co(x)/Pt(y)] m stack, Ru or Ir metal layer, [Co(x)/Pt(y)] m stack, Ta metal layer, CoFeB metal layer; secondly, a non-magnetic isolation structure and a free layer structure are sequentially formed on the upper surface of the fixed layer structure.
  • the materials of the non-magnetic isolation structure include MgO and Al 2 O 3
  • the materials of the free layer structure include CoFe, NiFe, NiFeCo, CoFeB
  • the materials of the free layer structure include CoFe, NiFe, NiFeCo, CoFeB
  • perform a thermal annealing process and remove the redundant free layer structure, non-magnetic isolation structure and fixed layer structure through a photolithography process, and obtain the free layer 210 composed of the remaining free layer structure, the remaining non-magnetic
  • the non-magnetic isolation layer 208 formed by the magnetic isolation structure and the fixed layer 206 formed by the remaining fixed layer structure typically, the area of the bottom of the fixed layer 206 is equal to the area of the top of the second extraction structure 204 .
  • a protective structure such as a silicon nitride structure, is formed on the sidewalls of the fixed layer 206 , the nonmagnetic isolation layer 208 and the free layer 210 , and the protective structure extends along the sidewall of the free layer 210 to cover the upper surface of the free layer 210 .
  • a third dielectric structure is formed on the substrate 100, the third dielectric structure is filled between adjacent free layers 210, and the upper surface of the third dielectric structure is higher than the upper surface of the protection structure.
  • the protective structure directly above the free layer 210 and the third dielectric structure are removed by a photolithography process to obtain the storage contact trench 312 above the free layer 210, the protective layer 216 composed of the remaining protective structure, and the remaining third dielectric structure.
  • the third dielectric layer 314 formed by the dielectric structure.
  • the storage contact trench 312 is filled to form a storage contact layer 316 whose upper surface is flush with the upper surface of the third dielectric layer 314 .
  • a bit line structure layer 318 is formed on the upper surface of the third dielectric layer 314 .
  • the sixth step is to form a bit line mask layer 320 on the bit line structure layer.
  • the bit line mask layer 320 defines the shape and position of the bit line structure 106 and the storage contact structure 104.
  • the bit line mask layer 320 at this time is only used to define the shape and position of the bit line structure 106 .
  • the seventh step is to use the bit line mask layer 320 as a mask to remove part of the bit line structure layer, part of the storage contact layer 316, and part of the third dielectric layer 314 through an etching process to obtain a bit line structure composed of the remaining bit line structure layers 106 .
  • the storage contact structure 104 formed by the remaining storage contact layer 316 .
  • a fourth dielectric layer 322 whose upper surface is flush with the bit line contact structure is formed between adjacent bit line structures 106 .
  • the materials of the first dielectric layer 308 , the second dielectric layer 310 , the third dielectric layer 314 and the fourth dielectric layer 322 include silicon dioxide, silicon oxynitride, and silicon nitride.
  • Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application such that variations in the shapes shown as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
  • an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed.
  • the regions shown in the figures are schematic in nature and their shapes do not indicate the actual shape of a region of a device and are not intended to limit the scope of the application.

Abstract

本申请涉及一种半导体结构及其制备方法，包括：基底，具有第一表面；多个存储元件，位于基底的第一表面上，存储元件按第一预设图形排布；多个存储接触结构，与存储元件一一对应，且存储接触结构的底部与存储元件的顶部相接触，存储接触结构的顶部按第二预设图形排布；其中，存储接触结构的底部和存储接触结构的顶部相对设置。通过该设置使得按照第一预设图形排布的存储元件上可以形成按照第二预设图形排布的器件结构，消除存储元件的排布形状对存储元件上形成的器件结构的排布或形状的影响，达到降低工艺难度，降低生产成本的目的。

Description

半导体结构及其制备方法
本申请要求于2021年9月28日提交中国专利局，申请号为2021111449283，申请名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种半导体结构及其制备方法。
背景技术
非挥发性存储器具有高速读写、低功耗、抗辐射以及数据保存时间长等特点，对于可靠性要求高的领域，例如国防、航天航空等具有不可取代的地位。
随着半导体技术的发展，对非挥发性存储器的容量要求越来越高，为了提高非挥发性存储器的容量，需要密集地布置存储元件。但是，密集排布的存储元件限制了位线结构的形状，增加了非挥发性存储器的生产成本和工艺难度，如何降低非挥发性存储器的生产成本和工艺难度成为亟需解决的问题。
发明内容
本申请实施例提供了一种半导体结构及其制备方法，可以优化非挥发性存储器的制备流程，达到降低非挥发性存储器的生产成本和工艺难度的目的。
一种半导体结构，包括：
基底，具有第一表面；
多个存储元件，位于基底的第一表面上，存储元件按第一预设图形排布；
多个存储接触结构，与存储元件一一对应，且存储接触结构的底部与存储元件的顶部相接触，存储接触结构的顶部按第二预设图形排布；
其中，存储接触结构的底部和存储接触结构的顶部相对设置。
在其中一个实施例中，第一预设图形包括正六边形，各存储元件位于正六边形的顶点位置和中心位置。
在其中一个实施例中，存储接触结构的底部按第一预设图形排布。
在其中一个实施例中，第二预设图形包括多行多列排布阵列。
在其中一个实施例中，半导体结构还包括：
多个位线结构，任一位线结构与位于同一列的存储接触结构的顶部相接触，位线结构为直线。
在其中一个实施例中，半导体结构还包括：
多个晶体管，位于基底与存储元件之间，晶体管与存储元件一一对应，晶体管按第二预设图形排布；
多个晶体管接触结构，位于晶体管与存储元件之间，分别与晶体管、存储元件相接触，且晶体管接触结构的顶部按第一预设图形排布。
在其中一个实施例中，晶体管接触结构的底部按第二预设图形排布；
其中，晶体管接触结构的底部和晶体管接触结构的顶部相对设置。
在其中一个实施例中，晶体管接触结构包括：
第一引出结构，第一引出结构的底部与晶体管相接触；
第二引出结构，第二引出结构的底部与第一引出结构的顶部相接触，第二引出结构的顶部为晶体管接触结构的顶部；
其中，第一引出结构的底部和第一引出结构的顶部相对设置，第二引出结构的底部和第二引出结构的顶部相对设置。
在其中一个实施例中，第二引出结构的底部的面积不小于第一引出结构的顶部的面积。
在其中一个实施例中，存储元件包括铁电存储元件、磁阻存储元件、阻变存储元件或相变存储元件。
一种半导体结构的制备方法，包括：
提供基底，基底具有第一表面；
于基底的第一表面上形成多个存储元件，存储元件按第一预设图形排布；
于各存储元件的顶部分别形成存储接触结构，存储接触结构的顶部按第二预设图形排布。
在其中一个实施例中，第一预设图形包括正六边形，各存储元件位于正六边形的顶点位置和中心位置。
在其中一个实施例中，存储接触结构的底部与存储元件的顶部相接触，存储接触结构的底部按第一预设图形排布；
其中，存储接触结构的底部与存储接触结构的顶部相对设置。
在其中一个实施例中，第二预设图形包括多行多列排布阵列。
在其中一个实施例中，半导体结构的制备方法还包括：
于存储接触结构的顶部形成多个位线结构，任一位线结构与位于同一列的存储接触结构的顶部相接触，位线结构为直线。
在其中一个实施例中，于基底的第一表面上形成多个存储元件之前还包括：
于基底的第一表面形成多个晶体管，晶体管与存储元件一一对应，晶体管按第二预设图形排布；
于各晶体管上分别形成晶体管接触结构，晶体管接触结构分别与晶体管、存储元件相接触，且晶体管接触结构的顶部按第一预设图形排布。
在其中一个实施例中，晶体管接触结构的底部按第二预设图形排布；
其中，晶体管接触结构的底部和晶体管接触结构的顶部相对设置。
在其中一个实施例中，晶体管接触结构包括第一引出结构和第二引出结构，于各晶体管上分别形成晶体管接触结构的步骤包括：
于各晶体管上分别形成第一引出结构，第一引出结构的底部与晶体管相接触；
于第一引出结构的顶部形成第二引出结构，第二引出结构的顶部与存储元件的底部相接触；
其中，第一引出结构的底部和第一引出结构的顶部相对设置。
在其中一个实施例中，第二引出结构的底部的面积不小于第一引出结构的顶部的面积；
其中，第二引出结构的底部和第二引出结构的顶部相对设置。
在其中一个实施例中，第一引出结构的底部按第二预设图形排布，第二引出结构的顶部按第一预设图形排布。
上述半导体结构，包括多个存储元件，位于基底的第一表面上，存储元件按照第一预设图形排布，多个存储接触结构，与存储元件一一对应，且存储接触结构的底部与存储元件的顶部相接触，存储接触结构的顶部按第二预设图形排布，通过该设置使得按照第一预设图形排布的存储元件上可以形成按照第二预设图形排布的器件结构，消除存储元件的排布形状对存储元件上形成的器件结构的排布或形状的影响，达到降低工艺难度，降低生产成本的目的。
上述半导体结构的制备方法，包括提供具有第一表面的基底，于基底的第一表面形成 多个按照第一预设图形排布的存储元件，于各存储元件的顶部分别形成存储接触结构，存储接触结构的顶部按第二预设图形排布。通过该设置使得按照第一预设图形排布的存储元件上可以形成按照第二预设图形排布的器件结构，消除存储元件的排布形状对存储元件上形成的器件结构的排布或形状的影响，达到降低工艺难度，降低生产成本的目的。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中半导体结构的剖面示意图；
图2为一实施例中形成存储元件之后半导体结构中存储元件的俯视示意图；
图3为一实施例中半导体结构的俯视示意图；
图4为一实施例中存储元件的剖面示意图；
图5为一实施例中半导体结构的制备方法的流程示意图；
图6为另一实施例中半导体结构的制备方法的流程示意图；
图7为一实施例中于各晶体管上分别形成晶体管接触结构的流程示意图；
图8为一实施例中形成晶体管接触掩膜层后半导体结构的剖面示意图；
图9为图8对应的一实施例中形成晶体管接触结构之后半导体结构的剖面示意图；
图10为图9对应的一实施例中形成存储元件之后半导体结构的剖面示意图；
图11为图10对应的一实施例中形成位线掩膜层后半导体结构的剖面示意图；
图12为图11对应的一实施例中形成位线结构之后半导体结构的剖面示意图。
附图标记说明：
100、基底；102、存储元件；104、存储接触结构；106、位线结构；108、晶体管；110、晶体管接触结构；112、字线结构；114、全局源极线；202、第一引出结构；204、第二引出结构；206、固定层；208、非磁性隔离层；210、自由层；212、底部电极；214、顶部电极；216、保护层；302、第一接触结构；304、第一导电薄膜；306、晶体管接触掩膜层；308、第一介质层；310、第二介质层；312、存储接触沟槽；314、第三介质层；316、存储接触层；318、位线结构层；320、位线掩膜层；322、第四介质层。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书 中，术语“和/或”包括相关所列项目的任何及所有组合。
MRAM(磁性随机存储器)为非挥发性存储器，MRAM中存储单元的存储元件包括上电极、下电极及位于上电极与下电极之间的磁性材料，通过在目标存储元件的上电极和下电极之间传递电流，向存储单元中写入数据，流经存储元件的电流产生磁场，该磁场可以以特定概率导致向非目标存储元件的错误写入，错误写入的概率依赖于存储元件的矫顽磁性(对外部磁场的耐受性)和磁场的大小，而磁场的大小与目标存储元件和受影响的非目标存储元件之间的距离的倒数成比例。
为了在提高MRAM中存储元件的集成度的同时保证写入数据的准确性，MRAM中的存储元件的排布及其对存储元件上方器件结构的形状或位置的影响，决定了MRAM的生产成本及工艺难度。
图1为一实施例中半导体结构的剖面示意图，参见图1，在本实施例中提供一种半导体结构，包括：基底100、多个存储元件102、和多个存储接触结构104；基底100具有第一表面；存储元件102位于基底100的第一表面上，存储元件102按第一预设图形排布，即各存储元件102在基底100的第一表面上按照第一预设图形排布。存储接触结构104位于存储元件102上，与基底100上的存储元件102一一对应，并且存储接触结构104的底部与存储元件102的顶部相接触，存储接触结构104的顶部按第二预设图形排布，即存储元件102上的存储接触结构104的顶部按照第二预设图形排布，第二预设图形与第一预设图形分别为不同的图形；其中，存储接触结构104的底部和存储接触结构104的顶部相对设置，即存储接触结构104的底部和存储接触结构104的顶部平行设置。
上述半导体结构，包括多个存储元件102，位于基底100的第一表面上，存储元件102按照第一预设图形排布，多个存储接触结构104，与存储元件102一一对应，且存储接触结构104的底部与存储元件102的顶部相接触，存储接触结构104的顶部按第二预设图形排布，通过该设置使得按照第一预设图形排布的存储元件102上可以形成按照第二预设图形排布的器件结构，消除存储元件102的排布形状对存储元件102上形成的器件结构的排布或形状的影响，达到降低工艺难度，降低生产成本的目的。
图2为一实施例中形成存储元件102之后半导体结构中存储元件的俯视示意图，如图2所示，在其中一个实施例中，第一预设图形包括正六边形，各存储元件102位于正六边形的顶点位置和中心位置。
在其中一个实施例中，存储接触结构104的底部按第一预设图形排布。
在其中一个实施例中，存储接触结构104的底部的面积大于存储元件102的顶部的面 积。在其他实施例中，存储接触结构104的底部的面积小于或等于存储元件102的顶部的面积，通过该设置可以在满足存储接触结构104与存储元件102密切接触的同时避免形成存储接触结构104过程中损伤存储元件102。
在其中一个实施例中，存储接触结构104的材料包括多晶硅、金属、导电性金属氮化物、导电性金属氧化物和金属硅化物中的一种或多种，其中，金属可以是钨(W)、镍(Ni)或钛(Ti)；导电性金属氮化物包括氮化钛(TiN)；导电性金属氧化物包括氧化铱(I rO 2)；金属硅化物包括硅化钛(TiSi)。
图3为一实施例中半导体结构的俯视示意图，如图3所示，在其中一个实施例中，第二预设图形包括多行多列排布阵列。
继续参考图1，在其中一个实施例中，半导体结构还包括：多个位线结构106，任一位线结构106与位于同一列的存储接触结构104的顶部相接触，位线结构106为直线。示例性的，位线结构106沿X方向的长度不小于存储接触结构104的顶部沿X方向的长度，X方向与位线结构106的延伸方向相交。
继续参考图1，在其中一个实施例中，半导体结构还包括：多个晶体管108和多个晶体管接触结构110；晶体管108位于基底100与存储元件102之间，晶体管108与存储元件102一一对应，晶体管接触结构110位于晶体管108与存储元件102之间，分别与晶体管108、存储元件102相接触，且晶体管接触结构110的顶部按第一预设图形排布。
在其中一个实施例中，晶体管108按第三预设图形排布。可以理解的是，第三预设图形包括第一预设图形、第二预设图形排布。在实际应用中，可以根据需要设置晶体管108的排布形状。示例性的，当晶体管108按第一预设图形排布时，晶体管108与存储元件102的排布相同。当晶体管108按第二预设图形排布时，晶体管108与存储接触结构104的排布相同。
在其中一个实施例中，晶体管接触结构110的底部按第三预设图形排布，晶体管接触结构110的底部和晶体管接触结构110的顶部相对设置，其中，第三预设图形包括第一预设图形、第二预设图形排布。
在其中一个实施例中，晶体管接触结构110的顶部的面积大于存储元件102底部的面积。在其他实施例中，晶体管接触结构110的顶部的面积小于或等于存储元件102底部的面积，该设置可以消除工艺偏差对晶体管接触结构110与存储元件102之间接触电阻的影响。
继续参考图1，在其中一个实施例中，晶体管接触结构110包括：第一引出结构202 和第二引出结构204；第一引出结构202的底部与晶体管108相接触，用于引出晶体管108；示例性的，第一引出结构202的底部与晶体管108的漏极连接，用于引出晶体管108的漏极，典型的，第一引出结构202的底部的面积等于晶体管108的漏极的面积；第二引出结构204的底部与第一引出结构202的顶部相接触，其中，第一引出结构202的底部和第一引出结构202的顶部相对设置，第二引出结构204的底部和第二引出结构204的顶部相对设置，第一引出结构202的底部为晶体管接触结构110的底部，第二引出结构204的顶部为晶体管接触结构110的顶部。此时，第一引出结构202的底部按第三预设图形排布，第二引出结构204的顶部按第一预设图形排布，例如第一引出结构202的底部按第二预设图形排布，第二引出结构204的顶部按第一预设图形排布；或者第一引出结构202的底部和第二引出结构204的顶部均按照第一预设图形排布。
在其中一个实施例中，第二引出结构204的底部的面积不小于第一引出结构202的顶部的面积。
在其中一个实施例中，第一引出结构202靠近第二引出结构204底部的部分为梯形结构。
在其中一个实施例中，第一引出结构202、第二引出结构204的材料包括多晶硅、金属、导电性金属氮化物、导电性金属氧化物和金属硅化物中的一种或多种，其中，金属可以是钨(W)、镍(Ni)或钛(Ti)；导电性金属氮化物包括氮化钛(TiN)；导电性金属氧化物包括氧化铱(I rO 2)；金属硅化物包括硅化钛(TiSi)。示例性的，存储接触结构104、第一引出结构202和第二引出结构204中至少有一个结构的材料与其他不同，例如，第一引出结构202的材料与存储接触结构104、第二引出结构204的材料不同。在实际应用中，也可以根据需要选取相同的材料制备存储接触结构104、第一引出结构202和第二引出结构204。
在其中一个实施例中，存储元件102包括铁电存储元件、磁阻存储元件、阻变存储元件或相变存储元件。
图4为一实施例中存储元件102的剖面示意图。如图4所示，在本实施例中，存储元件102为磁阻存储元件，存储元件102包括：固定层206、非磁性隔离层208和自由层210，固定层206位于存储元件102的底部，即固定层206与晶体管接触结构110连接，具有预设方向的磁场，与自由层210相比，固定层206的膜层较厚、磁性较强，磁矩不易反转，示例性的，固定层206的材料包括CoFe、CoFeB，典型的固定层206是由多层薄膜构成的叠层结构，该叠层结构自下而上依次包括种子层(seed layer)、[Co(x)/Pt(y)] m叠层、Ru or  Ir金属层、[Co(x)/Pt(y)] m叠层、Ta金属层、CoFeB金属层；非磁性隔离层208位于自由层210与固定层206之间，用于隔离固定层206和自由层210，示例性的，非磁性隔离层208的材料包括MgO、Al 2O 3；自由层210选用软铁磁材料，具有比较低的矫顽力、高的磁导率和对低磁场的高敏感性，自由层210的磁性较弱、磁矩容易反转，示例性的，自由层210的材料包括CoFe、NiFe、NiFeCo、CoFeB。
磁阻存储元件为电流控制元器件，通过电流流过存储元件102来控制自由层210的磁化方向，当自由层210的磁化方向与固定层206的磁化方向一致时，存储元件102处于低阻值状态，存储元件102存储数据为“0”，当自由层210的磁化方向与固定层206的磁化方向相反时，存储元件102处于高阻值状态，存储元件102存储数据为“1”。
继续参考图4，在其中一个实施例中，存储元件102还包括底部电极212，底部电极212位于晶体管接触结构110的上表面。可以理解的是，在有些实施例中，第二引出结构204同时作为存储元件102的底部电极212。
继续参考图4，在其中一个实施例中，存储元件102还包括顶部电极214，顶部电极214位于自由层210的上表面。可以理解的是，在有些实施例中，存储接触结构104同时作为存储元件102的顶部电极214。
继续参考图4，在其他实施例中，存储元件102还包括保护层216，覆盖在固定层206的侧壁，且沿固定层206的侧壁延伸覆盖在自由层210的侧壁。示例性的，保护层216的材料为氮化硅。
继续参考图1，在其中一个实施例中，半导体结构还包括：多个字线结构112和多个全局源极线114，字线结构112与晶体管108的栅极连接，全局源极线114与晶体管108的源极连接。
图5为一实施例中半导体结构的制备方法的流程示意图，如图1、5所示，本申请还提供一种半导体结构的制备方法，包括：
S102，提供基底，基底具有第一表面。
S104，于基底的第一表面上形成多个按第一预设图形排布的存储元件。
如图1所示，在基底100的第一表面上形成多个个存储元件102，各存储元件102按第一预设图形排布在基底100的第一表面上。
S106，于各存储元件的顶部分别形成顶部按第二预设图形排布的存储接触结构。
具体的，在各存储元件102上分别形成存储接触结构104，存储接触结构104的底部与存储元件102的顶部相接触，存储接触结构104的顶部按第二预设图形排布，第二预设 图形与第一预设图形分别为不同的图形；其中，存储接触结构104的底部和存储接触结构104的顶部相对设置，即存储接触结构104的底部和存储接触结构104的顶部平行设置。
上述半导体结构的制备方法，包括提供具有第一表面的基底100，于基底100的第一表面形成多个按照第一预设图形排布的存储元件102，于各存储元件102的顶部分别形成存储接触结构104，存储接触结构104的顶部按第二预设图形排布。通过该设置使得按照第一预设图形排布的存储元件102上可以形成按照第二预设图形排布的器件结构，消除存储元件102的排布形状对存储元件102上形成的器件结构的排布或形状的影响，达到降低工艺难度，降低生产成本的目的。
如图2所示，在其中一个实施例中，第一预设图形包括正六边形，各存储元件102位于正六边形的顶点位置和中心位置。
在其中一个实施例中，存储接触结构104的底部与存储元件102的顶部相接触，存储接触结构104的底部按第一预设图形排布。
在其中一个实施例中，存储接触结构104的底部的面积大于存储元件102的顶部的面积。在其他实施例中，存储接触结构104的底部的面积小于或等于存储元件102的顶部的面积，通过该设置可以在满足存储接触结构104与存储元件102密切接触的同时避免形成存储接触结构104过程中损伤存储元件102。
在其中一个实施例中，存储接触结构104的材料包括多晶硅、金属、导电性金属氮化物、导电性金属氧化物和金属硅化物中的一种或多种，其中，金属可以是钨(W)、镍(Ni)或钛(Ti)；导电性金属氮化物包括氮化钛(TiN)；导电性金属氧化物包括氧化铱(I rO 2)；金属硅化物包括硅化钛(TiSi)。
如图3所示，在其中一个实施例中，第二预设图形包括多行多列排布阵列。
继续参考图1，在其中一个实施例中，半导体结构的制备方法还包括：
于存储接触结构104的顶部形成多个位线结构106，任一位线结构106与位于同一列的存储接触结构104的顶部相接触，位线结构106为直线。示例性的，位线结构106沿X方向的长度不小于存储接触结构104的顶部沿X方向的长度，X方向与位线结构106的延伸方向相交。
图6为另一实施例中半导体结构的制备方法的流程示意图，如图1、图6所示，在其中一个实施例中，步骤S104之前还包括：
S202，于基底的第一表面形成多个晶体管。
具体的，在基底100的第一表面形成多个晶体管108，晶体管108与存储元件102一 一对应。在其中一个实施例中，晶体管108按第三预设图形排布。可以理解的是，第三预设图形包括第一预设图形、第二预设图形排布。在实际应用中，可以根据需要设置晶体管108的排布形状。示例性的，当晶体管108按第一预设图形排布时，晶体管108与存储元件102的排布相同。当晶体管108按第二预设图形排布时，晶体管108与存储接触结构104的排布相同。
S204，于各晶体管上分别形成顶部按第一预设图形排布的晶体管接触结构。
具体的，在各晶体管108上分别形成晶体管接触结构110，晶体管接触结构110分别与晶体管108、存储元件102相接触，且晶体管接触结构110的顶部按第一预设图形排布。
在其中一个实施例中，晶体管接触结构110的底部按第三预设图形排布，晶体管接触结构110的底部和晶体管接触结构110的顶部相对设置，其中，第三预设图形包括第一预设图形、第二预设图形排布。
在其中一个实施例中，晶体管接触结构110的顶部的面积大于存储元件102底部的面积。在其他实施例中，晶体管接触结构110的顶部的面积小于或等于存储元件102底部的面积，该设置可以消除工艺偏差对晶体管接触结构110与存储元件102之间接触电阻的影响。
图7为一实施例中于各晶体管上分别形成晶体管接触结构的流程示意图，如图1、图7所示，在其中一个实施例中，晶体管接触结构110包括第一引出结构202和第二引出结构204，步骤S204包括：
S302，于各晶体管108上分别形成第一引出结构202，第一引出结构202的底部与晶体管108相接触。
具体的，第一引出结构202的底部与晶体管108相接触，用于引出晶体管108；示例性的，第一引出结构202的底部与晶体管108的漏极连接，用于引出晶体管108的漏极，典型的，第一引出结构202的底部的面积等于晶体管108的漏极的面积。
S304，于第一引出结构的顶部形成第二引出结构，第二引出结构的顶部与存储元件的底部相接触。
具体的，第一引出结构202的底部为晶体管接触结构110的底部，第二引出结构204的顶部为晶体管接触结构110的顶部。此时，第一引出结构202的底部按第三预设图形排布，第二引出结构204的顶部按第一预设图形排布，例如第一引出结构202的底部按第二预设图形排布，第二引出结构204的顶部按第一预设图形排布；或者第一引出结构202的底部和第二引出结构204的顶部均按照第一预设图形排布。
图8为一实施例中形成晶体管接触掩膜层后半导体结构的剖面示意图，图9为图8对应的一实施例中形成晶体管接触结构之后半导体结构的剖面示意图。
如图8、图9所示，第一步，在形成有晶体管108的基底100上依次形成第一接触结构302、第一导电薄膜304和晶体管接触掩膜层306，其中，第一接触结构302与晶体管108的漏极连接，相邻第一接触结构302之间填充有上表面与第一接触结构302上表面相齐平的第一介质层308，第一导电薄膜304位于第一接触结构302的上表面，晶体管接触掩膜层306位于第一导电薄膜304上，定义出晶体管接触结构110的形状和位置。第二步，首先以晶体管接触掩膜层306为掩膜通过刻蚀工艺去除部分第一导电薄膜304、部分第一接触结构302及部分第一介质层308，得到由剩余第一接触结构302构成的第一引出结构202，剩余第一导电薄膜304构成的第二引出结构204；可以理解的是，在某些实施例中，通过刻蚀工艺仅去除未被晶体管接触掩膜层306覆盖的第一导电薄膜304和第一接触结构302，形成第二引出结构204和第一引出结构202。其次，在相邻第二引出结构204之间填充上表面与第二引出结构204上表面相齐平的第二介质层310。
在其中一个实施例中，第二引出结构204的底部的面积不小于第一引出结构202的顶部的面积；其中，第二引出结构204的底部和第二引出结构204的顶部相对设置。
在其中一个实施例中，第一引出结构202靠近第二引出结构204底部的部分为梯形结构。
在其中一个实施例中，第一引出结构202、第二引出结构204的材料包括多晶硅、金属、导电性金属氮化物、导电性金属氧化物和金属硅化物中的一种或多种，其中，金属可以是钨(W)、镍(Ni)或钛(Ti)；导电性金属氮化物包括氮化钛(TiN)；导电性金属氧化物包括氧化铱(I rO 2)；金属硅化物包括硅化钛(TiSi)。示例性的，存储接触结构104、第一引出结构202和第二引出结构204中至少有一个结构的材料与其他不同，例如，第一引出结构202的材料与存储接触结构104、第二引出结构204的材料不同。在实际应用中，也可以根据需要选取相同的材料制备存储接触结构104、第一引出结构202和第二引出结构204。
在其中一个实施例中，存储元件102包括铁电存储元件、磁阻存储元件、阻变存储元件或相变存储元件。
在其中一个实施例中，第一引出结构202的底部按第二预设图形排布，第二引出结构204的顶部按第一预设图形排布。
图10为图9对应的一实施例中形成存储元件之后半导体结构的剖面示意图；图11为 图10对应的一实施例中形成位线掩膜层后半导体结构的剖面示意图；图12为图11对应的一实施例中形成位线结构之后半导体结构的剖面示意图。如图10、图11、图12所示，第三步，在各第二引出结构204上形成存储元件102，以存储元件102为磁阻存储元件来说，形成存储元件102的步骤如下，首先通过常见的沉积工艺，例如物理气相沉积工艺在第二引出结构204上表面形成固定层结构，示例性的，固定层结构由多层薄膜构成的叠层结构，包括自第二引出结构204上表面依次形成的种子层(seed layer)、[Co(x)/Pt(y)] m叠层、Ru or Ir金属层、[Co(x)/Pt(y)] m叠层、Ta金属层、CoFeB金属层；其次，在固定层结构的上表面依次形成非磁性隔离结构和自由层结构，示例性的，非磁性隔离结构的材料包括MgO、Al 2O 3，自由层结构的材料包括CoFe、NiFe、NiFeCo、CoFeB；再次，进行热退火工艺，并通过光刻刻蚀工艺去除多余的自由层结构、非磁性隔离结构和固定层结构，得到由剩余自由层结构构成的自由层210、剩余非磁性隔离结构构成的非磁性隔离层208和剩余固定层结构构成的固定层206；典型的，固定层206的底部的面积等于第二引出结构204的顶部的面积。然后在固定层206、非磁性隔离层208和自由层210的侧壁形成保护结构，例如氮化硅结构，所述保护结构沿自由层210的侧壁延伸覆盖在自由层210的上表面。再次，在基底100上形成第三介质结构，第三介质结构填充在相邻自由层210之间，且第三介质结构的上表面高于保护结构的上表面。再次，通过光刻刻蚀工艺去除自由层210正上方的保护结构及第三介质结构，得到位于自由层210上方的存储接触沟槽312、由剩余保护结构构成的保护层216以及由剩余第三介质结构构成的第三介质层314。第四步，在存储接触沟槽312中填充形成上表面与第三介质层314的上表面相齐平的存储接触层316。第五步，在第三介质层314的上表面形成位线结构层318。第六步，在位线结构层上形成位线掩膜层320，位线掩膜层320定义位线结构106、存储接触结构104的形状和位置，在其他实施例中，在第五步之前包括在第三介质层314的上表面形成用于定义存储接触结构104的形状和位置的存储掩膜层之后，通过光刻刻蚀工艺刻蚀去除部分存储接触层316，得到由剩余存储接触层316构成的存储接触结构104，此时的位线掩膜层320仅用于定义位线结构106的形状和位置。第七步，以位线掩膜层320为掩膜通过刻蚀工艺去除部分位线结构层、部分存储接触层316、部分第三介质层314，得到由剩余位线结构层构成的位线结构106、由剩余存储接触层316构成的存储接触结构104。第八步，在相邻位线结构106之间填充形成上表面与位线接触结构相齐平的第四介质层322。示例性的，第一介质层308、第二介质层310、第三介质层314和第四介质层322的材料包括二氧化硅、氮氧化硅、氮化硅。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本申请的范围。
在本说明书的描述中，参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体结构，包括：
    基底，具有第一表面；
    多个存储元件，位于所述基底的第一表面上，所述存储元件按第一预设图形排布；
    多个存储接触结构，与所述存储元件一一对应，且所述存储接触结构的底部与所述存储元件的顶部相接触，所述存储接触结构的顶部按第二预设图形排布；
    其中，所述存储接触结构的底部和所述存储接触结构的顶部相对设置。
  2. 根据权利要求1所述的半导体结构，其中，所述第一预设图形包括正六边形，各所述存储元件位于所述正六边形的顶点位置和中心位置。
  3. 根据权利要求1所述的半导体结构，其中，所述存储接触结构的底部按所述第一预设图形排布。
  4. 根据权利要求1所述的半导体结构，其中，所述第二预设图形包括多行多列排布阵列。
  5. 根据权利要求4所述的半导体结构，还包括：
    多个位线结构，任一所述位线结构与位于同一列的所述存储接触结构的顶部相接触，所述位线结构为直线。
  6. 根据权利要求1所述的半导体结构，还包括：
    多个晶体管，位于所述基底与所述存储元件之间，所述晶体管与所述存储元件一一对应，所述晶体管按所述第二预设图形排布；
    多个晶体管接触结构，位于所述晶体管与所述存储元件之间，分别与所述晶体管、所述存储元件相接触，且所述晶体管接触结构的顶部按所述第一预设图形排布。
  7. 根据权利要求6所述的半导体结构，其中，所述晶体管接触结构的底部按所述第二预设图形排布；
    其中，所述晶体管接触结构的底部和所述晶体管接触结构的顶部相对设置。
  8. 根据权利要求6所述的半导体结构，其中，所述晶体管接触结构包括：
    第一引出结构，所述第一引出结构的底部与所述晶体管相接触；
    第二引出结构，所述第二引出结构的底部与所述第一引出结构的顶部相接触，所述第二引出结构的顶部为所述晶体管接触结构的顶部；
    其中，所述第一引出结构的底部和所述第一引出结构的顶部相对设置，所述第二引出结构的底部和所述第二引出结构的顶部相对设置。
  9. 根据权利要求8所述的半导体结构，其中，所述第二引出结构的底部的面积不小于所述第一引出结构的顶部的面积。
  10. 根据权利要求1所述的半导体结构，其中，所述存储元件包括铁电存储元件、磁阻存储元件、阻变存储元件或相变存储元件。
  11. 一种半导体结构的制备方法，包括：
    提供基底，所述基底具有第一表面；
    于所述基底的第一表面上形成多个存储元件，所述存储元件按第一预设图形排布；
    于各所述存储元件的顶部分别形成存储接触结构，所述存储接触结构的顶部按第二预设图形排布。
  12. 根据权利要求11所述的制备方法，其中，所述第一预设图形包括正六边形，各所述存储元件位于所述正六边形的顶点位置和中心位置。
  13. 根据权利要求11所述的制备方法，其中，所述存储接触结构的底部与所述存储元件的顶部相接触，所述存储接触结构的底部按所述第一预设图形排布；
    其中，所述存储接触结构的底部与所述存储接触结构的顶部相对设置。
  14. 根据权利要求11所述的制备方法，其中，所述第二预设图形包括多行多列排布阵列。
  15. 根据权利要求14所述的制备方法，还包括：
    于所述存储接触结构的顶部形成多个位线结构，任一所述位线结构与位于同一列的所述存储接触结构的顶部相接触，所述位线结构为直线。
  16. 根据权利要求11所述的制备方法，其中，所述于所述基底的第一表面上形成多个存储元件之前还包括：
    于所述基底的第一表面形成多个晶体管，所述晶体管与所述存储元件一一对应，所述晶体管按所述第二预设图形排布；
    于各所述晶体管上分别形成晶体管接触结构，所述晶体管接触结构分别与所述晶体管、所述存储元件相接触，且所述晶体管接触结构的顶部按所述第一预设图形排布。
  17. 根据权利要求16所述的制备方法，其中，所述晶体管接触结构的底部按所述第二预设图形排布；
    其中，所述晶体管接触结构的底部和所述晶体管接触结构的顶部相对设置。
  18. 根据权利要求16所述的制备方法，其中，所述晶体管接触结构包括第一引出结构和第二引出结构，所述于各所述晶体管上分别形成晶体管接触结构的步骤包括：
    于各所述晶体管上分别形成第一引出结构，所述第一引出结构的底部与所述晶体管相接触；
    于所述第一引出结构的顶部形成第二引出结构，所述第二引出结构的顶部与所述存储元件的底部相接触；
    其中，所述第一引出结构的底部和所述第一引出结构的顶部相对设置。
  19. 根据权利要求18所述的制备方法，其中，所述第二引出结构的底部的面积不小于所述第一引出结构的顶部的面积；
    其中，所述第二引出结构的底部和所述第二引出结构的顶部相对设置。
  20. 根据权利要求19所述的制备方法，其中，所述第一引出结构的底部按所述第二预设图形排布，所述第二引出结构的顶部按所述第一预设图形排布。
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