CN103151312B - 一种在cmos源漏注入前进行多晶硅掺杂的方法 - Google Patents
一种在cmos源漏注入前进行多晶硅掺杂的方法 Download PDFInfo
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CN103151312B true CN103151312B (zh) | 2014-12-10 |
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CN104347370B (zh) * | 2013-07-23 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | 提高pmos器件栅极的负偏压温度稳定性方法 |
CN109346402A (zh) * | 2018-10-08 | 2019-02-15 | 西安微电子技术研究所 | 一种消除Polycide MOS工艺制程中WSix剥落的工艺和版图设计方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1065704A2 (en) * | 1999-07-01 | 2001-01-03 | Intersil Corporation | Low temperature coefficient resistor (TCRL) |
KR20050049154A (ko) * | 2003-11-21 | 2005-05-25 | 삼성전자주식회사 | 게이트 씨닝을 방지할 수 있는 씨모스 트랜지스터의제조방법 |
CN1889236A (zh) * | 2005-06-30 | 2007-01-03 | 中芯国际集成电路制造(上海)有限公司 | 多晶硅栅极掺杂方法 |
CN101295640A (zh) * | 2007-04-28 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | 一种dram的多晶硅栅极制作方法 |
CN101728426A (zh) * | 2008-10-28 | 2010-06-09 | 上海华虹Nec电子有限公司 | 多晶硅栅结构及其制作方法 |
CN102054696A (zh) * | 2009-10-29 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | 形成源漏极的方法 |
Family Cites Families (1)
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US7394155B2 (en) * | 2004-11-04 | 2008-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Top and sidewall bridged interconnect structure and method |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1065704A2 (en) * | 1999-07-01 | 2001-01-03 | Intersil Corporation | Low temperature coefficient resistor (TCRL) |
KR20050049154A (ko) * | 2003-11-21 | 2005-05-25 | 삼성전자주식회사 | 게이트 씨닝을 방지할 수 있는 씨모스 트랜지스터의제조방법 |
CN1889236A (zh) * | 2005-06-30 | 2007-01-03 | 中芯国际集成电路制造(上海)有限公司 | 多晶硅栅极掺杂方法 |
CN101295640A (zh) * | 2007-04-28 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | 一种dram的多晶硅栅极制作方法 |
CN101728426A (zh) * | 2008-10-28 | 2010-06-09 | 上海华虹Nec电子有限公司 | 多晶硅栅结构及其制作方法 |
CN102054696A (zh) * | 2009-10-29 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | 形成源漏极的方法 |
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