CN103094131B - 利用激光直接结构化的堆叠式封装体 - Google Patents
利用激光直接结构化的堆叠式封装体 Download PDFInfo
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- CN103094131B CN103094131B CN201210431122.7A CN201210431122A CN103094131B CN 103094131 B CN103094131 B CN 103094131B CN 201210431122 A CN201210431122 A CN 201210431122A CN 103094131 B CN103094131 B CN 103094131B
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Abstract
本文公开一种利用激光直接结构化的堆叠式封装体。堆叠式封装体包括附连到基板的晶粒。晶粒用激光直接结构化模制材料包封。激光直接结构化模制材料被激光激活以在激光直接结构化模制材料的顶表面和侧表面上形成电路走线。然后,电路走线经受金属化。然后,封装体附连到已金属化的电路走线,并经由已金属化的电路走线电连接到基板。
Description
技术领域
本申请涉及电子器件的封装。
背景技术
对于更小巧、紧凑、更廉价和特性丰富的诸如数码相机、数码摄像机、耳机、音乐播放器等电子器件的期望,驱使着对电路板的小型化和高效利用。
发明内容
本文公开一种利用激光直接结构化的堆叠式封装体。堆叠式封装体包括附连到基板的晶粒。晶粒用激光直接结构化模制材料包封。激光直接结构化模制材料被激光激活以在激光直接结构化模制材料的顶表面和侧表面上形成电路走线。然后,电路走线经受金属化。然后,封装体附连到已金属化的电路走线,并经由已金属化的电路走线电连接到基板。
附图说明
图1示出利用激光直接结构化(laser direct structuring)的堆叠式封装体的一实施方式;
图2A、2B以及2C示出利用激光直接结构化的堆叠式封装体的一实施方式的不同剖面和视图;
图3示出借助于晶粒结合和布线结合处理的堆叠式封装体基板的一实施方式和工艺视图;
图4示出借助于模制、电路构建(circuit creation)以及金属化处理的堆叠式封装体基板的一实施方式和工艺视图;
图5示出用于具有球栅阵列的非堆叠构造的借助于焊球附连和单个化的堆叠式封装体基板的一实施方式和工艺视图;
图6示出用于具有球栅阵列的预堆叠构造的借助于焊球附连和单个化的堆叠式封装体基板的一实施方式和工艺视图;
图7示出设有具有球栅阵列的预堆叠构造的堆叠式封装体的一实施方式的横剖视图;
图8示出设有具有球栅阵列的预堆叠倒装构造的堆叠式封装体的一实施方式的横剖视图;
图9是用于在非堆叠构造中利用激光直接结构化制成堆叠式封装体的示例流程图;以及
图10是用于在预堆叠构造中利用激光直接结构化制成堆叠式封装体的示例流程图。
具体实施方式
可以理解,已简化了利用激光直接结构化的堆叠式封装体的实施方式的附图和描述来解释相关元件以便于清楚理解,同时为了清楚起见,去除了典型电子封装中常见的很多其它元件。本领域技术人员可认识到在实现本发明时,其它元件和/或步骤也是期望的和/或需要的。然而,因为这些元件和步骤在本领域内是众所周知的,并且因为它们不便于更清楚理解本发明,因此本文不讨论这些元件和步骤。
本文所述的非限制性实施方式是关于电子器件的。阅读过这些教示后,在不偏离本文所述的主旨或范围情况下,其它器件、模块以及应用也可使用。利用激光直接结构化的堆叠式封装体可为了多种应用和用途而修改,但仍落入权利要求书的主旨和范围内。本文所述的和/或附图所示的多种实施方式和变型仅以举例方式呈现,并不对范围和主旨构成限制。虽然可关联特定实施方式进行描述,但本文所述可应用于利用激光直接结构化的堆叠式封装体的所有实施方式。
一般而言,图1示出利用激光直接结构化(laser direct structuring,LDS)的堆叠式封装体100的一实施方式。堆叠式封装体100可包括基板105,基板105的一个表面附连有晶粒110,另一表面上安装有焊球125。晶粒110可用模制互连器件(molded interconnectdevice,MID)模制材料115包封。举非限制性示例,MID模制材料115可为激光直接结构化模制材料。在MID模制材料115上构建电路走线120。第二封装体130可利用本文所述的很多可用技术安装到电路走线120。举非限制性示例,图1示出通过焊球135连接的第二封装体130。电路走线120提供第二封装体130和基板105之间的连接路径。
MID部件是利用高温热塑和结构化金属化的具有集成电路走线的注塑成型热塑部件。MID技术通过选择性金属化而将塑料部件和电路结合在一个部件中,并可利用LDS或双射模工艺(two shot molding process)实施。
一般而言,LDS工艺可使用掺杂有借助于激光激活的金属-塑料添加剂的热塑材料。形成模制物,然后在激光束击中塑料且金属添加剂形成微粗糙迹线的塑料上,激光划写电路走线。这种迹线的金属微粒形成用于后续金属化的核。在无电铜浴(electro-lesscopper bath)中,导体路径层在这些迹线上精确地产生。以此方式可完成利用镍和金的镀覆。LDS工艺名义上具有宽广范围的材料、在一个区域上的完全的三维性、以及适于由激光单元改变走线走向的灵活性。不同功能部件可由一个基本单元生产,且具有小于80微米直径的良好走线是可能的。
程序上,在一个实施方式中,LDS工艺名义上利用对商业上可购得的掺杂热塑性塑料的一次共射射出成型(one shot injection molding)。可激光激活的热塑性塑料掺杂有由激光束激活的特定添加剂。物理化学反应形成金属核。这些作用为用于还原铜镀覆的催化剂。除了激活,激光产生在显微镜下粗糙的表面,在金属化工艺中铜牢固地锚固到上述表面。下一步是对LDS部件即电路的金属化。走线的附加累积——典型地借助于无电铜浴达到5至8μm——之后,是利用镍和金的镀覆。
如图1所示,利用LDS的堆叠式封装体提供在封装体堆叠上完成封装的能力,并产生器件的有效3D集成。在非限制示例中,利用LDS的堆叠封装能够实现高密度逻辑器件和记忆器件堆叠在一起。这种竖向封装集成利用应用于封装的MID技术、特别通过利用用于转移模制工艺(transfer molding process)的MID模制材料而实现。而且,由于高度集成封装体,可实现小型化。这就产生具有小引脚尺寸的小形状因素产品。堆叠式封装体可减少主印刷电路板基板面,并可为了更快数据传输速率而提供较短互连。
图2A、2B和2C示出利用激光直接结构化的堆叠式封装体的一实施方式的不同剖面和视图。图2A示出基板205,基板205的一个表面附连有晶粒210,另一表面上安装有焊球225。也即,封装平台可为连接盘栅格阵列(LGA)、球栅阵列(BGA)、塑料球栅格阵列(PBGA)或类似平台。晶粒210可用LDS模制材料215包封。在用LDS模制材料215包封晶粒210之后,LDS模制材料215的表面可利用3D激光束激活,并用Ni/Au镀覆来镀覆以在LDS模制材料215上构建电路走线220。所述电路走线可将LDS模制材料215的顶表面和侧表面与基板205连接。图2B示出沿图2A所示实施方式的线A-A所截取的横剖面图。如图示,电路走线220可形成沿LDS模制材料215的顶表面和侧表面至基板205的多个连接路径。
图2C示出可堆叠在电路走线220上的封装体230。封装体230可为任何类型的封装体,并可包括,举非限制性示例而言,倒装芯片式封装体、芯片级封装体、布线结合式封装体、引线框架式封装体、表面贴装无源器件、无源部件、有源部件等。
图3-7示出用于利用LDS的堆叠式封装体的实施方式和工艺流程。图3示出基板带300,其可具有多个基板单元305。基板可为柔性条带、陶瓷、引线框架、诸如双马来酰亚胺三嗪(BT)或FR4材料等刚性基板。各基板单元305可具有顶表面310和底表面315。举非限制性示例而言,各基板单元305还可具有位于顶表面310上的布线结合垫320。布线结合垫320可以矩形格式设置以形成晶粒附连部分330。举非限制性示例而言,底表面310可具有焊球安装垫335。保护膜340可附连到底表面310以防护焊球安装垫335被进一步处理。在基板带高度处完成保护膜的附连。
晶粒345可放置于并利用布线350以布线结合方式附连到各基板单元305内的晶粒附连部分330。诸如本领域技术人员已知的倒装芯片结合技术和工艺等其它技术也可使用。这些技术可包括,举非限制性示例而言,热-压缩或热-音速倒装芯片结合技术。在基板带高度处完成晶粒附连。
图4示出借助于模制、电路构建以及金属化处理的堆叠式封装体基板的实施方式和工艺视图。图4示出基板单元400,基板单元400具有用模制物405覆盖的附连晶粒(不可见)。模制物405可利用本领域技术人员已知的模制转移(mold transfer)技术和工艺而实现。该模制物可为LDS模制物或其它MID模制材料。模塑转移可在带高度处完成,以提高效率并降低成本。
然后,模制物405可利用激光激活以在模制物405表面上构建电路410。然后,可将金属化处理应用于电路410以形成镀覆的电路走线415。然后,可将基板单元400翻转,并从底表面425移除保护膜420。
图5示出用于具有球栅阵列的非堆叠构造的借助于焊球附连和单个化的堆叠式封装体基板的实施方式和工艺视图。图5示出位于基板单元500的底表面510上的焊球安装垫505。焊球520利用本领域技术人员已知的焊球附连和回流焊技术和工艺附连到焊球安装垫505,以产生球栅阵列525。然后,可利用单个化以将非堆叠BGA基板单元535与非堆叠BGA基板带530分离。可利用本领域技术人员已知的技术和工艺完成单个化。
沿线B-B截取的非堆叠BGA基板单元535的横剖面图示出具有布线结合545晶粒550的基板540。晶粒550用金属化电路(不可见)模制材料555包封。然后,非堆叠BGA基板单元535可被发送到电子制造服务企业(EMS)以具有安装在BGA 525上和/或金属化电路模制材料555上的表面贴装部件(SMT)。本文上述的另一封装体也可附连到金属化电路模制材料555。
利用LDS的堆叠式封装体可提供灵活设计,这是因为这使得可与大多数封装体协作,并且与不同封装体供应商合作。它可使更快时间地上市,并且非重复性工程(NRE)工具作业可最小,因为这仅需要改变激光编程即可。全部测试封装体的能力消除了因晶粒成品率引起的良品晶粒(KGD)问题。增加的灵活性包括具有在电路板组装过程中在部件水平上的预堆叠式封装体或非堆叠式封装体以供EMS做最终堆叠的选择。利用LDS的堆叠式封装体可改善物流、提供供货灵活性、以及维持机密或独家占有信息。
图6示出用于具有球栅阵列的预堆叠构造的借助于焊球附连和单个化的堆叠式封装体基板的实施方式和工艺视图。图6示出预堆叠基板带600的预堆叠基板单元605,其中封装体610附连到金属化电路模制材料615。封装体610可利用本领域技术人员已知的倒装芯片结合技术和工艺附连。这些技术和工艺包括,举非限制性示例而言,热-压缩或热-音速倒装芯片结合技术、以及借助于导电环氧树脂的倒装芯片结合和利用各向异性导电胶(ACP)的倒装芯片结合。
预堆叠基板带600的底表面620可包括焊球安装垫625。如本文以上所述,焊球630利用本领域技术人员已知的焊球附连和回流焊技术和工艺附连到焊球安装垫625以产生球栅阵列635。然后,可利用单个化以将预堆叠BGA基板单元645与预堆叠BGA基板带640分离。可利用本领域技术人员已知的技术和工艺完成单个化。
图7示出沿图6的线C-C截取的预堆叠BGA基板单元700的横剖面图。预堆叠BGA基板单元700包括基板705,基板705具有与布线715以布线结合方式附连的晶粒710。举非限制性示例而言,布线715可为金线。晶粒710可用具有金属化电路720的模制材料715包封。封装体725可利用本领域技术人员已知的BGA附连730技术和工艺附连或安装在金属化电路720上。举非限制性示例而言,封装体725可为布线结合式封装体。SMT 735可利用本领域技术人员已知技术和工艺附连或安装在金属化电路720上。预堆叠基板单元700的底表面740可包括焊球745以形成球栅阵列。
图8示出预堆叠倒装芯片BGA基板单元800的横剖面图。预堆叠倒装芯片BGA基板单元800包括基板805,基板805具有与布线813以布线结合方式附连的晶粒810。举非限制性示例而言,布线815可为金线。晶粒810可用具有金属化电路820的模制材料815包封。封装体825可利用本领域技术人员已知的倒装芯片附连技术和工艺附连或安装在金属化电路820上。SMT 835可利用本领域技术人员已知技术和工艺附连或安装在金属化电路820上。预堆叠基板单元800的底表面840可包括焊球845以形成球栅阵列。
图9是用于在非堆叠构造中利用激光直接结构化制造堆叠式封装体的示例流程图900。基板可被处理以包括位于顶表面上的布线结合垫和晶粒附连部分与位于底表面上的焊球安装垫(910)。保护膜可附连到底表面(915)。将晶粒如上所述附连到基板(920)。晶粒可用LDS模制材料包封(925)。模制材料被激光激活以在模制材料上构建电路(930)。电路经受金属化(935)。从底表面移除保护膜(940)。焊球附连到焊球安装垫以产生BGA(945)。各基板单元从基板带单个化(950),并被发送到EMS以进行封装和SMT附连(955)。
图10是用于在预堆叠构造中利用激光直接结构化制造堆叠式封装体的示例流程图1000。基板可被处理以包括位于顶表面上的布线结合垫和晶粒附连部分与位于底表面上的焊球安装垫(1010)。保护膜可附连到底表面(1015)。晶粒如上所述附连到基板(1020)。晶粒可用LDS模制材料包封(1025)。模制材料被激光激活以在模制材料上构建电路(1030)。电路经受金属化(1035)。从底表面移除保护膜(1040)。封装体和/或SMT附连到模制物上的金属化电路(1045)。焊球附连到焊球安装垫以产生BGA(1050)。各基板单元从基板带单个化(1055)。
如本文所述,本文所述方法不局限于执行任何特定功能的任何特定元件,且所呈方法的一些步骤不一定需要按所示顺序发生。例如,在一些示例中,两个或更多个方法步骤可以不同顺序或同时发生。另外,所述方法的一些步骤可为可选的(即使未清楚阐明为可选的),因此可省略。本文所公开方法的这些以及其它变化,尤其在阅读了本文描述的堆叠式封装体的详述后,将易清楚,且这些以及其它变化将视为落入本发明的全部范围内。
虽然上文以特定结合形式描述了特征和元件,但各特征或元件可在不存在其它特征和元件的情况下单独使用,或以与其它特征和元件结合或不结合的各种形式使用。
Claims (20)
1.一种用于利用激光直接结构化制造堆叠式封装体的方法,包括:
制备具有至少一个晶粒的基板带;
用激光直接结构化模制材料包封各晶粒;
激光激活由位于至少一个晶粒上的所述激光直接结构化模制材料形成的至少一个表面,以在所述激光直接结构化模制材料上形成电路走线,其中,激光激活导致一形成金属核的物理化学反应,所述金属核为还原铜镀覆的催化剂;
利用所述金属核来还原铜镀覆所述电路走线,以形成金属化的电路走线,其中所述还原铜镀覆采用无电铜浴,所述无电铜浴通过所述金属核进行催化;以及
将封装体附连到已金属化的电路走线上。
2.如权利要求1所述的方法,还包括:
在与附连晶粒相对的表面上提供焊球安装垫。
3.如权利要求2所述的方法,还包括:
将焊球附连到所述焊球安装垫以形成球栅阵列。
4.如权利要求1所述的方法,还包括:
将保护膜附连到与附连晶粒相对的表面,所述保护膜防护焊球安装垫。
5.如权利要求1所述的方法,还包括:
从所述基板带单个化基板单元。
6.如权利要求5所述的方法,其中所述单个化步骤在金属化电路走线之后进行。
7.如权利要求1所述的方法,还包括:
将部件附连到所述已金属化的电路走线。
8.如权利要求1所述的方法,其中,所述封装体利用倒装芯片附连或球栅阵列附连之一附连。
9.一种激光直接结构化堆叠式封装体,包括:
基板;
激光直接结构化模制材料覆盖的晶粒,所述晶粒附连到所述基板,在所述激光直接结构化模制材料上形成金属化的电路走线,其中,通过激光激活所述激光直接结构化模制材料以形成作为还原铜镀覆的催化剂的金属核、且通过无电铜浴来还原铜镀覆激光直接结构化区域来形成所述金属化的电路走线,其中所述无电铜浴通过金属核进行催化;以及
封装体,所述封装体附连到所述已金属化的电路走线。
10.如权利要求9所述的激光直接结构化堆叠式封装体,还包括:
位于与附连晶粒相对的表面上的焊球安装垫。
11.如权利要求9所述的激光直接结构化堆叠式封装体,还包括:
位于与附连晶粒相对的表面上的球栅阵列。
12.如权利要求9所述的激光直接结构化堆叠式封装体,还包括:
附连到所述已金属化的电路走线的部件。
13.如权利要求9所述的激光直接结构化堆叠式封装体,其中,所述封装体利用倒装芯片附连或球栅阵列附连之一附连。
14.一种电子器件,包括:
基板,所述基板具有顶表面和底表面;
激光直接结构化模制材料覆盖的晶粒,所述晶粒附连到所述基板的顶表面,其中所述激光直接结构化模制材料包括在被激光激活时经历一物理化学反应以形成作为还原铜镀覆的催化剂的金属核的物质,
所述激光直接结构化模制材料的至少一个表面具有通过还原铜镀覆形成的金属化的电路走线,其中所述还原铜镀覆采用无电铜浴,所述无电铜浴通过所述金属核进行催化;以及
封装体,所述封装体附连到所述金属化电路走线。
15.如权利要求14所述的电子器件,还包括:
位于所述基板的底表面上的焊球安装垫。
16.如权利要求14所述的电子器件,还包括:
位于所述基板的底表面上的球栅阵列。
17.如权利要求14所述的电子器件,还包括:
附连到所述已金属化的电路走线的部件。
18.如权利要求14所述的电子器件,其中,所述封装体利用倒装芯片附连或球栅阵列附连之一附连。
19.如权利要求14所述的电子器件,还包括:
附连到位于所述基板的底表面上的球栅阵列的部件。
20.如权利要求14所述的电子器件,还包括:
附连到位于所述基板的底表面上的连接盘栅格阵列的部件。
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US13/286,366 US8642387B2 (en) | 2011-11-01 | 2011-11-01 | Method of fabricating stacked packages using laser direct structuring |
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Publication number | Priority date | Publication date | Assignee | Title |
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US8642387B2 (en) * | 2011-11-01 | 2014-02-04 | Flextronics Ap, Llc | Method of fabricating stacked packages using laser direct structuring |
CN103530673A (zh) * | 2013-07-25 | 2014-01-22 | 上海杉德金卡信息系统科技有限公司 | 一种基于lds技术的金融pci安全设计方法 |
TWI561132B (en) | 2013-11-01 | 2016-12-01 | Ind Tech Res Inst | Method for forming metal circuit, liquid trigger material for forming metal circuit and metal circuit structure |
KR102147354B1 (ko) | 2013-11-14 | 2020-08-24 | 삼성전자 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR102245003B1 (ko) | 2014-06-27 | 2021-04-28 | 삼성전자주식회사 | 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법 |
DE202014008843U1 (de) * | 2014-11-06 | 2014-11-24 | Rosenberger Hochfrequenztechnik Gmbh & Co. Kg | Leiterplattenanordnung |
US10383233B2 (en) * | 2015-09-16 | 2019-08-13 | Jabil Inc. | Method for utilizing surface mount technology on plastic substrates |
CN105140191B (zh) * | 2015-09-17 | 2019-03-01 | 中芯长电半导体(江阴)有限公司 | 一种封装结构及再分布引线层的制作方法 |
JP6691835B2 (ja) * | 2016-06-17 | 2020-05-13 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージの製造方法 |
IT201700055983A1 (it) * | 2017-05-23 | 2018-11-23 | St Microelectronics Srl | Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti |
CN107256847A (zh) * | 2017-05-27 | 2017-10-17 | 华天科技(昆山)电子有限公司 | 增加焊盘面积的芯片封装结构及其制作方法 |
TWI616999B (zh) * | 2017-07-20 | 2018-03-01 | 華騰國際科技股份有限公司 | 具有堆疊式積體電路晶片之記憶體製作方法 |
US10886199B1 (en) * | 2019-07-17 | 2021-01-05 | Infineon Technologies Ag | Molded semiconductor package with double-sided cooling |
US11302613B2 (en) | 2019-07-17 | 2022-04-12 | Infineon Technologies Ag | Double-sided cooled molded semiconductor package |
DE102020112879A1 (de) | 2020-05-12 | 2021-11-18 | Lpkf Laser & Electronics Aktiengesellschaft | Verbundstruktur mit zumindest einer elektronischen Komponente sowie ein Verfahren zur Herstellung einer solchen Verbundstruktur |
CN113078118A (zh) * | 2021-03-25 | 2021-07-06 | 福唐激光(苏州)科技有限公司 | 一种激光实现pop接合的方法及其pop结构 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1355568A (zh) * | 2000-11-27 | 2002-06-26 | 矽品精密工业股份有限公司 | 芯片堆叠封装结构 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7548430B1 (en) * | 2002-05-01 | 2009-06-16 | Amkor Technology, Inc. | Buildup dielectric and metallization process and semiconductor package |
US7633765B1 (en) * | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
DE102004049654B3 (de) * | 2004-10-11 | 2006-04-13 | Infineon Technologies Ag | Halbleiterbauteil mit Kunststoffgehäuse und Verfahren zur Herstellung desselben |
DE102004049663B3 (de) * | 2004-10-11 | 2006-04-13 | Infineon Technologies Ag | Kunststoffgehäuse und Halbleiterbauteil mit derartigem Kunststoffgehäuse sowie Verfahren zur Herstellung derselben |
DE102005006995B4 (de) * | 2005-02-15 | 2008-01-24 | Infineon Technologies Ag | Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben |
US8466542B2 (en) * | 2009-03-13 | 2013-06-18 | Tessera, Inc. | Stacked microelectronic assemblies having vias extending through bond pads |
EP2309535A1 (en) * | 2009-10-09 | 2011-04-13 | Telefonaktiebolaget L M Ericsson (Publ) | Chip package with a chip embedded in a wiring body |
US8354297B2 (en) * | 2010-09-03 | 2013-01-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die |
US8642387B2 (en) * | 2011-11-01 | 2014-02-04 | Flextronics Ap, Llc | Method of fabricating stacked packages using laser direct structuring |
-
2011
- 2011-11-01 US US13/286,366 patent/US8642387B2/en not_active Expired - Fee Related
-
2012
- 2012-10-29 EP EP12190418.9A patent/EP2590217A3/en not_active Ceased
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- 2014-01-02 US US14/146,376 patent/US9018749B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1355568A (zh) * | 2000-11-27 | 2002-06-26 | 矽品精密工业股份有限公司 | 芯片堆叠封装结构 |
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