CN113078118A - 一种激光实现pop接合的方法及其pop结构 - Google Patents
一种激光实现pop接合的方法及其pop结构 Download PDFInfo
- Publication number
- CN113078118A CN113078118A CN202110317838.3A CN202110317838A CN113078118A CN 113078118 A CN113078118 A CN 113078118A CN 202110317838 A CN202110317838 A CN 202110317838A CN 113078118 A CN113078118 A CN 113078118A
- Authority
- CN
- China
- Prior art keywords
- laser
- bonding
- substrate
- wire
- pop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004806 packaging method and process Methods 0.000 claims abstract description 9
- 229920000642 polymer Polymers 0.000 claims description 58
- 239000000758 substrate Substances 0.000 claims description 51
- 239000010410 layer Substances 0.000 claims description 50
- 238000007789 sealing Methods 0.000 claims description 13
- 239000000565 sealant Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 2
- 230000014509 gene expression Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 150000004696 coordination complex Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- CPBQJMYROZQQJC-UHFFFAOYSA-N helium neon Chemical compound [He].[Ne] CPBQJMYROZQQJC-UHFFFAOYSA-N 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明提供了一种激光实现POP接合的方法及其POP结构。其采用两个导线弧进行软性接合,相较于导电柱的刚性接合具有更高的适应度,可以匹配不同的芯片高度和封装体高度之间的接合。
Description
技术领域
本发明涉及半导体芯片封装测试领域,具体涉及一种激光实现POP接合的方法及其POP结构。
背景技术
对于堆叠封装结构,尤其是封装上封装结构(即POP结构),其上下连接往往通过导电柱进行电连接,往往需要刻蚀形成通孔然后填充导体形成,这样的形成方法结构较为单一,不利于上下互联的可靠性,容易产生上下电连接不对位的问题。
发明内容
基于解决上述问题,本发明提供了一种激光实现POP接合的方法,包括以下步骤:
(1)提供第一基板,所述第一基板的第一表面包括边缘位置的多个第一功能焊盘;
(2)在所述多个第一功能焊盘上接合导线形成多个第一导线弧;
(3)在所述多个第一导线弧上包覆可激光活化聚合物形成第一聚合物层;
(4)在所述第一基板的第一表面的中间位置上倒装第一芯片,形成第一封装体;
(5)重复上述步骤,形成第二封装体,所述第二封装体包括第二基板、多个第二功能焊盘、多个第二导线弧、第二聚合物层和第二芯片;
(6)将第一封装体和第二封装体接合,使得所述第一芯片通过一粘合层与第二芯片粘合,同时使得所述第一聚合物层和第二聚合物层直接接合形成第一接合部;
(7)激光照射所述第一接合部处,以使得所述第一聚合物和第二聚合物的可激光活化聚合物被活化形成第一导电接点,所述第一导电接点使得所述第一导线弧和第二导线弧电连接;
(8)在所述第一基板和所述第二基板之间填充密封剂形成第一密封层。
根据本发明的实施例,在所述第一基板上还包括至少一第一冗余焊盘,相较于所述多个第一功能焊盘,所述第一冗余焊盘更靠近第一基板的边缘位置;在步骤(2)中,还包括形成第三导线弧,所述第三导线弧的一端连接一第一功能焊盘,另一端连接第一冗余焊盘;其中,所述第三导线弧的高度低于所述第一导线弧的高度。
根据本发明的实施例,在步骤(3)中,还包括在所述第三导线弧上包覆可激光活化聚合物形成第三聚合物层;在步骤(7)中,还包括激光照射所述第三聚合物层,以使得所述第三聚合物层的可激光活化聚合物至少在靠近所述第一冗余焊盘的位置被活化形成导电部。
根据本发明的实施例,在步骤(8)之后还包括:沿所述多个第一功能焊盘和所述第一冗余焊盘之间切割,以使得所述第三导线弧被切断,进而使得导电部在被切割后的所述第一密封层的侧表面露出。
根据本发明的实施例,在所述第二基板的第二表面上还具有多个第三功能焊盘,还包括在所述多个第三功能焊盘上接合导线形成多个第四导线弧,以及在所述多个第四导线弧上包覆可激光活化聚合物形成第四聚合物层。
根据本发明的实施例,还包括在所述第二基板的第二表面的中间区域倒装第三芯片;在所述第二表面形成第二密封层并研磨,以使得所述第四聚合物层从所述第二密封层的上表面露出;以及激光照射第四聚合物层的露出部分,以使得在此处的第四聚合物的可激光活化聚合物被活化形成第二导电接点。
根据本发明的实施例,还包括利用第一导线将所述导电部与一封装基板电连接。
根据本发明的实施例,还包括利用第二导线将所述第二导电接点与一封装基板电连接。
本发明还提供了一种POP结构,其由上述的激光实现POP接合的方法制造形成。
附图说明
图1-11为本发明的激光实现POP接合的方法的流程示意图。
具体实施方式
本发明的实施例提供了一种便于接合上下封装体的激光实现POP接合的方法,其采用两个导线弧进行软性接合,相较于导电柱的刚性接合具有更高的适应度,可以匹配不同的芯片高度和封装体高度之间的接合。
下面结合图1-11详细介绍本发明的具体接合方法。
参见图1,首先提供第一基板1,该第一基板1可以是印刷电路板、DBC板等基板结构。在第一基板1的上表面具有多个第一功能焊盘2,该些功能焊盘2位于第一基板1的上表面的边缘位置。多个第一功能焊盘2阵列排布,其与后续的第一芯片电连接,实现电引出。
在第一基板1的上表面上还包括至少一个第一冗余焊盘5,第一冗余焊盘5不作为电连接的功能部件,其仅仅用于临时键合引线并在后续步骤被切除。多个第一功能焊盘2和第一冗余焊盘5可以是相同的结构和材料。
然后在多个第一功能焊盘2和第一冗余焊盘5上接合导线形成多个第一导线弧3以及至少一个第二导线弧4,其中第一导线弧3的高度大于第二导线弧4的高度。并且,第一导线弧3的两端分别接合至第一功能焊盘2上,其顶端直接作为电引出。而第二导线弧4的一端接合至第一功能焊盘2上,另一端接合至第一冗余焊盘5上。
俯视观察时,多个第一导线弧3和多个第二导线弧4形成为环绕第一基板1的边缘区域形状,且多个第一导线弧3和多个第二导线弧4不易过于柔软,其可以具有一定的刚性,以使得其在接合时利用弹性进行挤压接合。
接着,将第一基板1的上的第一导线弧3和第二导线弧4浸入至一可激光活化聚合物液体中,以使得在所述多个第一导线弧3上包覆可激光活化聚合物形成第一聚合物层6,在所述第二导线弧4上包覆可激光活化聚合物形成第二聚合物层7,具体参见图2。此可激光活化聚合物材料可以是常规的具有金属络合物的聚合物材料,其在激光烧蚀时,会被活化形成金属,例如铜、铝等。
在将第一导线弧3和第二导线弧4浸入至可激光活化聚合物液体中时,第一基板1的上表面应当不被该可激光活化聚合物覆盖,以实现其他焊盘的暴露。提起第一基板1,使得第一导线弧3和第二导线弧4的可激光活化聚合物被风干但是仍保留一定的粘性,即半固化状态。
进一步的,在第一基板1的上表面的中间区域利用多个焊球9倒装第一芯片8,具体参见图3,至此形成第一封装体。第一芯片8通过第一基板1的内部线路电连接至多个第一导线弧3和多个第二导线弧4。
重复上述步骤,形成第二封装体,参见图4,第二封装体包括第二基板11、多个第二功能焊盘12、多个第三导线弧13、第三聚合物层14和第二芯片15。第二封装体的结构与第一封装体的结构大致相同,第二封装体也可以包括冗余焊盘,第二芯片15通过多个第二焊球15倒装在第二基板11上。
接着,将第一基板1和第二基板11对准,使得第一封装体和第二封装体接合,在此,所述第一芯片8通过一粘合层17与第二芯片15粘合。同时,使得所述第一聚合物层6和第三聚合物层14直接接合形成第一接合部,在第一接合部,第一导线弧3和第三导线弧13弹性挤压接合,并且,第一导线弧3所围成的垂直面与第三导线弧13所围成的垂直面具有一定的角度,例如,60-90°,这样可以保证接合的可靠性。
接着参见图5,激光照射上述第一接合部处,以使得所述第一聚合物6和第三聚合物14的可激光活化聚合物被活化形成第一导电接点,所述第一导电接点18使得所述第一导线弧3和第三导线弧13电连接。该激光可以是二氧化碳激光器、氦氖激光器等,其照射角度可以是沿着第一基板1和第二基板11之间的角度实现。
此外,还包括激光照射所述第二聚合物层3,以使得所述第二聚合物层3的可激光活化聚合物至少在靠近所述第一冗余焊盘5的位置被活化形成第一导电部19。该第一导电部19靠近第一冗余焊盘5,该第一导电部19直接接触第二导线弧4。
在第一基板1和第二基板11之间填充密封剂形成第一密封层20。密封层20密封所述第一至第三导线弧以及第一芯片8和第二芯片15。该密封层20的材料可以是环氧树脂、聚酰亚胺等,具体参见图6。
进一步的,在所述第二基板11的上表面上还具有多个第三功能焊盘26,还包括在所述多个第三功能焊盘26上接合导线形成多个第四导线弧21,以及在所述多个第四导线弧21上包覆可激光活化聚合物形成第四聚合物层22。上述部件的形成方法可以参见第一封装体的形成方法,在此不再赘述。在第二基板11的上表面还包括至少一第二冗余焊盘27和第五导线弧23,第五导线弧23的一端接合第三功能焊盘26,另一端则接合至第二冗余焊盘27。在第五导线弧23上具有第五聚合物层24,第五聚合物层24的靠近第二冗余焊盘27的位置被活化形成第二导电部25。
接着,第三芯片28通过多个第三焊球29倒装于第二基板11的上表面的中间部分,并在第二基板11的上表面上覆盖第二密封层30。第二密封层30的材质与第一密封层20的材质相同,且第二密封层30覆盖所述第四导线弧21和第二导线弧24以及第三芯片28,参见图7。
参见图8,研磨所述第二密封层30,以使得第四导线弧21最顶部的第四聚合物层22或者第四导线弧21的最顶端被露出。
然后参见图9,沿所述多个第一功能焊盘2和所述第一冗余焊盘5之间切割,以使得所述第二导线弧7和第五导线弧23被切断,进而使得第一导电部19和第二导电部25分在被切割后的所述第一密封层20和第二密封层30的侧表面露出形成导电接点。
此外,为了保证接点31的电连接可靠性,还包括激光活化该位置的第四聚合物层22形成最终的接点32,该接点32具有更大的接触面积和更好的导电性。
最后,上述结构均可以被集成到一封装基板上,如图11所示。其中,第一导线33可以使得侧面的导电接点互联,第二导线34可以使得侧面的接点与封装基板电连接,第三导线则可以使得接点32与封装基板电连接。
本发明中使用的表述“示例性实施例”、“示例”等不是指同一实施例,而是被提供来着重描述不同的特定特征。然而,上述示例和示例性实施例不排除他们与其他示例的特征相组合来实现。例如,即使在另一示例中未提供特定示例的描述的情况下,除非另有陈述或与其他示例中的描述相反,否则该描述可被理解为与另一示例相关的解释。
本发明中使用的术语仅用于示出示例,而无意限制本发明。除非上下文中另外清楚地指明,否则单数表述包括复数表述。
虽然以上示出并描述了示例实施例,但对本领域技术人员将明显的是,在不脱离由权利要求限定的本发明的范围的情况下,可做出变型和改变。
Claims (9)
1.一种激光实现POP接合的方法,包括以下步骤:
(1)提供第一基板,所述第一基板的第一表面包括边缘位置的多个第一功能焊盘;
(2)在所述多个第一功能焊盘上接合导线形成多个第一导线弧;
(3)在所述多个第一导线弧上包覆可激光活化聚合物形成第一聚合物层;
(4)在所述第一基板的第一表面的中间位置上倒装第一芯片,形成第一封装体;
(5)重复上述步骤,形成第二封装体,所述第二封装体包括第二基板、多个第二功能焊盘、多个第二导线弧、第二聚合物层和第二芯片;
(6)将第一封装体和第二封装体接合,使得所述第一芯片通过一粘合层与第二芯片粘合,同时使得所述第一聚合物层和第二聚合物层直接接合形成第一接合部;
(7)激光照射所述第一接合部处,以使得所述第一聚合物和第二聚合物的可激光活化聚合物被活化形成第一导电接点,所述第一导电接点使得所述第一导线弧和第二导线弧电连接;
(8)在所述第一基板和所述第二基板之间填充密封剂形成第一密封层。
2.根据权利要求1所述的激光实现POP接合的方法,其特征在于:在所述第一基板上还包括至少一第一冗余焊盘,相较于所述多个第一功能焊盘,所述第一冗余焊盘更靠近第一基板的边缘位置;在步骤(2)中,还包括形成第三导线弧,所述第三导线弧的一端连接一第一功能焊盘,另一端连接第一冗余焊盘;其中,所述第三导线弧的高度低于所述第一导线弧的高度。
3.根据权利要求2所述的激光实现POP接合的方法,其特征在于:在步骤(3)中,还包括在所述第三导线弧上包覆可激光活化聚合物形成第三聚合物层;在步骤(7)中,还包括激光照射所述第三聚合物层,以使得所述第三聚合物层的可激光活化聚合物至少在靠近所述第一冗余焊盘的位置被活化形成导电部。
4.根据权利要求3所述的激光实现POP接合的方法,其特征在于:在步骤(8)之后还包括:沿所述多个第一功能焊盘和所述第一冗余焊盘之间切割,以使得所述第三导线弧被切断,进而使得导电部在被切割后的所述第一密封层的侧表面露出。
5.根据权利要求1所述的激光实现POP接合的方法,其特征在于:在所述第二基板的第二表面上还具有多个第三功能焊盘,还包括在所述多个第三功能焊盘上接合导线形成多个第四导线弧,以及在所述多个第四导线弧上包覆可激光活化聚合物形成第四聚合物层。
6.根据权利要求5所述的激光实现POP接合的方法,其特征在于:还包括在所述第二基板的第二表面的中间区域倒装第三芯片;在所述第二表面形成第二密封层并研磨,以使得所述第四聚合物层从所述第二密封层的上表面露出;以及激光照射第四聚合物层的露出部分,以使得在此处的第四聚合物的可激光活化聚合物被活化形成第二导电接点。
7.根据权利要求4所述的激光实现POP接合的方法,其特征在于:还包括利用第一导线将所述导电部与一封装基板电连接。
8.根据权利要求6所述的激光实现POP接合的方法,其特征在于:还包括利用第二导线将所述第二导电接点与一封装基板电连接。
9.一种POP结构,其由权利要求1-8任一项所述的激光实现POP接合的方法制造形成。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110317838.3A CN113078118A (zh) | 2021-03-25 | 2021-03-25 | 一种激光实现pop接合的方法及其pop结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110317838.3A CN113078118A (zh) | 2021-03-25 | 2021-03-25 | 一种激光实现pop接合的方法及其pop结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113078118A true CN113078118A (zh) | 2021-07-06 |
Family
ID=76610128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110317838.3A Pending CN113078118A (zh) | 2021-03-25 | 2021-03-25 | 一种激光实现pop接合的方法及其pop结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN113078118A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114792669A (zh) * | 2022-06-22 | 2022-07-26 | 甬矽半导体(宁波)有限公司 | 三维封装结构及其制作方法和电子设备 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140110162A1 (en) * | 2011-11-01 | 2014-04-24 | Flextronics Ap, Llc | Stacked packages using laser direct structuring |
FR3094137A1 (fr) * | 2019-03-20 | 2020-09-25 | Stmicroelectronics (Grenoble 2) Sas | Boîtier électronique comportant des pistes contactant des fils |
CN111883445A (zh) * | 2020-08-11 | 2020-11-03 | 济南南知信息科技有限公司 | 一种堆叠电子组件及其制造方法 |
CN111883444A (zh) * | 2020-08-11 | 2020-11-03 | 济南南知信息科技有限公司 | 一种多芯片堆叠封装及其制造方法 |
CN112018052A (zh) * | 2019-05-31 | 2020-12-01 | 英飞凌科技奥地利有限公司 | 具有可激光活化模制化合物的半导体封装 |
-
2021
- 2021-03-25 CN CN202110317838.3A patent/CN113078118A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140110162A1 (en) * | 2011-11-01 | 2014-04-24 | Flextronics Ap, Llc | Stacked packages using laser direct structuring |
FR3094137A1 (fr) * | 2019-03-20 | 2020-09-25 | Stmicroelectronics (Grenoble 2) Sas | Boîtier électronique comportant des pistes contactant des fils |
CN112018052A (zh) * | 2019-05-31 | 2020-12-01 | 英飞凌科技奥地利有限公司 | 具有可激光活化模制化合物的半导体封装 |
CN111883445A (zh) * | 2020-08-11 | 2020-11-03 | 济南南知信息科技有限公司 | 一种堆叠电子组件及其制造方法 |
CN111883444A (zh) * | 2020-08-11 | 2020-11-03 | 济南南知信息科技有限公司 | 一种多芯片堆叠封装及其制造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114792669A (zh) * | 2022-06-22 | 2022-07-26 | 甬矽半导体(宁波)有限公司 | 三维封装结构及其制作方法和电子设备 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5801448A (en) | Conductive lines on the back side of wafers and dice for semiconductor interconnects | |
US5627405A (en) | Integrated circuit assembly incorporating an anisotropic elecctrically conductive layer | |
US6353263B1 (en) | Semiconductor device and manufacturing method thereof | |
US5519936A (en) | Method of making an electronic package with a thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
JP3481444B2 (ja) | 半導体装置及びその製造方法 | |
US5633533A (en) | Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto | |
US7374969B2 (en) | Semiconductor package with conductive molding compound and manufacturing method thereof | |
JP2738568B2 (ja) | 半導体チップモジュール | |
US20090146314A1 (en) | Semiconductor Device | |
US6137162A (en) | Chip stack package | |
CN113078118A (zh) | 一种激光实现pop接合的方法及其pop结构 | |
CN116207067A (zh) | 大电流功率半导体器件的封装结构及其封装方法 | |
JPH11251363A (ja) | フリップチップ実装方法及びフリップチップ実装構造 | |
US7960214B2 (en) | Chip package | |
CN110677986A (zh) | 电路板结构 | |
JP3582513B2 (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
TWI378546B (en) | Substrate and package for micro bga | |
US5054680A (en) | Bonding electrical conductors | |
KR19990049144A (ko) | 칩 사이즈 반도체 패키지 및 그의 제조 방법 | |
US6624008B2 (en) | Semiconductor chip installing tape, semiconductor device and a method for fabricating thereof | |
TW201005903A (en) | Semiconductor package with holes through holes | |
KR100592785B1 (ko) | 칩 스케일 패키지를 적층한 적층 패키지 | |
CN211125640U (zh) | 一种封装结构、封装模块及计算机设备 | |
JP3457547B2 (ja) | 半導体装置およびその製造方法ならびにフィルムキャリア | |
JP3714127B2 (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20240426 |
|
AD01 | Patent right deemed abandoned |