CN103081103A - 制造斜坡-叠层芯片封装的固定装置 - Google Patents

制造斜坡-叠层芯片封装的固定装置 Download PDF

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Publication number
CN103081103A
CN103081103A CN2011800421931A CN201180042193A CN103081103A CN 103081103 A CN103081103 A CN 103081103A CN 2011800421931 A CN2011800421931 A CN 2011800421931A CN 201180042193 A CN201180042193 A CN 201180042193A CN 103081103 A CN103081103 A CN 103081103A
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semiconductor die
assembly
semiconductor
vertical
ramp
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CN2011800421931A
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Chinese (zh)
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J·A·哈拉达
R·J·德罗斯特
D·C·道格拉斯
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Oracle International Corp
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Oracle International Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/293—Configurations of stacked chips characterised by non-galvanic coupling between the chips, e.g. capacitive coupling
    • H—ELECTRICITY
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    • H10W99/00—Subject matter not provided for in other groups of this subclass
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
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    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/728—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

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  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Led Device Packages (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN2011800421931A 2010-09-01 2011-08-04 制造斜坡-叠层芯片封装的固定装置 Pending CN103081103A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/873,945 US8373280B2 (en) 2010-09-01 2010-09-01 Manufacturing fixture for a ramp-stack chip package using solder for coupling a ramp component
US12/873,945 2010-09-01
PCT/US2011/046517 WO2012030469A2 (en) 2010-09-01 2011-08-04 Manufacturing fixture for a ramp-stack chip package

Publications (1)

Publication Number Publication Date
CN103081103A true CN103081103A (zh) 2013-05-01

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US (1) US8373280B2 (https=)
EP (1) EP2612355B1 (https=)
JP (1) JP6000951B2 (https=)
KR (1) KR101807743B1 (https=)
CN (1) CN103081103A (https=)
TW (1) TWI517353B (https=)
WO (1) WO2012030469A2 (https=)

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CN105659382A (zh) * 2013-10-21 2016-06-08 甲骨文国际公司 用于控制堆叠裸片的位置的技术
CN111048479A (zh) * 2019-12-27 2020-04-21 华天科技（西安）有限公司 一种多芯片堆叠封装结构及其封装方法
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US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104603640A (zh) * 2013-09-05 2015-05-06 皇家飞利浦有限公司 辐射探测器元件
CN104603640B (zh) * 2013-09-05 2018-03-30 皇家飞利浦有限公司 辐射探测器元件
CN105659382A (zh) * 2013-10-21 2016-06-08 甲骨文国际公司 用于控制堆叠裸片的位置的技术
CN105659382B (zh) * 2013-10-21 2019-04-12 甲骨文国际公司 用于控制堆叠裸片的位置的技术
CN111048479A (zh) * 2019-12-27 2020-04-21 华天科技（西安）有限公司 一种多芯片堆叠封装结构及其封装方法
CN111048479B (zh) * 2019-12-27 2021-06-29 华天科技(南京)有限公司 一种多芯片堆叠封装结构及其封装方法
CN111554682A (zh) * 2020-05-18 2020-08-18 中国科学院微电子研究所 一种半导体器件及其制作方法
CN111554682B (zh) * 2020-05-18 2023-03-21 中国科学院微电子研究所 一种半导体器件及其制作方法

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JP6000951B2 (ja) 2016-10-05
KR20130105819A (ko) 2013-09-26
KR101807743B1 (ko) 2017-12-13
EP2612355B1 (en) 2021-06-30
WO2012030469A3 (en) 2012-05-10
TWI517353B (zh) 2016-01-11
US8373280B2 (en) 2013-02-12
TW201220464A (en) 2012-05-16

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